PD - 95618
IRF3007PbF
AUTOMOTIVE MOSFET
Typical Applications
l
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HEXFET® Power MOSFET
42 Volts Automotive Electrical Systems
Lead-Free
D
VDSS = 75V
Features
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Ultra Low On-Resistance
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
Automotive [Q101] Qualified
RDS(on) = 0.0126Ω
G
ID = 75A
S
Description
Specifically designed for Automotive applications, this
design of HEXFET® Power MOSFETs utilizes the
lastest processing techniques to achieve extremely low
on-resistance per silicon area. Additional features of
this HEXFET power MOSFET are a 175°C junction
operating temperature, fast switching speed and
improved repetitive avalanche rating. These combine
to make this design an extremely efficient and reliable
device for use in Automotive applications and a wide
variety of other applications.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
EAS
EAS (6 sigma)
IAR
EAR
TJ
TSTG
Max.
Continuous Drain Current, VGS @ 10V (Silicon limited)
Continuous Drain Current, VGS @ 10V (See Fig.9)
Continuous Drain Current, VGS @ 10V (Package limited)
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
Repetitive Avalanche Energy
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Units
80
56
75
320
200
1.3
± 20
280
946
See Fig.12a, 12b, 15, 16
A
W
W/°C
V
mJ
A
mJ
-55 to + 175
°C
300 (1.6mm from case )
1.1 (10)
N•m (lbf•in)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
Units
–––
0.50
–––
0.74
–––
62
°C/W
1
8/2/04
IRF3007PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
75
–––
–––
2.0
180
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.084
10.5
–––
–––
–––
–––
–––
–––
89
21
30
12
80
55
49
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
3270
520
78
3500
340
640
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
12.6 mΩ VGS = 10V, ID = 48A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 25V, ID = 48A
20
VDS = 75V, VGS = 0V
µA
250
VDS = 60V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
130
ID = 48A
32
nC
VDS = 60V
45
VGS = 10V
–––
VDD = 38V
–––
ID = 48A
ns
–––
RG = 4.6Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 80
showing the
A
G
integral reverse
––– ––– 320
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 48A, VGS = 0V
––– 85 130
ns
TJ = 25°C, IF = 48A, VDD = 38V
––– 280 420
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
Starting TJ = 25°C, L = 0.24mH
Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 48A, VGS=10V (See Figure 12).
avalanche performance.
ISD ≤ 48A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS,
This
value determined from sample failure population. 100%
TJ ≤ 175°C
tested to this value in production.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRF3007PbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
4.5V
20µs PULSE WIDTH
Tj = 25°C
1
0.1
1
10
100
4.5V
10
20µs PULSE WIDTH
Tj = 175°C
1
0.1
100
1
VDS, Drain-to-Source Voltage (V)
100
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
100
Gfs, Forward Transconductance (S)
ID, Drain-to-Source Current ( A)
10
VDS, Drain-to-Source Voltage (V)
T J = 175°C
10
T J = 25°C
VDS = 25V
20µs PULSE WIDTH
1
4.0
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
T J = 175°C
80
60
T J = 25°C
40
20
VDS = 25V
20µs PULSE WIDTH
0
0
40
80
120
160
ID, Drain-to-Source Current (A)
Fig 4. Typical Forward Transconductance
Vs. Drain Current
3
IRF3007PbF
6000
Crss
Coss
4000
= Cgd
= Cds + Cgd
Ciss
3000
2000
1000
16
12
8
4
Coss
Crss
0
1
0
10
0
100
10000
ID, Drain-to-Source Current (A)
1000.0
100.0
TJ = 175°C
10.0
1.0
T J = 25°C
0.1
0.2
0.4
0.6
0.8
1.0
1.2
VGS = 0V
1.4
80
120
160
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
ISD, Reverse Drain Current (A)
40
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
1.6
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 60V
VDS= 38V
VDS= 15V
ID= 48A
VGS , Gate-to-Source Voltage (V)
5000
C, Capacitance (pF)
20
VGS = 0V,
f = 1 MHZ
C iss
= C gs + C gd , C ds
SHORTED
1000
100
100µsec
10
1
0.1
1.8
OPERATION IN THIS AREA
LIMITED BY RDS(on)
1msec
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3007PbF
80
3.0
LIMITED BY PACKAGE
I D = 80A
2.5
40
20
0
25
50
75
100
125
TC , Case Temperature
150
175
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID , Drain Current (A)
60
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
( °C)
-20
0
20
40
60
80
100 120 140 160 180
( °C)
TJ, Junction Temperature
Fig 10. Normalized On-Resistance
Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
1
(Z thJC)
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
0.02
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
0.01
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
t1/ t 2
J = P DM x Z thJC
+T C
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3007PbF
600
ID
15V
TOP
20A
34A
48A
500
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
BOTTOM
DRIVER
L
VDS
400
300
200
100
0
25
50
75
100
125
I AS
150
175
( °C)
Starting T , JJunction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
-VGS(th) Gate threshold Voltage (V)
10 V
ID = 250µA
3.0
2.0
1.0
-75
VGS
-50
-25
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF3007PbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
100
0.01
0.05
10
0.10
1
0.1
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
300
T OP
Single Pulse
BOTT OM 50% Duty Cycle
ID = 48A
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of T jmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav ) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF3007PbF
D.U.T
Driver Gate Drive
+
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
VDD
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V DS
VGS
RG
RD
D.U.T.
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on)
tr
t d(off)
tf
Fig 18b. Switching Time Waveforms
8
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IRF3007PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- SOURCE
3- EMITTER
4 - DRAIN
HEXFET
1.40 (.055)
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
LOT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
TO-220AB package is not recommended for Surface Mount Application
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/04
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9
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/