IRF640 IRF640FP N - CHANNEL 200V - 0.150Ω - 18A TO-220/TO-220FP MESH OVERLAY MOSFET TYPE IRF640 IRF640FP ■ ■ ■ ■ V DSS R DS(on) ID 200 V 200 V < 0.18 Ω < 0.18 Ω 18 A 18 A TYPICAL RDS(on) = 0.150 Ω EXTREMELY HIGH dV/dt CAPABILITY VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED DESCRIPTION This power MOSFET is designed using he company’s consolidated strip layout-based MESH OVERLAY process. This technology matches and improves the performances compared with standard parts from various sources. APPLICATIONS ■ HIGH CURRENT SWITCHING ■ UNINTERRUPTIBLE POWER SUPPLY (UPS) ■ DC/DC COVERTERS FOR TELECOM, INDUSTRIAL, AND LIGHTING EQUIPMENT. 3 1 3 2 1 TO-220 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value IRF640 V DS V DGR V GS Un it IRF 640F P Drain-source Voltage (V GS = 0) 200 V Drain- gate Voltage (R GS = 20 kΩ) 200 V ± 20 G ate-source Voltage V ID Drain Current (continuous) at Tc = 25 o C 18 18(**) A ID Drain Current (continuous) at Tc = 100 oC 11 11(**) A I DM (•) P tot dv/dt( 1 ) V ISO Ts tg Tj Drain Current (pulsed) 72 72 A T otal Dissipation at T c = 25 oC 125 40 W Derating Factor 1.0 0.32 W/ C V/ns Peak Diode Recovery voltage slope 5 5 Insulation Withstand Voltage (DC) 2000 Storage Temperature Max. Operating Junction Temperature o V -65 to 150 o C 150 o C (•) Pulse width limited by safe operating area ( 1) ISD ≤ 18A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX First Digit of the Datecode Being Z or K Identifies Silicon Characterized in this Datasheet (**) Limited only by Maximum Temperature Allowed October 1999 1/9 IRF640/FP THERMAL DATA R thj -case Thermal Resistance Junction-case R thj -amb R thc-sink Tl Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose TO-220 TO-220FP 1.0 3.12 Max 62.5 0.5 300 o C/W o C/W C/W o C o AVALANCHE CHARACTERISTICS Symbo l Max Valu e Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Parameter 18 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 50 V) 280 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA T yp. Max. 200 V GS = 0 V DS = Max Rating Zero G ate Voltage Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (VDS = 0) Min. Unit V o T c = 125 C V GS = ± 20 V 1 10 µA µA ± 100 nA ON (∗) Symbo l Parameter Test Con ditions ID = 250 µA V GS(th) Gate Threshold Voltage R DS(on) Static Drain-source O n V GS = 10V Resistance I D(o n) V DS = V GS Min. T yp. Max. Unit 2 3 4 V 0.15 0.18 Ω ID = 9 A On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V 18 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/9 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse T ransfer Capacitance V DS = 25 V f = 1 MHz ID = 9 A V GS = 0 Min. T yp. 7 11 1200 200 60 Max. Unit S 1560 260 80 pF pF pF IRF640/FP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l T yp. Max. Unit t d(on) tr Turn-on Time Rise Time Parameter V DD = 100 V ID = 9 A VGS = 10 V R G = 4.7 Ω (see test circuit, figure 3) Test Con ditions 13 27 17 35 ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 160 V 55 10 21 72 nC nC nC T yp. Max. Unit 21 25 50 27 32 65 ns ns ns T yp. Max. Unit 18 72 A A I D = 18 A Min. V GS = 10V SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Con ditions Min. V DD = 160 V ID = 18 A R G = 4.7 Ω V GS = 10 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symbo l ISD I SDM (•) V SD (∗) t rr Q rr I RRM Parameter Test Con ditions Min. Source-drain Current Source-drain Current (pulsed) Forward On Voltage I SD = 18 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 18 A di/dt = 100 A/µs T j = 150 o C V DD = 50 V (see test circuit, figure 5) V GS = 0 1.5 V 240 ns 1.8 µC 15 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 IRF640/FP Thermal Impedance for TO-220 Thermal Impedance for TO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 IRF640/FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 IRF640/FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 IRF640/FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 IRF640/FP TO-220FP MECHANICAL DATA mm DIM. MIN. A 4.4 inch TYP. MAX. MIN. TYP. MAX. 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 0.630 28.6 30.6 1.126 1.204 L4 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 Ø 3 3.2 0.118 0.126 B D A E L3 L3 L6 F F1 L7 F2 H G G1 ¯ 1 2 3 L2 8/9 L4 IRF640/FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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