PHILIPS IRLZ34

Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope using ’trench’
technology. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection up to 2kV. It is intended for
use in switched mode power supplies
and general purpose switching
applications.
PINNING - TO220AB
PIN
IRLZ34N
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
PIN CONFIGURATION
MAX.
UNIT
55
30
68
175
35
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
tab
1
gate
2
drain
3
source
tab
g
drain
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDSS
VDGR
VGS
ID
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Continuous drain current
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 kΩ
IDM
PD
Tj, Tstg
Pulsed drain current
Total power dissipation
Operating junction and
storage temperature
- 55
55
55
± 13
30
21
110
68
175
V
V
V
A
A
A
W
˚C
TYP.
MAX.
UNIT
-
2.2
K/W
60
-
K/W
MIN.
MAX.
UNIT
-
2
kV
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
Rth j-a
CONDITIONS
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
ESD LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
VC
Human body model (100 pF, 1.5 kΩ)
Electrostatic discharge
capacitor voltage, all pins
February 1999
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
V(BR)DSS
V(BR)GSS
VGS(TO)
Drain-source breakdown
voltage
Gate-source breakdown
voltage
Gate threshold voltage
CONDITIONS
MIN.
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
IG = ±1 mA;
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
VGS = 5 V; ID = 17 A
VGS = 10 V; ID = 17 A
TYP. MAX. UNIT
55
50
10
-
-
V
V
V
1.0
0.5
12
-
1.5
28
26
40
0.02
0.05
-
2.0
2.3
46
35
74
1
20
10
500
V
V
V
mΩ
mΩ
mΩ
S
µA
µA
µA
µA
RDS(ON)
Drain-source on-state
resistance
gfs
IGSS
Forward transconductance
VDS = 25 V; ID = 15 A
Gate source leakage current VGS = ±5 V; VDS = 0 V
IDSS
Zero gate voltage drain
current
VDS = 55 V; VGS = 0 V;
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 30 A; VDD = 44 V; VGS = 5 V
-
22.5
6
11
-
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 25 A;
VGS = 5 V; RG = 10 Ω
Resistive load
-
14
77
55
48
21
110
80
65
ns
ns
ns
ns
Ld
Ld
Internal drain inductance
Internal drain inductance
-
3.5
4.5
-
nH
nH
Ls
Internal source inductance
Measured from tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
-
7.5
-
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
1050
205
113
1400
245
150
pF
pF
pF
Tj = 175˚C
Tj = 175˚C
Tj = 175˚C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
IS
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
trr
Qrr
Reverse recovery time
Reverse recovery charge
ISM
February 1999
CONDITIONS
MIN.
TYP. MAX. UNIT
-
-
30
A
-
-
110
A
IF = 25 A; VGS = 0 V
IF = 34 A; VGS = 0 V
-
0.95
1.0
1.2
-
V
V
IF = 34 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
40
0.16
-
ns
µC
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
-
45
mJ
Drain-source non-repetitive ID = 20 A; VDD ≤ 25 V; VGS = 5 V;
unclamped inductive turn-off RGS = 50 Ω; Tmb = 25 ˚C
energy
WDSS
120
Normalised Power Derating
PD%
1000
110
ID/A
100
90
tp =
RDS(ON) = VDS/ID
100
80
1 us
70
10us
60
50
40
100 us
DC
10
30
1 ms
20
10ms
100ms
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
10
100
VDS/V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
1
10
ZTH/ (K/W)
110
100
90
80
1 0.5
70
60
0.2
50
0.1
40
0.05
0.1
30
PD
tp
D=
t
T
0.02
tp
T
20
10
0
0
0
20
40
60
80 100
Tmb / C
120
140
160
0.01
180
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
February 1999
1.0E-06
0.0001
0.01
t/s
1
100
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
Drain current, ID (A)
100
10
7
80
25
5.0
4.6
60
20
4.0
40
Transconductance, gfs (S)
30
VGS = 6.0 V
5.6
15
3.6
20
0
10
3.0
0
2
4
6
8
Drain-source voltage, VDS (V)
5
10
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
45
0
20
30
40
50
Drain current, ID (A)
60
70
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON)/mOhm
2.5
VGS/V =
10
BUK959-60
a
Rds(on) normlised to 25degC
4
4.2
40
2
4.4
4.6
35
1.5
4.8
5
1
30
25
0
10
20
30 ID/A
40
50
0.5
-100
60
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
-50
0
50
Tmb / degC
100
150
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 17 A; VGS = 5 V
70
2.5
ID/A
60
BUK959-60
VGS(TO) / V
max.
2
50
typ.
1.5
40
min.
30
1
20
0.5
10
Tj/C =
0
0
1
175
25
2
3
VGS/V
4
5
6
0
-100
7
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
February 1999
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
100
Sub-Threshold Conduction
1E-01
IF/A
80
1E-02
2%
1E-03
typ
60
98%
Tj/C =
25
40
1E-04
20
1E-05
1E-05
175
0
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
0
0.5
1
VSDS/V
1.5
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
2.5
120
WDSS%
110
100
2.0
Thousands pF
90
80
1.5
70
60
50
Ciss
1.0
40
30
20
0.5
10
0
0.01
Coss
Crss
0.1
1
VDS/V
10
0
20
40
100
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 20 A
6
VGS/V
VDD
+
5
L
VDS = 14V
4
VDS
VDS = 44V
-
VGS
3
-ID/100
0
2
RGS
1
0
T.U.T.
0
5
10
QG/nC
15
20
25
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 30 A; parameter VDS
February 1999
R 01
shunt
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
MECHANICAL DATA
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
E
SOT78
A
A1
P
q
D1
D
L1
L2(1)
Q
b1
L
1
2
e
e
3
c
b
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
UNIT
A
A1
b
b1
c
D
D1
E
mm
4.5
4.1
1.39
1.27
0.9
0.7
1.3
1.0
0.7
0.4
15.8
15.2
6.4
5.9
10.3
9.7
e
L
L1
2.54
15.0
13.5
3.30
2.79
L2
max.
P
q
Q
3.0
3.8
3.6
3.0
2.7
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT78
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
97-06-11
TO-220
Fig.17. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to mounting instructions for SOT78 (TO220AB) package.
3. Epoxy meets UL94 V0 at 1/8".
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
Logic level TrenchMOSTM transistor
IRLZ34N
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999
7
Rev 1.000