Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope available in TO220AB and SOT404 . Using ’trench’ technology which features very low on-state resistance. It is intended for use in automotive and general purpose switching applications. QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot Tj RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance VGS = 5 V VGS = 10 V MAX. UNIT 100 75 230 175 V A W ˚C 15 14.4 mΩ mΩ PINNING TO220AB & SOT404 PIN PIN CONFIGURATION DESCRIPTION 1 gate 2 drain 3 source SYMBOL d tab mb g 2 1 tab/mb drain 3 1 2 3 TO220AB SOT404 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage RGS = 20 kΩ tp≤50µS - 100 100 10 15 V V V V ID ID IDM Ptot Tstg, Tj Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 75 53 313 230 175 A A A W ˚C TYP. MAX. UNIT - 0.65 K/W in free air 60 - K/W Minimum footprint, FR4 board 50 - K/W THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient(TO220AB) Thermal resistance junction to ambient(SOT404) - Rth j-a Rth j-a November 1999 1 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A STATIC CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage VGS = 0 V; ID = 0.25 mA; VGS(TO) MIN. TYP. MAX. UNIT VGS = 10 V; ID = 25 A VGS = 4.5 V; ID = 25 A 100 89 1 0.5 - 1.5 0.05 2 12 11.5 - 2.0 2.3 10 500 100 15 40.5 14.4 16 V V V V V µA µA nA mΩ mΩ mΩ mΩ MIN. TYP. MAX. UNIT - 6500 8600 pF - 550 325 660 400 pF pF Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C IDSS Zero gate voltage drain current VDS = 100 V; VGS = 0 V; IGSS RDS(ON) Gate source leakage current Drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 5 V; ID = 25 A Tj = 175˚C Tj = 175˚C DYNAMIC CHARACTERISTICS Tmb = 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz Coss Crss Output capacitance Feedback capacitance td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; Rload =1.2Ω; VGS = 5 V; RG = 10 Ω - 45 130 400 130 65 195 560 190 ns ns ns ns Ld Internal drain inductance - 4.5 - nH Ld Internal drain inductance - 3.5 - nH Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from contact screw on tab to centre of die(TO220AB) Measured from upper edge of drain tab to centre of die(SOT404) Measured from source lead to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT - - 75 A IF = 25 A; VGS = 0 V IF = 75 A; VGS = 0 V - 0.85 1.1 313 1.2 - A V V IF = 75 A; -dIF/dt = 100 A/µs; VGS = -10 V; VR = 30 V - 60 0.24 - ns µC REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IDR IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage trr Qrr Reverse recovery time Reverse recovery charge November 1999 CONDITIONS 2 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 35 A; VDD ≤ 25 V; VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C 120 Normalised Power Derating PD% MIN. TYP. MAX. UNIT - - 120 mJ 1000 110 ID/A 100 tp = 90 1uS RDS(ON) = VDS/ID 100 80 100uS 70 60 1mS 50 40 DC 10 10mS 30 100mS 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 1 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 10 100 VDS/V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 1 Zth / (K/W) 1 D= 110 0.5 100 90 0.2 80 0.1 70 0.1 60 0.05 50 0.02 40 PD tp D= 0.01 30 20 T 0 10 tp T t 0 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V November 1999 0.00001 0.001 t/S 0.1 10 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 3 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET 250 10.0 BUK9515-100A BUK9615-100A 100 5.0 4.0 VGS/V = ID/A ID/A 3.8 80 200 3.6 3.4 60 150 3.2 3.0 100 Tj/C = 40 25 175 2.8 50 20 2.6 2.4 0 0 2 4 6 VDS/V 8 0 10 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 20 0 0.5 1 1.5 VGS/V 2 2.5 3 3.5 Fig.8. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj RDS(ON)/mOhm 150 gfs/S 19 18 100 17 VGS/V = 16 15 3.0 3.2 3.4 3.6 4.0 5.0 14 13 12 11 0 50 20 40 ID/A 60 80 0 100 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 15 0 20 40 ID/A 60 80 100 Fig.9. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V RDS(ON)/mOhm 3 Rds(on) normalised to 25degC a 14.5 2.5 14 13.5 2 13 12.5 1.5 12 11.5 1 11 10.5 0.5 3 4 5 6 VGS/V 7 8 9 10 Fig.7. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(VGS); conditions: ID = 25 A; November 1999 -100 -50 0 50 100 Tmb / degC 150 200 Fig.10. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V 4 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A VGS(TO) / V 2.5 6 VGS/V max. 5 typ. 4 2 VDS = 1.5 14V 80V 3 min. 1 2 0.5 1 0 -100 -50 0 50 Tj / C 100 150 0 200 Fig.11. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS 10 20 30 40 50 60 70 QG/nC 80 90 100 110 Fig.14. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 25 A; parameter VDS 100 Sub-Threshold Conduction 1E-01 0 ID/A 80 1E-02 2% 1E-03 typ 60 98% Tj/C = 175 0.5 0.6 0.7 VSDS/V 25 40 1E-04 20 1E-05 0 1E-05 0 0.5 1 1.5 2 2.5 0 0.1 0.2 0.3 0.4 3 Fig.12. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 0.8 0.9 1 1.1 Fig.15. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj 20 120 WDSS% 110 100 15 90 Thousands 80 70 60 10 50 40 Ciss 30 5 20 10 0 0.01 0.1 1 VDS/V 10 100 0 Coss Crss 20 Fig.13. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz November 1999 40 60 80 100 120 Tmb / C 140 160 180 Fig.16. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 75 A 5 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A + VDD + VDD RD L VDS VDS - VGS - VGS -ID/100 T.U.T. 0 0 RG T.U.T. R 01 shunt RGS Fig.17. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.19. Switching test circuit. 100 25ºC IAV 10 Tj prior to avanche 150ºC 1 0.001 0.01 0.1 1 10 Avalanche Time, tAV (ms) Fig.18. Maximum permissible repetitive avalanche current(IAV) versus avalanche time(tAV) for unclamped inductive loads. November 1999 6 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.20. SOT78 (TO220AB); pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT78 (TO220) envelopes. 3. Epoxy meets UL94 V0 at 1/8". November 1999 7 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404 A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 OUTLINE VERSION D max. D1 E 11 1.60 1.20 10.30 9.70 e Lp HD Q 2.54 2.90 2.10 15.40 14.80 2.60 2.20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 SOT404 Fig.21. SOT404 surface mounting package. Centre pin connected to mounting base. Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". November 1999 8 Rev 1.000 Philips Semiconductors Product specification TrenchMOS transistor Logic level FET BUK9515-100A BUK9615-100A MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.22. SOT404 : soldering pattern for surface mounting. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 1999 9 Rev 1.000