INTERSIL ISL6754

ISL6754
¬
Data Sheet
September 29, 2008
ZVS Full-Bridge PWM Controller with
Adjustable Synchronous Rectifier Control
The ISL6754 is a high-performance extension of the Intersil
family of zero-voltage switching (ZVS) full-bridge PWM
controllers. Like the ISL6752, it achieves ZVS operation by
driving the upper bridge FETs at a fixed 50% duty cycle while
the lower bridge FETs are trailing-edge modulated with
adjustable resonant switching delays.
Adding to the ISL6752’s feature set are average current
monitoring and soft-start. The average current signal may be
used for average current limiting, current sharing circuits and
average current mode control. Additionally, the ISL6754
supports both voltage- and current-mode control.
FN6754.1
Features
• Adjustable Resonant Delay for ZVS Operation
• Synchronous Rectifier Control Outputs with Adjustable
Delay/Advance
• Voltage- or Current-Mode Control
• 3% Current Limit Threshold
• Adjustable Average Current Limit
• Adjustable Deadtime Control
• 175µA Start-up Current
• Supply UVLO
• Adjustable Oscillator Frequency Up to 2MHz
The ISL6754 features complemented PWM outputs for
synchronous rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision deadtime
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, Multi-Pulse
Suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL6754AAZA* 6754 AAZ
TEMP.
RANGE
(°C)
• Internal Over-Temperature Protection
• Buffered Oscillator Sawtooth Output
• Fast Current Sense to Output Delay
• Adjustable Cycle-by-Cycle Peak Current Limit
• 70ns Leading Edge Blanking
• Multi-Pulse Suppression
• Pb-Free (RoHS Compliant)
Applications
PACKAGE
(Pb-free)
PKG.
DWG. #
-40 to +105 20 Ld QSOP M20.15
• ZVS Full-Bridge Converters
• Telecom and Datacom Power
*Add -T suffix to part number for tape and reel packaging.
• Wireless Base Station Power
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
• File Server Power
• Industrial Power Systems
Pinout
ISL6754
(20 LD QSOP)
TOP VIEW
VREF 1
20 SS
VERR 2
19 VADJ
CTBUF 3
18 VDD
RTD 4
17 OUTLL
RESDEL 5
16 OUTLR
CT 6
15 OUTUL
FB 7
14 OUTUR
RAMP 8
13 OUTLLN
CS 9
12 OUTLRN
IOUT 10
1
11 GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
VDD
OUTUL
50%
VDD
VREF
OUTUR
DELAY/
ADVANCE
TIMING
CONTROL
PWM
STEERING
LOGIC
UVLO
OUTLL
2
OVERTEMPERATURE
PROTECTION
OUTLR
PWM
OUTLLN
OUTLRN
GND
SAMPLE
AND
HOLD
VREF
VADJ
RESDEL
-
4X
+70 nS
LEADING
EDGE
BLANKING
1.00V
OVER CURRENT
COMPARATOR
CT
ISL6754
IOUT
CS
+
OSCILLATOR
VREF
RAMP
RTD
VREF
PWM
COMPARATOR
CTBUF
80mV
1 mA
+
-
SS
VERR
0.33
SOFTSTART
CONTROL
+
FN6754.1
September 29, 2008
-
0.6V
FB
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
VIN+
CR2
CR3
T3
Q2
Q8A
R15
R16
Q8B
Q5A
Q5B
Q1
C3
C2
+
T1
C1
3
R18
400 VDC
+ Vout
L1
Q12
Q10A
C4
Q9A
C16
C15
Q9B
Q10B
+
C14
Q13
R17
RETURN
Q4
Q6A
Q7A
Q6B
Q7B
C13
Q3
ISL6754
VIN-
R20
R19
R13
R7
T2
R6
CR1
SS 20
2 VERR
VADJ 19
3 CTBUF
R8
4 RTD
R1
R4
VDD 18
C17
EL7212
C12
T4
EL7212
OUTLR 16
6 CT
OUTUL 15
CR4
R21
U4
OUTUR 14
8 RAMP
OUTLLN 13
9 CS
U1
10 IOUT
OUTLRN 12
R11
R23
OUTLL 17
5 RESDEL
7 FB
R5
ISL6754
1 VREF
U5
R22
C18
R24
GND 11
U1
R12
BIAS
C9
VDD
C5
C6
C7
U3
TL431
C10
C8
R14
R2
R3
R9
R10
C11
U2
R25
FN6754.1
September 29, 2008
Typical Application - High Voltage Input Secondary Side Control ZVS Full-Bridge Converter
VIN+
T3
1:1:1
Q1
Q2
Q6
Q5
CR2
R17
CR3
T1
Np:Ns:Ns=9:2:2
R18
Ns
R20
+ Vout
4
Np
L1
C12
Q16
Ns
Q10A
Q9A
C15
C14
Q9B
Q10B
+
+
400 VDC
C1
R19
Q15
T4
1:1:1
Q4
Q3
CR5
CR4
Q7A
C13
Q8A
R15
Q7B
R16
C10
Q8B
RETURN
C11
ISL6754
C9
Q11A
Q12A
Q12B
Q11B
Q13A
VIN-
Q13B
VREF
U1
R11
T2
CR1
1 VREF
SS 20
2 VERR
VADJ 19
3 CTBUF
R10
4 RTD
ISL6754
R12
5 RESDEL
R4
OUTUL 15
7 FB
OUTUR 14
9 CS
R5
10 IOUT
R9
OUTLL 17
OUTLR 16
6 CT
8 RAMP
R1
R23
VDD 18
C16
OUTLLN 13
Q14A
VREF
OUTLRN 12
Q14B
GND 11
C17
R24
C6
R14
R8
CR6
SECONDARY
BIAS SUPPLY
R22
U3
+
FN6754.1
September 29, 2008
C2
R21
R2
C3
C4
C5
R6
R7
R13
C7
R25
C8
R3
C18
ISL6754
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22.0V
OUTxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VREF + 0.3V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 6.0V
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1A
Latchup (Note 3) . . . . . . . . . . . . . . . . . . . Class II, Level B @ +85°C
Thermal Resistance Junction to Ambient (Typical)
θJA (°C/W)
20 Lead QSOP (Note 1). . . . . . . . . . . . . . . . . . . . . .
88
Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL6754AAxx . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . 9VDC to 16VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. All voltages are with respect to GND.
3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are using a pulse limited to 50mA.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application schematics” beginning on page 3. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF,
TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY VOLTAGE
Supply Voltage
-
-
20
V
Start-Up Current, IDD
VDD = 5.0V
-
175
400
µA
Operating Current, IDD
RLOAD, COUT = 0
-
11.0
15.5
mA
UVLO START Threshold
8.00
8.75
9.00
V
UVLO STOP Threshold
6.50
7.00
7.50
V
-
1.75
-
V
4.850
5.000
5.150
V
Hysteresis
REFERENCE VOLTAGE
Overall Accuracy
IVREF = 0mA to 10mA
Long Term Stability
TA = +125°C, 1000 hours (Note 4)
-
3
-
mV
-10
-
-
mA
5
-
-
mA
VREF = 4.85V
-15
-
-100
mA
Current Limit Threshold
VERR = VREF
0.97
1.00
1.03
V
CS to OUT Delay
Excl. LEB
-
35
-
ns
-
70
-
ns
Operational Current (source)
Operational Current (sink)
Current Limit
CURRENT SENSE
Leading Edge Blanking (LEB) Duration
CS to OUT Delay + LEB
TA = +25°C
-
-
150
ns
CS Sink Current Device Impedance
VCS = 1.1V
-
-
20
Ω
Input Bias Current
VCS = 0.3V
-1.0
-
1.0
µA
IOUT Sample and Hold Buffer Amplifier Gain
TA = +25°C
3.85
4.00
4.15
V/V
IOUT Sample and Hold VOH
VCS = max, ILOAD = -300μA
3.9
-
-
V
IOUT Sample and Hold VOL
VCS = 0.00V, ILOAD = 10μA
-
-
0.3
V
5
FN6754.1
September 29, 2008
ISL6754
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application schematics” beginning on page 3. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF,
TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
RAMP
-
-
20
Ω
65
80
95
mV
VRAMP = 0.3V
-5.0
-
-2.0
μA
Minimum Duty Cycle
VERR < 0.6V
-
-
0
%
Maximum Duty Cycle (per half-cycle)
VERR = 4.20V, VCS = 0V (Note 5)
-
94
-
%
RTD = 2.00kΩ, CT = 220pF
-
97
-
%
RTD = 2.00kΩ, CT = 470pF
-
99
-
%
0.85
-
1.20
V
0.7
0.8
0.9
V
0.31
0.33
0.35
V/V
(Note 4)
0
-
4.45
V
Input Common Mode (CM) Range
(Note 4)
0
-
VREF
V
GBWP
(Note 4)
5
-
-
MHz
VERR VOL
ILOAD = 2mA
-
-
0.4
V
VERR VOH
ILOAD = 0mA
4.20
-
-
V
VERR Pull-Up Current Source
VERR = 2.5V
0.8
1.0
1.3
mA
EA Reference
TA = +25°C
0.594
0.600
0.606
V
0.590
0.600
0.612
V
165
183
201
kHz
-10
-
10
%
RAMP Sink Current Device Impedance
VRAMP = 1.1V
RAMP to PWM Comparator Offset
TA = +25°C
Bias Current
PULSE WIDTH MODULATOR
Zero Duty Cycle VERR Voltage
VERR to PWM Comparator Input Offset
TA = +25°C
VERR to PWM Comparator Input Gain
Common Mode (CM) Input Range
ERROR AMPLIFIER
EA Reference + EA Input Offset Voltage
OSCILLATOR
Frequency Accuracy, Overall
(Note 4)
Frequency Variation with VDD
TA = +25°C, (F20V- - F10V)/F10V
-
0.3
1.7
%
Temperature Stability
VDD = 10V, |F-40°C - F0°C|/F0°C
-
4.5
-
%
|F0°C - F105°C|/F25°C (Note 4)
-
1.5
-
%
-193
-200
-207
µA
19
20
23
µA/µA
TA = +25°C
Charge Current
Discharge Current Gain
CT Valley Voltage
Static Threshold
0.75
0.80
0.88
V
CT Peak Voltage
Static Threshold
2.75
2.80
2.88
V
CT Pk-Pk Voltage
Static Value
1.92
2.00
2.05
V
1.97
2.00
2.03
V
RTD Voltage
RESDEL Voltage Range
0
-
2.00
V
CTBUF Gain (VCTBUFP-P/VCTP-P)
VCT = 0.8V, 2.6V
1.95
2.0
2.05
V/V
CTBUF Offset from GND
VCT = 0.8V
0.34
0.40
0.44
V
CTBUF VOH
ΔV(ILOAD = 0mA, ILOAD = -2mA), VCT = 2.6V
-
-
0.10
V
CTBUF VOL
ΔV(ILOAD = 2mA, ILOAD = 0mA), VCT = 0.8V
-
-
0.10
V
6
FN6754.1
September 29, 2008
ISL6754
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application schematics” beginning on page 3. 9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF,
TA = -40°C to +105°C, Typical values are at TA = +25°C; Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Charging Current
SS = 3V
SS Clamp Voltage
SS Discharge Current
SS = 2V
Reset Threshold Voltage
TA = +25°C
-60
-70
-80
μA
4.410
4.500
4.590
V
10
-
-
mA
0.23
0.27
0.33
V
OUTPUT
High Level Output Voltage (VOH)
IOUT = -10mA, VDD - VOH
-
0.5
1.0
V
Low Level Output Voltage (VOL)
IOUT = 10mA, VOL - GND
-
0.5
1.0
V
Rise Time
COUT = 220pF, VDD = 15V (Note 4)
-
110
200
ns
Fall Time
COUT = 220pF, VDD = 15V (Note 4)
-
90
150
ns
UVLO Output Voltage Clamp
VDD = 7V, ILOAD = 1mA (Note 6)
-
-
1.25
V
Output Delay/Advance Range
VADJ = 2.50V
OUTLLN/OUTLRN relative to OUTLL/OUTLR
VADJ < 2.425V
-
2
-
ns
-40
-
-300
ns
VADJ > 2.575V
40
-
300
ns
2.575
-
5.000
V
0
-
2.425
V
Delay/Advance Control Voltage Range
OUTLxN Delayed
OUTLLN/OUTLRN relative to OUTLL/OUTLR
OUTLxN Advanced
VADJ Delay Time
TA = +25°C (OUTLx Delayed) (Note 7)
VADJ = 0
-
300
-
ns
VADJ = 0.5V
-
105
-
ns
VADJ = 1.0V
-
70
-
ns
VADJ = 1.5V
-
55
-
ns
VADJ = 2.0V
-
50
-
ns
VADJ = VREF
-
300
-
ns
VADJ = VREF - 0.5V
-
100
-
ns
VADJ = VREF - 1.0V
-
68
-
ns
VADJ = VREF - 1.5V
-
55
-
ns
VADJ = VREF - 2.0V
-
48
-
ns
TA = +25°C (OUTLxN Delayed)
THERMAL PROTECTION
Thermal Shutdown
(Note 4)
-
140
-
°C
Thermal Shutdown Clear
(Note 4)
-
125
-
°C
Hysteresis, Internal Protection
(Note 4)
-
15
-
°C
NOTES:
4. Limits established by characterization and are not production tested.
5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 through 3.
6. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
7. When OUTLx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge
time (deadtime) as determined by CT and RTD.
7
FN6754.1
September 29, 2008
ISL6754
Typical Performance Curves
1.01
1
0.99
0.98
-40
25
CT DISCHARGE CURRENT GAIN
NORMALIZED VREF
1.02
-25
-10
5
20
35
50
65
80
95
24
23
22
21
20
19
18
110
0
200
400
600
800
1000
RTD CURRENT (¬¨¬
TEMPERATURE (¬¨Ð
FIGURE 1. REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 2. CT DISCHARGE CURRENT GAIN vs RTD CURRENT
1-103
1-104
CT = 1000pF
FREQUENCY (kHz)
DEADTIME TD (ns)
CT = 680pF
CT = 470pF
1-103
CT = 100pF
CT = 220pF
CT = 330pF
100
RTD = 10kΩ
100
RTD = 50kΩ
RTD = 100kΩ
10
0
10
20
30
40 50 60
RTD (kΩ)
70
80
90
100
FIGURE 3. DEADTIME (DT) vs CAPACITANCE
Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize
noise immunity, bypass VDD to GND with a ceramic
capacitor as close to the VDD and GND pins as possible.
VDD is monitored for supply voltage undervoltage lock-out
(UVLO). The start and stop thresholds track each other
resulting in relatively constant hysteresis.
GND - Signal and power ground connections for this device.
Due to high peak currents and high frequency operation, a
low impedance layout is necessary. Ground planes and
short traces are highly recommended.
VREF - The 5.00V reference voltage output having 3%
tolerance over line, load and operating temperature. Bypass
to GND with a 0.1μF to 2.2μF low ESR capacitor.
CT - The oscillator timing capacitor is connected between
this pin and GND. It is charged through an internal 200μA
current source and discharged with a user adjustable current
source controlled by RTD.
RTD - This is the oscillator timing capacitor discharge
current control pin. The current flowing in a resistor
connected between this pin and GND determines the
8
10
0.1
1
CT (nF)
10
FIGURE 4. CAPACITANCE vs FREQUENCY
magnitude of the current that discharges CT. The CT
discharge current is nominally 20x the resistor current. The
PWM deadtime is determined by the timing capacitor
discharge duration. The voltage at RTD is nominally 2.00V.
CS - This is the input to the overcurrent comparator. The
overcurrent comparator threshold is set at 1.00 V nominal.
The CS pin is shorted to GND at the termination of either
PWM output.
Depending on the current sensing source impedance, a
series input resistor may be required due to the delay
between the internal clock and the external power switch.
This delay may result in CS being discharged prior to the
power switching device being turned off.
RAMP - This is the input for the sawtooth waveform for the
PWM comparator. The RAMP pin is shorted to GND at the
termination of the PWM signal. A sawtooth voltage
waveform is required at this input. For current-mode control
this pin is connected to CS and the current loop feedback
signal is applied to both inputs. For voltage-mode control,
the oscillator sawtooth waveform may be buffered and used
to generate an appropriate signal, RAMP may be connected
to the input voltage through a RC network for voltage feed
forward control, or RAMP may be connected to VREF
FN6754.1
September 29, 2008
ISL6754
through a RC network to produce the desired sawtooth
waveform.
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
When the PWM outputs are delayed relative to the SR
outputs (VADJ < 2.425V), the delay time should not exceed
90% of the deadtime as determined by RTD and CT.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR - These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
OUTLLN and OUTLRN - These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
VADJ - A 0V to 5V control voltage applied to this input sets
the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above
2.575V result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero
phase difference. A weak internal 50% divider from VREF
results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40 to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(Δt/ΔV) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
9
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a
nominal 1mA pull-up current source.
When VERR is driven by an opto-coupler or other current
source device, a pull-up resistor from VREF is required to
linearize the gain. Generally, a pull-up resistor on the order
of 5kΩ is acceptable.
FB - FB is the inverting inputs to the error amplifier (EA). The
amplifier may be used as the error amplifier for voltage
feedback or used as the average current limit amplifier (IEA).
If the amplifier is not used, FB should be grounded.
IOUT - Output of the 4X buffer amplifier of the sample and
hold circuitry that captures and averages the CS signal.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of
the capacitor and the internal current source determine the
rate of increase of the duty cycle during start-up.
SS may also be used to inhibit the outputs by grounding
through a small transistor in an open collector/drain
configuration.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The ISL6754 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features,
a highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
If synchronous rectification is not required, please consider
the ISL6755 controller.
Oscillator
The ISL6754 has an oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor and capacitor.
FN6754.1
September 29, 2008
ISL6754
The switching period is the sum of the timing capacitor
charge and discharge durations. The charge duration is
determined by CT and a fixed 200µA internal current source.
The discharge duration is determined by RTD and CT.
3
T C ≈ 11.5 ⋅ 10 ⋅ CT
S
(EQ. 1)
T D ≈ ( 0.06 ⋅ RTD ⋅ CT ) + 50 ⋅ 10
1
T SW = T C + T D = -----------F SW
–9
S
S
(EQ. 2)
(EQ. 3)
where TC and TD are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, TSW is the
oscillator period, and FSW is the oscillator frequency. One
output switching cycle requires two oscillator cycles. The
actual times will be slightly longer than calculated due to
internal propagation delays of approximately 10ns/transition.
This delay adds directly to the switching duration, but also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very small
discharge currents are used, there will be increased error
due to the input impedance at the CT pin. The maximum
recommended current through RTD is 1mA, which produces
a CT discharge current of 20mA.
operation. The DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. Average current limit will prevent the
instability and allow continuous operation in current limit
provided the control loop is designed with adequate
bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased
by the leading edge blanking (LEB) interval. The effective
delay is the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to
the peak current comparator and a sample and hold
averaging circuit. After a 70ns leading edge blanking (LEB)
delay, the current sense signal is actively sampled during the
on time, the average current for the cycle is determined, and
the result is amplified by 4x and output on the IOUT pin. If an
RC filter is placed on the CS input, its time constant should
not exceed ~50ns or significant error may be introduced on
IOUT.
The maximum duty cycle, D, and percent deadtime, DT, can
be calculated from:
TC
D = -----------T SW
(EQ. 4)
DT = 1 – D
(EQ. 5)
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle
peak overcurrent protection which provides fast response.
The cycle-by-cycle peak current limit results in pulse-by-pulse
duty cycle reduction when the current feedback signal
exceeds 1.0V. When the peak current exceeds the threshold,
the active output pulse is immediately terminated. This results
in a decrease in output voltage as the load current increases
beyond the current limit threshold. The ISL6754 operates
continuously in an overcurrent condition without shutdown.
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 5. CS INPUT vs IOUT
Figure 5 shows the relationship between the CS signal and
IOUT under steady state conditions. IOUT is 4x the average
of CS. Figure 6 shows the dynamic behavior of the current
averaging circuitry when CS is modulated by an external
sine wave. Notice IOUT is updated by the sample and hold
circuitry at the termination of the active output pulse.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent
protection also maintains flux balance in the transformer by
maintaining duty cycle symmetry between half-cycles. If
voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
10
FN6754.1
September 29, 2008
ISL6754
The EA available on the ISL6754 may also be used as the
voltage EA for the voltage feedback control loop rather than
the current EA as described above. An external op-amp may
be used as either the current or voltage EA providing the
circuit is not allowed to source current into VERR. The
external EA must only sink current, which may be
accomplished by adding a diode in series with its output.
The 4x gain of the sample and hold buffer allows a range of
150 - 1000mV peak on the CS signal, depending on the
resistor divider placed on IOUT. The overall bandwidth of the
average current loop is determined by the integrating current
EA compensation and the divider on IOUT.
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
If average overcurrent limit is desired, IOUT may be used
with the error amplifier of the ISL6754. Typically IOUT is
divided down and filtered as required to achieve the desired
amplitude. The resulting signal is input to the current error
amplifier (IEA). The IEA is similar to the voltage EA found in
most PWM controllers, except it cannot source current.
Instead, VERR has a separate internal 1mA pull-up current
source.
Configure the IEA as an integrating (Type I) amplifier using
the internal 0.6V reference. The voltage applied at FB is
integrated against the 0.6V reference. The resulting signal,
VERR, is applied to the PWM comparator where it is
compared to the sawtooth voltage on RAMP. If FB is less
than 0.6V, the IEA will be open loop (can’t source current),
VERR will be at a level determined by the voltage loop, and
the duty cycle is unaffected. As the output load increases,
IOUT will increase, and the voltage applied to FB will
increase until it reaches 0.6V. At this point the IEA will
reduce VERR as required to maintain the output current at
the level that corresponds to the 0.6V reference. When the
output current again drops below the average current limit
threshold, the IEA returns to an open loop condition, and the
duty cycle is again controlled by the voltage loop.
The average current control loop behaves much the same
as the voltage control loop found in typical power supplies
except it regulates current rather than voltage.
11
20 VREF
2 VERR
19 SS
3
18 VDD
ISL6754
FIGURE 6. DYNAMIC BEHAVIOR OF CS vs IOUT
The average current signal on IOUT remains accurate
provided the output inductor current remains continuous
(CCM operation). Once the inductor current becomes
discontinuous (DCM operation), IOUT represents 1/2 the
peak inductor current rather than the average current. This
occurs because the sample and hold circuitry is active only
during the on time of the switching cycle. It is unable to
detect when the inductor current reaches zero during the off
time.
1
C10
150 - 1000 mV
4
17 OUTLL
5
16 OUTLR
6
15 OUTUL
7 FB
0.6V +
8
14 OUTUR
9 CS
10 IOUT
R6
S&H
4x
13 N/C
12 GND
11 GND
R5
R4
FIGURE 7. AVERAGE OVERCURRENT IMPLEMENTATION
The current EA cross-over frequency, assuming R6 >>
(R4||R5), is:
1
f CO = ----------------------------------2π ⋅ R6 ⋅ C10
Hz
(EQ. 6)
where fCO is the cross-over frequency. A capacitor in parallel
with R4 may be used to provide a double-pole roll-off.
The average current loop bandwidth is normally set to be
much less than the switching frequency, typically less than
5kHz and often as slow as a few hundred hertz or less. This
is especially useful if the application experiences large
surges. The average current loop can be set to the steady
state overcurrent threshold and have a time response that is
longer than the required transient. The peak current limit can
be set higher than the expected transient so that it does not
interfere with the transient, but still protects for short-term
larger faults. In essence a 2-stage overcurrent response is
possible.
The peak overcurrent behavior is similar to most other PWM
controllers. If the peak current exceeds 1.0V, the active
output pulse is terminated immediately.
FN6754.1
September 29, 2008
ISL6754
If voltage-mode control is used in a bridge topology, it should
be noted that peak current limit results in inherently unstable
operation. DC blocking capacitors used in voltage-mode
bridge topologies become unbalanced, as does the flux in
the transformer core. The average overcurrent circuitry
prevents this behavior by maintaining symmetric duty cycles
for each half-cycle. If the average current limit circuitry is not
used, a latching overcurrent shutdown method using
external components is recommended.
selected so that the ramp amplitude reaches 1.0V at
minimum input voltage within the duration of one half-cycle.
VIN
Voltage feed forward is a technique used to regulate the
output voltage for changes in input voltage without the
intervention of the control loop. Voltage feed forward is
implemented in voltage-mode control loops, but is redundant
and unnecessary in peak current-mode control loops.
Voltage feed forward operates by modulating the sawtooth
ramp in direct proportion to the input voltage. Figure 8
demonstrates the concept.
20
2
19
3
18
4
R3
The CS to output propagation delay is increased by the
leading edge blanking (LEB) interval. The effective delay is
the sum of the two delays and is 130ns maximum.
Voltage Feed Forward Operation
1
C7
17
ISL6754
5
16
6
15
7
14
8 RAMP
13
9
12
10
GND 11
FIGURE 9. VOLTAGE FEED FORWARD CONTROL
The charging time of the ramp capacitor is:
V RAMP ( PEAK )⎞
⎛
t = – R3 ⋅ C7 ⋅ ln ⎜ 1 – ----------------------------------------⎟
V IN ( MIN ) ⎠
⎝
S
(EQ. 7)
For optimum performance, the maximum value of the
capacitor should be limited to 10nF. The maximum DC
current through the resistor should be limited to 2mA
maximum. For example, if the oscillator frequency is
400kHz, the minimum input voltage is 300V, and a 4.7nF
ramp capacitor is selected, the value of the resistor can be
determined by rearranging Equation 7.
VIN
ERROR VOLTAGE
RAMP
CT
–6
– 2.5 ⋅ 10
–t
R3 = ------------------------------------------------------------------------- = -----------------------------------------------------------–9
1
V RAMP ( PEAK )⎞
⎛
4.7
10
⋅
⋅ ln ⎛ 1 – ----------⎞
C7 ⋅ ln ⎜ 1 – ----------------------------------------⎟
⎝
⎠
300
V IN ( MIN ) ) ⎠
⎝
OUTLL, LR
= 159
FIGURE 8. VOLTAGE FEED FORWARD BEHAVIOR
Input voltage feed forward may be implemented using the
RAMP input. An RC network connected between the input
voltage and ground, as shown in Figure 9, generates a
voltage ramp whose charging rate varies with the amplitude
of the source voltage. At the termination of the active output
pulse, RAMP is discharged to ground so that a repetitive
sawtooth waveform is created. The RAMP waveform is
compared to the VERR voltage to determine duty cycle. The
selection of the RC components depends upon the desired
input voltage operating range and the frequency of the
oscillator. In typical applications, the RC components are
12
kΩ
(EQ. 8)
where t is equal to the oscillator period minus the deadtime.
If the deadtime is short relative to the oscillator period, it can
be ignored for this calculation.
If feed forward operation is not desired, the RC network may
be connected to VREF rather than the input voltage.
Alternatively, a resistor divider from CTBUF may be used as
the sawtooth signal. Regardless, a sawtooth waveform must
be generated on RAMP as it is required for proper PWM
operation.
Gate Drive
The ISL6754 outputs are capable of sourcing and sinking
10mA (at rated VOH, VOL) and are intended to be used in
conjunction with integrated FET drivers or discrete bipolar
totem pole drivers. The typical on resistance of the outputs is
50Ω.
FN6754.1
September 29, 2008
ISL6754
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding:
T SW ⋅ V ⋅ R CS N
O
S 1
V e = ------------------------------------------ ⋅ -------- ⎛ --- + D – 0.5⎞
⎠
N CT ⋅ L O
NP ⎝ π
V
(EQ. 15)
where RCS is the current sense burden resistor, NCT is the
current transformer turns ratio, LO is the output inductance,
VO is the output voltage, and NS and NP are the secondary
and primary turns, respectively.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is:
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields:
1
Fm = -------------------SnTsw
N S ⋅ R CS ⎛
D ⋅ T SW ⎛
NS
⎞⎞
V CS = ------------------------ ⎜ I O + --------------------- ⎜ V IN ⋅ -------- – V O⎟ ⎟
N P ⋅ N CT ⎝
2L O ⎝
NP
⎠⎠
(EQ. 9)
V
(EQ. 16)
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes:
where VCS is the voltage across the current sense resistor
and IO is the output current at current limit.
1
1
Fm = --------------------------------------- = ---------------------------( Sn + Se )Tsw
m c SnTsw
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
(EQ. 10)
V e + V CS = 1
where Se is slope of the external ramp and
Se
m c = 1 + ------Sn
(EQ. 17)
(EQ. 11)
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
1
Q = ------------------------------------------------π ( m c ( 1 – D ) – 0.5 )
(EQ. 12)
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields:
1
1
S e = S n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
(EQ. 13)
Since Sn and Se are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by TON to obtain the voltage change that occurs during TON.
1
1
V e = V n ⎛ ⎛ --- + 0.5⎞ ------------- – 1⎞
⎠1 –D
⎝⎝π
⎠
(EQ. 14)
where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
13
Substituting Equations 15 and 16 into Equation 17 and
solving for RCS yields:
N P ⋅ N CT
1
R CS = ------------------------ ⋅ -----------------------------------------------------VO
NS
1 D
I O + -------- T SW ⎛ --- + ----⎞
⎝ π 2⎠
L
Ω
(EQ. 18)
O
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
V IN ⋅ DT SW
ΔI P = ------------------------------Lm
A
(EQ. 19)
where VIN is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
resistor, RCS, is:
ΔI P ⋅ R CS
ΔV CS = -------------------------N CT
V
(EQ. 20)
FN6754.1
September 29, 2008
ISL6754
If ΔVCS is greater than or equal to Ve, then no additional
slope compensation is needed and RCS becomes:
N CT
R CS = -------------------------------------------------------------------------------------------------------------------------------------NS ⎛
DT SW ⎛
NS
⎞ ⎞ V IN ⋅ DT SW
-------- ⋅ ⎜ I O + ---------------- ⋅ ⎜ V ⋅ ------- – V O⎟ ⎟ + ------------------------------Lm
NP ⎝
2L O ⎝ IN N P
⎠⎠
LO = 2.0µH
(EQ. 21)
Adding slope compensation may be accomplished in the
ISL6754 using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-topeak amplitude of CT (0.4V to 4.4V). A typical application
sums this signal with the current sense feedback and applies
the result to the CS pin as shown in Figure 10.
1
20
2
19
3 CTBUF
18
4
17
5
6
R6
RCS
16
ISL6754
15
7
14
8 RAMP
13
9 CS
12
10
VIN = 280V
VO = 12V
If ΔVCS is less than Ve, then Equation 16 is still valid for the
value of RCS, but the amount of slope compensation added
by the external ramp must be reduced by ΔVCS.
R9
Example:
GND 11
Np/Ns = 20
Lm = 2mH
IO = 55A
Oscillator Frequency, Fsw = 400kHz
Duty Cycle, D = 85.7%
NCT = 50
R6 = 499Ω
Solve for the current sense resistor, RCS, using Equation 18.
RCS = 15.1Ω.
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 15.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 20.
ΔVCS = 91mV
Using Equation 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1kΩ
Determine the new value of RCS, R’CS, using Equation 24.
C4
R’CS = 15.4Ω
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
FIGURE 10. ADDING SLOPE COMPENSATION
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
( D ( V CTBUF – 0.4 ) + 0.4 ) ⋅ R6
V e – ΔV CS = ------------------------------------------------------------------------------R6 + R9
(EQ. 22)
V
Rearranging to solve for R9 yields:
( D ( V CTBUF – 0.4 ) – V e + ΔV CS + 0.4 ) ⋅ R6
R9 = ------------------------------------------------------------------------------------------------------------------V e – ΔV CS
If the application requires deadtime less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300ns to 400ns. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown in Figure 11.
Ω
(EQ. 23)
The value of RCS determined in Equation 18 or 21 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 16. The divider created
by R6 and R9 makes this necessary.
R6 + R9
R′ CS = ---------------------- ⋅ R CS
R9
(EQ. 24)
14
FN6754.1
September 29, 2008
ISL6754
1 VREF
20
2
19
3
ISL6754
CT
18
DEADTIME
R9
4
17
5 CT
16
6
15
7
14
8 RAMP
13
9 CS
R6
PWM
PWM
OUTLR
PWM
12
OUTUR
10
RCS
PWM
OUTLL
OUTUL
CT
C4
RESONANT
DELAY
GND 11
RESDEL
WINDOW
FIGURE 12. BRIDGE DRIVE SIGNAL TIMING
FIGURE 11. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 22
and 23 require modification. Equation 22 becomes:
2D ⋅ R6
V e – ΔV CS = ---------------------R6 + R9
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
VIN+
UL
UR
D1
VOUT+
LL
V
(EQ. 25)
RTN
and Equation 23 becomes:
LL
LR
D2
( 2D – V e + ΔV CS ) ⋅ R6
R9 = ------------------------------------------------------------V e – ΔV CS
Ω
(EQ. 26)
VIN-
FIGURE 13. IDEALIZED FULL-BRIDGE
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
The ISL6754 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hardswitched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
In Figure 13, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 14, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by IP and IS, respectively.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
LR
D2
VIN-
FIGURE 14. UL - LR POWER TRANSFER CYCLE
15
FN6754.1
September 29, 2008
ISL6754
The UL - LR power transfer period terminates when switch
LR turns off as determined by the PWM. The current flowing
in the primary cannot be interrupted instantaneously, so it
must find an alternate path. The current flows into the
parasitic switch capacitance of LR and UR which charges
the node to VIN and then forward biases the body diode of
upper switch UR.
where τ is the resonant transition time, LL is the leakage
inductance, CP is the parasitic capacitance, and R is the
equivalent resistance in series with LL and CP.
The resonant delay is always less than or equal to the
deadtime and may be calculated using Equation 28.
V resdel
τ resdel = -------------------- ⋅ DT
2
S
(EQ. 28)
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
LR
D2
VIN-
FIGURE 15. UL - UR FREE-WHEELING PERIOD
The primary leakage inductance, LL, maintains the current
which now circulates around the path of switch UL, the
transformer primary, and switch UR. When switch LR opens,
the output inductor current free-wheels through both output
diodes, D1 and D2. During the switch transition, the output
inductor current assists the leakage inductance in charging
the upper and lower bridge FET capacitance.
The current flow from the previous power transfer cycle
tends to be maintained during the free-wheeling period
because the transformer primary winding is essentially
shorted. Diode D1 may conduct very little or none of the
free-wheeling current, depending on circuit parasitics. This
behavior is quite different than occurs in a conventional
hard-switched full-bridge topology where the free-wheeling
current splits nearly evenly between the output diodes, and
flows not at all in the primary.
This condition persists through the remainder of the halfcycle.
During the period when CT discharges, also referred to as
the deadtime, the upper switches toggle. Switch UL turns off
and switch UR turns on. The actual timing of the upper
switch toggle is dependent on RESDEL which sets the
resonant delay. The voltage applied to RESDEL determines
how far in advance the toggle occurs prior to a lower switch
turning on. The ZVS transition occurs after the upper
switches toggle and before the diagonal lower switch turns
on. The required resonant delay is 1/4 of the period of the LC
resonant frequency of the circuit formed by the leakage
inductance and the parasitic capacitance. The resonant
transition may be estimated from Equation 27.
1
π
τ = --- ----------------------------------2
2
R
1
--------------- – ---------2
LL CP
4L L
(EQ. 27)
16
where τresdel is the desired resonant delay, Vresdel is a
voltage between 0V and 2V applied to the RESDEL pin, and
DT is the deadtime (see Equations 1 through 5).
When the upper switches toggle, the primary current that
was flowing through UL must find an alternate path. It
charges/discharges the parasitic capacitance of switches UL
and LL until the body diode of LL is forward biased. If
RESDEL is set properly, switch LL will be turned on at this
time. The output inductor does not assist this transition. It is
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
LR
D2
VIN-
FIGURE 16. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
purely a resonant transition driven by the leakage
inductance.
The second power transfer period commences when switch
LL closes. With switches UR and LL on, the primary and
secondary currents flow as indicated in Figure 17.
VIN+
UL
UR
D1
VOUT+
LL
RTN
LL
LR
D2
VIN-
FIGURE 17. UR - LL POWER TRANSFER CYCLE
The UR - LL power transfer period terminates when switch
LL turns off as determined by the PWM. The current flowing
in the primary must find an alternate path. The current flows
into the parasitic switch capacitance which charges the node
to VIN and then forward biases the body diode of upper
switch UL. As before, the output inductor current assists in
this transition. The primary leakage inductance, LL,
FN6754.1
September 29, 2008
ISL6754
maintains the current, which now circulates around the path
of switch UR, the transformer primary, and switch UL. When
switch LL opens, the output inductor current free-wheels
predominantly through diode D1. Diode D2 may actually
conduct very little or none of the free-wheeling current,
depending on circuit parasitics. This condition persists
through the remainder of the half-cycle.
opposite PWM output, i.e. OUTLL and OUTLRN are paired
together and OUTLR and OUTLLN are paired together.
CT
OUTLL
VIN+
UL
UR
D1
IS
OUTLR
VOUT+
LL
IP
RTN
LL
OUTLLN
(SR1)
LR
OUTLRN
(SR2)
D2
VIN-
FIGURE 18. UR - UL FREE-WHEELING PERIOD
FIGURE 20. BASIC WAVEFORM TIMING
When the upper switches toggle, the primary current that
was flowing through UR must find an alternate path. It
charges/discharges the parasitic capacitance of switches UR
and LR until the body diode of LR is forward biased. If
RESDEL is set properly, switch LR will be turned on at this
time.
VIN+
UL
UR
D1
IS
VOUT+
LL
IP
RTN
LL
Referring to Figure 20, the SRs alternate between being both
on during the free-wheeling portion of the cycle (OUTLL/LR
off), and one or the other being off when OUTLL or OUTLR is
on. If OUTLL is on, its corresponding SR must also be on,
indicating that OUTLRN is the correct SR control signal.
Likewise, if OUTLR is on, its corresponding SR must also be
on, indicating that OUTLLN is the correct SR control signal.
LR
D2
VIN-
A useful feature of the ISL6754 is the ability to vary the
phase relationship between the PWM outputs (OUTLL, OUT
LR) and the their complements (OUTLLN, OUTLRN) by
±300ns. This feature allows the designer to compensate for
differences in the propagation times between the PWM FETs
and the SR FETs. A voltage applied to VADJ controls the
phase relationship.
FIGURE 19. UPPER SWITCH TOGGLE AND RESONANT
TRANSITION
CT
The first power transfer period commences when switch LR
closes and the cycle repeats. The ZVS transition requires
that the leakage inductance has sufficient energy stored to
fully charge the parasitic capacitances. Since the energy
stored is proportional to the square of the current (1/2 LLIP2),
the ZVS resonant transition is load dependent. If the leakage
inductance is not able to store sufficient energy for ZVS, a
discrete inductor may be added in series with the
transformer primary.
Synchronous Rectifier Outputs and Control
The ISL6754 provides double-ended PWM outputs, OUTLL
and OUTLR, and synchronous rectifier (SR) outputs,
OUTLLN and OUTLRN. The SR outputs are the
complements of the PWM outputs. It should be noted that
the complemented outputs are used in conjunction with the
17
OUTLL
OUTLR
OUTLLN
(SR1)
OUTLRN
(SR2)
FIGURE 21. WAVEFORM TIMING WITH PWM OUTPUTS
DELAYED, 0V < VADJ < 2.425V
FN6754.1
September 29, 2008
ISL6754
On/Off Control
The ISL6754 does not have a separate enable/disable
control pin. The PWM outputs, OUTLL/OUTLR, may be
disabled by pulling VERR to ground. Doing so reduces the
duty cycle to zero, but the upper 50% duty cycle outputs,
OUTUL/OUTUR, will continue operation. Likewise, the SR
outputs OUTLLN/OUTLRN will be active high.
CT
OUTLL
OUTLR
Pulling Soft-Start to ground will disable all outputs and set
them to a low condition
OUTLLN
(SR1)
Fault Conditions
OUTLRN
(SR2)
FIGURE 22. WAVEFORM TIMING WITH SR OUTPUTS
DELAYED, 2.575V < VADJ < 5.00V
Setting VADJ to VREF/2 results in no delay on any output.
The no delay voltage has a ±75mV tolerance window.
Control voltages below the VREF/2 zero delay threshold
cause the PWM outputs, OUTLL/LR, to be delayed. Control
voltages greater than the VREF/2 zero delay threshold cause
the SR outputs, OUTLLN/LRN, to be delayed. It should be
noted that when the PWM outputs, OUTLL/LR, are delayed,
the CS to output propagation delay is increased by the
amount of the added delay.
The delay feature is provided to compensate for mismatched
propagation delays between the PWM and SR outputs as
may be experienced when one set of signals crosses the
primary-secondary isolation boundary. If required, individual
output pulses may be stretched or compressed as required
using external resistors, capacitors, and diodes.
When the PWM outputs are delayed, the 50% upper outputs
are equally delayed, so the resonant delay setting is
unaffected.
18
A fault condition occurs if VREF or VDD fall below their
undervoltage lockout (UVLO) thresholds or if the thermal
protection is triggered. When a fault is detected the outputs
are disabled low. When the fault condition clears the outputs
are re-enabled.
An overcurrent condition is not considered a fault and does
not result in a shutdown.
Thermal Protection
Internal die over temperature protection is provided. An
integrated temperature sensor protects the device should
the junction temperature exceed +140°C. There is
approximately +15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. VDD and
VREF should be bypassed directly to GND with good high
frequency capacitance.
References
[1] Ridley, R., “A New Continuous-Time Model for Current
Mode Control”, IEEE Transactions on Power
Electronics, Vol. 6, No. 2, April 1991.
FN6754.1
September 29, 2008
ISL6754
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
N
INDEX
AREA
H
0.25(0.010) M
M20.15
B M
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
E
GAUGE
PLANE
-B1
2
INCHES
SYMBOL
3
L
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45¬
-C-
α
e
A2
A1
B
C
0.10(0.004)
0.17(0.007) M
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.337
0.344
8.56
8.74
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
α
20
0°
20
8°
0°
7
8°
Rev. 1 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
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19
FN6754.1
September 29, 2008