ISL9007 ® Datasheet October 13, 2005 FN9218.0 High Current LDO with Low IQ and High PSRR Features ISL9007 is a high performance LDO that delivers a continuous 400mA of load current. It has a low standby current and high PSRR and is stable with output capacitance of 1µF to 10µF with an ESR of up to 200mΩ. • Excellent transient response to large current steps The ISL9007 has a very high PSRR of 75dB and output noise less than 30µVRMS. When coupled with a no load quiescent current of 50µA (typical), and 1µA (max) shutdown current, the ISL9007 is an ideal choice for portable wireless equipment. The ISL9007 comes in fixed voltage options of 3.3V, 2.85V, 2.8V, and 2.5V with ±1.8% output voltage accuracy over temperature, line and load. Other voltage options are available on request. • High performance LDO with 400mA continuous output • Excellent load regulation: <0.1% voltage change across full range of load current • Very high PSRR: 75dB @ 1kHz • Wide input voltage capability: 2.3V -6.5V • Very low quiescent current: 50µA • Low dropout voltage: typically 200mV @ 400mA • Low output noise: typically 30µVrms @ 100µA(2.5V) • Stable with 1-10µF ceramic capacitors • Shutdown pin turns off LDO for 1µA (max) standby current • Soft-start to limit input current surge during enable Pinout • Current limit and overheat protection ISL9007 (8 Ld MSOP) TOP VIEW • ±1.8% accuracy over all operating conditions • 8 Ld MSOP package • -40°C to +85°C operating temperature range VO VI NC VI NC SD Applications NC GND • PDAs, Cell Phones and Smart Phones • Pb-free plus anneal available (RoHS compliant) • Portable Instruments, MP3 Players • Handheld Devices including Medical Handhelds Ordering Information PART MARKING VO VOLTAGE (Note 1) TEMP RANGE (°C) ISL9007IUNZ* (Note 2) 007NZ 3.3V -40 to +85 8 Ld MSOP (Pb-free) M8.118 ISL9007IUKZ* (Note 2) 007KZ 2.85V -40 to +85 8 Ld MSOP (Pb-free) M8.118 ISL9007IUJZ* (Note 2) 007JZ 2.8V -40 to +85 8 Ld MSOP (Pb-free) M8.118 ISL9007IUFZ* (Note 2) 007FZ 2.5V -40 to +85 8 Ld MSOP (Pb-free) M8.118 PART NUMBER PACKAGE PKG. DWG. # *Add "-T" suffix for tape and reel. NOTES: 1. For other output voltages, contact Intersil Marketing. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9007 Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V Thermal Resistance (Notes 3, 4) θJA (°C/W) 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 157 Junction Temperature Range -40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 6.5 V 70 µA DC CHARACTERISTICS Supply Voltage VIN Ground Current IDD 2.3 Quiescent condition: IO = 0µA 50 Shutdown Current IDDS 0.1 1.0 µA UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Drop-out Voltage (Note 6) Thermal Shutdown Temperature @25°C Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = 25°C -0.7 +0.7 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 400mA, TJ = 25°C -0.8 +0.8 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 400mA, TJ = -40°C to 125°C -1.8 +1.8 % Continuous 400 470 mA 540 750 mA VDO1 IO = 400mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV VDO2 IO = 400mA; 2.8V < VO 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 75 dB @ 10kHz 60 dB @ 100kHz AC CHARACTERISTICS Ripple Rejection (Note 5) IO = 10mA, VIN = 2.8V(min), VO = 1.8V Output Noise Voltage (Note 5) 40 dB IO = 100µA, VO = 1.5V, TA = 25°C BW = 10Hz to 100kHz 40 µVrms Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) 250 500 µs Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V DEVICE START-UP CHARACTERISTICS Device Enable TIme TEN LDO Soft-start Ramp Rate TSSR 2 FN9218.0 October 13, 2005 ISL9007 Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SD PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.4 V Input High Voltage VIH 1.4 VIN+0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 5. Guaranteed by design and characterization. 6. VO-x = 0.98 * VO-x(NOM). Typical Performance Curves 0.10 0.8 VO = 3.3V IL = 0mA 0.4 0.2 -40°C 0.0 25°C -0.2 +85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 -0.6 0.06 0.04 -40°C 0.02 25°C 0.00 -0.02 +85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 -0.10 6.6 0 50 300 350 400 3.4 VIN = 3.8V VO = 3.3V IL = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE (%) 250 FIGURE 2. OUTPUT VOLTAGE vs LOAD CURRENT 0.10 0.06 200 LOAD CURRENT - IO (mA) FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 0.08 150 100 INPUT VOLTAGE (V) 0.04 0.02 0.00 -0.02 -0.04 -0.06 VO = 3.3V IO = 0mA 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 -25 -10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 FIGURE 3. OUTPUT VOLTAGE vs TEMPERATURE 3 2.8 3.1 3.6 4.1 4.6 5.1 5.6 6.1 6.5 INPUT VOLTAGE (V) FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FN9218.0 October 13, 2005 ISL9007 Typical Performance Curves 2.9 350 VO = 2.8V IO = 0mA DROP OUT VOLTAGE, VDO (mV) OUTPUT VOLTAGE, VO (V) 2.8 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 2.3 2.6 3.1 3.6 4.1 4.6 5.1 6.1 5.6 300 250 200 VO = 2.8V 150 VO = 3.3V 100 50 0 6.5 0 50 100 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) 150 200 250 OUTPUT LOAD (mA) 300 350 400 FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT 80 350 70 GROUND CURRENT (µA) DROP OUT VOLTAGE, VDO (mV) VO = 3.3V 300 250 200 25°C +85°C 150 -40°C 100 50 -40°C 40 VO = 3.3V IO = 0µA 0 20 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 3.0 3.5 4.0 4.58 5.0 5.5 6.5 6.0 INPUT VOLTAGE (V) FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE 80 200 180 25°C 140 +85°C -40°C 120 100 80 60 40 0 50 100 150 200 250 300 LOAD CURRENT (mA) FIGURE 9. GROUND CURRENT vs LOAD 4 350 60 50 40 VIN = 3.8V VO = 3.3V IL = 0µA 30 VIN = 3.8V VO = 3.3V 20 GROUND CURRENT (µA) 70 160 GROUND CURRENT (µA) 25°C 30 50 0 125°C 60 400 20 -40 -25 -10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 FIGURE 10. GROUND CURRENT vs TEMPERATURE FN9218.0 October 13, 2005 ISL9007 Typical Performance Curves VO = 3.3V IL = 300mA VIN = 5.0V VO = 3.3V IL = 300mA CL = 1µF 3 CL = 1µF 4.3V VO1 (V) 2 3.6V 1 0 VEN (V) 5 10mV/DIV 0 0 100 200 300 400 500 600 700 800 900 1K 400 µs/DIV TIME (µs) FIGURE 11. TURN ON/TURN OFF RESPONSE FIGURE 12. LINE TRANSIENT RESPONSE, 3.3V OUTPUT VO = 2.8V IL = 300mA CL = 1µF VO (25mV/DIV) 4.2V 3.5V VO = 1.8V VIN = 2.8V 300mA 10mV/DIV ILOAD 100µA 100µs/DIV 400µs/DIV FIGURE 14. LOAD TRANSIENT RESPONSE FIGURE 13. LINE TRANSIENT RESPONSE, 2.8V OUTPUT 100 10 90 80 SPECTRAL NOISE DENSITY (µV/√Hz) VIN = 3.5V VO = 2.5V IO = 10mA CL = 1µF PSRR (dB) 70 60 50 40 30 20 10 0 0.1 1 10 100 FREQUENCY (kHz) FIGURE 15. PSRR vs FREQUENCY 5 1K 1 0.1 0.01 0.001 10 VIN = 3.6V VO = 1.8V ILOAD = 10mA CIN = 1µF CL = 1µF 100 1K 10K FREQUENCY (Hz) 100K 1M FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY FN9218.0 October 13, 2005 ISL9007 Pin Description Functional Description PIN # PIN NAME DESCRIPTION 1 VO LDO Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended) 2, 3, 4 NC No Connection 5 GND 6 SD LDO Shutdown. When this signal goes high, the LDO is turned off. 7 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 8 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. GND is the connection to system ground. Connect to PCB Ground plane. ISL9007 8 7 OFF 6 SHUTDOWN ON VIN VO 1 VOUT VIN SD GND 5 C1 The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart thermal shutdown protects the device against overheating. Soft-start minimize start-up input current surges without causing execssive device turn-on time. Power Control Typical Application VIN (3.0-6.5V) The ISL9007 contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9007 adjusts its biasing to achieve the lowest standby current consumption. C2 The ISL9007 has a shutdown pin, SD, to control power to the LDO output. When SD is high, the device is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. When the SD pin goes low, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least 2.1V (typical). Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry turn on. Once the references are stable, the LDO powers up. During operation, whenever the VIN voltage drops below about 1.84V, the ISL9007 immediately disables both LDO outputs. When VIN rises back above 2.1V (assuming the SD pin is low), the device re-initiates its start-up sequence and LDO operation will resume automatically. C1, C2: 1µF X5R ceramic capacitor Reference Generation Block Diagram The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. VIN VO VIN UVLO CONTROL LOGIC A current generator provides references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START LDO Regulation and Programmable Output Divider SD BANDGAP AND TEMPERATURE SENSOR GND 6 The bandgap generates a zero temperature coefficient (TC) voltage for the regulator reference and other voltage references required for current generation and overtemperature detection. The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9000 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output FN9218.0 October 13, 2005 ISL9007 capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9007 provides short-circuit protection by limiting the output current to about 500mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory to one of the following output voltages: 3.3, 2.85V, 2.8V, and 2.5V. 7 Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 145°C, the LDO momentarily shuts down until the die cools sufficiently. In the overheat condition, if the LDO sources more than 50mA it will be shut off. Once the die temperature falls back below about 110°C, the disabled LDO is re-enabled and soft-start automatically takes place. FN9218.0 October 13, 2005 ISL9007 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L1 SEATING PLANE C D 0.20 (0.008) C a CL E1 0.20 (0.008) C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C SIDE VIEW MIN A L1 -A- e SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 7 - - 0.07 - - 5o 15o - 0o 6o - 0.07 0.003 - 5o 15o 0o 6o -B- Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN9218.0 October 13, 2005