ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 DUAL DIGITAL ISOLATORS Check for Samples: ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1 FEATURES 1 • • • Qualified for Automotive Applications 1-Mbps and 25-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew: 1 ns (Max) – Low Pulse-Width Distortion (PWD): 1 ns (Max) – Low Jitter Content: 1 ns (Typ) at 150 Mbps 25-Year (Typ) Life at Rated Voltage (See Application Report SLLA197 and Figure 14) • • • • • 4000-Vpeak Isolation, 560 Vpeak VIORM – UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2), IEC 61010-1, IEC 60950-1 and CSA Approved – 50 kV/μs Typical Transient Immunity Operates with 3.3-V or 5-V Supplies 4 kV ESD Protection High Electromagnetic Immunity –40°C to 125°C Operating Free-Air Temperature Range DESCRIPTION The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. The small capacitance and resulting time constant provide fast operation with signaling rates available from 0 Mbps (dc) to 25 Mbps. (1)The A-option and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. These devices require two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation over the ambient temperature range of –40°C to 125°C. (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2012, Texas Instruments Incorporated ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SIGNALING RATE TA –40°C to 125°C (2) ORDERABLE PART NUMBER TOP-SIDE MARKING 1 Mbps SOIC – D Reel of 2500 ISO7220AQDRQ1 7220AQ 1 Mbps SOIC – D Reel of 2500 ISO7221AQDRQ1 7221AQ 25 Mbps SOIC – D Reel of 2500 ISO7221CQDRQ1 7221CQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. ISO7221 VCC1 1 INA INB 2 GND1 4 Isolation ISO7220 3 8 VCC2 7 OUTA OUTB GND2 6 5 VCC1 1 OUTA INB 2 GND1 4 3 Isolation (1) PACKAGE (2) 8 VCC2 7 INA OUTB GND2 6 5 SINGLE-CHANNEL FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel IN Filter OSC + PWM Vref Input + Filter Vref Pulse Width Demodulation Carrier Detect Data MUX AC Detect OUT Output Buffer AC Channel REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File Number: 40016131 File Number: 1698195 File Number: E181974 (1) 2 Production tested ≥3000 VRMS for 1 second in accordance with UL 1577. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN, OUT –0.5 V to 6 V IO Output current ±15 mA Human-Body Model ESD Electrostatic discharge ±4 kV Field-Induced Charged-Device Model All pins ±1 kV Machine Model TJ Maximum junction temperature Tstg Storage temperature (1) (2) ±200 V 150°C –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (1) IOH High-level output current IOL Low-level output current tui VCC1, VCC2 TYP 3 MAX 5.5 4 –4 Input pulse width UNIT V mA mA ISO722xA 1 0.67 ISO722xC 40 33 ISO722xA 0 1500 ISO722xC 0 30 μs ns 1000 kbps 25 Mbps 1/tui Signaling rate VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V TJ Operating virtual-junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 certification (1) –40 150 °C 1000 A/m For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 3 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5 V (1), over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ISO7220x ISO7221x ICC1 Supply current, VCC1 ISO7220A ISO7221A ISO7221C ISO7220x ISO7221x ICC2 Supply current, VCC2 ISO7220A ISO7221A ISO7221C VOH High-level output voltage VOL Low-level output voltage MIN Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps MAX 1 2 8.5 17 2 3 10 18 12 22 16 31 8.5 17 17 32 10 18 12 22 IOH = –4 mA, See Figure 1 VCC – 0.8 4.6 IOH = –20 μA, See Figure 1 VCC – 0.1 5 0.2 0.4 IOL = 20 μA, See Figure 1 0 0.1 150 IIH High-level input current IN from 0 V to VCC IIL Low-level input current IN from 0 V to VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 UNIT mA mA V IOL = 4 mA, See Figure 1 VI(HYS) Input voltage hysteresis (1) TYP V mV 10 μA μA –10 1 pF 25 50 kV/μs MIN TYP MAX UNIT 280 405 480 ns 1 14 ns 22 32 42 ns 1 2 ns For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS VCC1 = VCC2 = 5 V, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay (1) ISO722xA See Figure 1 PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 1 tf Output signal fall time See Figure 1 1 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) 4 (2) (3) ISO722xC See Figure 1 ISO722xA 180 ISO722xC 10 ISO722xA 3 15 ISO722xC 0.2 1 ns ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS VCC1 = 5 V, VCC2 = 3.3 V (1), over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ISO7220x ISO7221x ICC1 Supply current, VCC1 ISO7220A ISO7221A ISO7221C ISO7220x ISO7221x ICC2 Supply current, VCC2 ISO7220A ISO7221A ISO7221C Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load Quiescent VI = VCC or 0 V, no load 1 Mbps VI = VCC or 0 V, no load 25 Mbps VI = VCC or 0 V, no load MIN ISO7220x VOH ISO7221x (5-V side) High-level output voltage Low-level output voltage 1 2 8.5 17 2 3 10 18 12 22 8 18 4.3 9.5 9 19 5 11 6 12 VCC – 0.8 UNIT mA mA V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VI(HYS) Input voltage hysteresis 150 IIH High-level input current IN from 0 V to VCC IIL Low-level input current IN from 0 V to VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) MAX VCC – 0.4 IOH = –4 mA, See Figure 1 IOH = –20 μA, See Figure 1 VOL TYP V mV 10 μA μA –10 1 pF 15 40 kV/μs MIN TYP MAX UNIT 285 410 480 ns 1 14 ns 36 48 ns 2 ns For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS VCC1 = 5 V, VCC2 = 3.3 V, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) (2) ISO722xA ISO722xC See Figure 1 25 See Figure 1 1 ISO722xA 180 ISO722xC 10 tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 2 tf Output signal fall time See Figure 1 2 tfs Failsafe output delay time from input power loss See Figure 2 3 (1) (2) (3) (3) ISO722xA 3 15 ISO722xC 0.2 1 ns ns ns μs Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 5 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 = 3.3 V, VCC2 = 5 V (1), over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ISO7220x ISO7221x ICC1 Supply current, VCC1 ISO7220A ISO7221A ISO7221C ISO7220x ISO7221x ICC2 Supply current, VCC2 ISO7220A ISO7221A ISO7221C Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps ISO7220x VOH ISO7221x (3.3-V side) High-level output voltage 0.6 1 4.3 9.5 1 2 5 11 6 12 16 31 8.5 17 18 32 10 18 12 22 UNIT mA mA V VCC – 0.1 IOL = 4 mA, See Figure 1 Low-level output voltage MAX VCC – 0.4 0.4 IOL = 20 μA, See Figure 1 0 VI(HYS) Input threshold voltage hysteresis 0.1 150 IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) TYP VCC – 0.8 IOH = –4 mA, See Figure 1 IOH = –20 μA, See Figure 1 VOL MIN V mV 10 μA μA –10 1 pF 15 40 kV/μs MIN TYP MAX UNIT 285 395 480 ns 1 18 ns 36 48 ns 3 ns For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS VCC1 = 3.3 V, VCC2 = 5 V, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) (2) ISO722xA ISO722xC See Figure 1 24 See Figure 1 1 ISO722xA 190 ISO722xC 10 tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 1 tf Output signal fall time See Figure 1 1 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) 6 (3) ISO722xA 3 15 ISO722xC 0.2 1 ns ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS VCC1 = VCC2 = 3.3 V (1), over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS ISO7220x ISO7221x ICC1 Supply current, VCC1 ISO7220A ISO7221A ISO7221C ISO7220x ISO7221x ICC2 Supply current, VCC2 ISO7220A ISO7221A ISO7221C VOH High-level output voltage VOL Low-level output voltage MIN Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps Quiescent 1 Mbps VI = VCC or 0 V, no load 25 Mbps MAX 0.6 1 4.3 9.5 1 2 5 11 6 12 8 18 4.3 9.5 9 19 5 11 6 12 IOH = –4 mA, See Figure 1 VCC – 0.4 3 IOH = –20 μA, See Figure 1 VCC – 0.1 3.3 0.2 0.4 IOL = 20 μA, See Figure 1 0 0.1 150 IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 UNIT mA mA V IOL = 4 mA, See Figure 1 VI(HYS) Input voltage hysteresis (1) TYP V mV 10 μA μA –10 1 pF 15 40 kV/μs MIN TYP MAX UNIT 290 400 485 ns 1 18 ns 25 40 52 ns 1 3 ns For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS VCC1 = VCC2 = 3.3 V, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay (1) ISO722xA See Figure 1 PWD Pulse-width distortion |tpHL – tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL – tpLH| (1) tsk(pp) Part-to-part skew (2) tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 2 tf Output signal fall time See Figure 1 2 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) (3) ISO722xC See Figure 1 ISO722xA 190 ISO722xC 10 ISO722xA 3 15 ISO722xC 0.2 1 ns ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 7 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI 0V or VCC1 A. ISOLATION BARRIER VCC1 IN VCC1 OUT VI 2.7 V VO 0V VOH tfs CL NOTE A VO 50% FAILSAFE HIGH VOL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 ISOLATION BARRIER C = 0.1 mF± 1% IN GND1 C = 0.1 mF± 1% Pass-fail criteria: Output must remain stable OUT NOTE A VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit VCC1 DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 8 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 DEVICE INFORMATION IEC PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 ≥175 V Minimum internal gap (internal clearance) Distance through the insulation 0.008 mm RIO SOIC-8 4.8 mm 4.3 mm Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C Isolation resistance Input to output, VIO = 500 V, 100°C ≤ TA ≤ max >1012 Ω 11 Ω >10 CIO Barrier capacitance input to output VI = 0.4 sin (4E6πt) 1 pF CI Input capacitance to ground VI = 0.4 sin (4E6πt) 1 pF NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary . Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group IIIa Rated mains voltage ≤150 VRMS I-IV Rated mains voltage ≤300 VRMS I-III Rated mains voltage ≤400 VRMS I-II IEC 60747-5-2 INSULATION CHARACTERISTICS (1) PARAMETER VIORM TEST CONDITIONS Maximum working insulation voltage SPECIFICATION UNIT 560 V 1050 V VPR Input to output test voltage Method b1, VPR = VIORM × 1.875, 100% Production test with t = 1 s, Partial discharge <5 pC VIOTM Transient overvoltage t = 60 s 4000 V RS Insulation resistance VIO = 500 V at TS >109 Ω Pollution degree (1) 2 Climatic Classification 40/125/21 Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 9 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com DEVICE I/O SCHEMATICS Input VCC1 VCC1 VCC1 Output VCC2 750 kW 8W 500 W IN OUT 13 W IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current SOIC-8 TS Maximum case temperature SOIC-8 MIN MAX θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 124 θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 190 150 UNIT mA °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 10 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 SOIC-8 PACKAGE THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Low-K thermal resistance θJA Junction-to-air thermal resistance θJB Junction-to-board thermal resistance θJC Junction-to-case thermal resistance (1) MIN TYP (1) MAX 212 High-K thermal resistance 122 UNIT °C/W 37 °C/W 69.1 °C/W Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. 250 225 VCC1,2 at 3.6 V Safety Limiting Current - mA 200 175 150 125 VCC1,2 at 5.5 V 100 75 50 25 0 0 50 100 150 TC - Case Temperature - °C 200 Figure 5. SOIC-8 θJC THERMAL DERATING CURVE per IEC 60747-5-2 DEVICE FUNCTION TABLE Table 1. ISO7220x or ISO7221x (1) INPUT SIDE VCC OUTPUT SIDE VCC PU PU PD (1) PU INPUT IN OUTPUT OUT H H L L Open H X H PU = Powered up(Vcc ≥ 3.0 V), PD = Powered down (Vcc ≤ 2.5 V), X = Irrelevant, H = High level, L = Low level Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 11 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTIC CURVES 3.3-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 5-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 20 30 TA = 25°C, 15 pF Load 18 26 ISO7220x ICC2 24 14 ICC - Supply Current - mA 16 ICC - Supply Current - mA TA = 25°C, 15 pF Load 28 ISO7220x ICC2 12 10 ISO7221x ICC1&2 8 6 4 ISO7220x ICC1 22 20 ISO7221x ICC1&2 18 16 14 12 10 ISO7220x ICC1 8 6 4 2 2 0 0 0 25 50 75 0 100 25 Signaling Rate - Mbps 50 75 Signaling Rate - Mbps 100 Figure 6. Figure 7. ISO722xA AND ISO722xC INPUT VOLTAGE LOW-TO-HIGH SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE VCC FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE 2.92 1.4 5-V Vth+ 1.35 2.9 15 pF Load VCC = 3.3 V or 5 V 3.3-V Vth+ 2.88 1.25 15 pF Load 1.2 1.15 5-V Vth1.1 Failsafe Threshold - V Input Voltage Threshold - V VFS 1.3 2.86 2.84 2.82 VFS2.8 1.05 3.3-V Vth1 -40 -25 -10 5 20 35 50 65 Temperature - °C Figure 8. 12 Submit Documentation Feedback 80 95 110 125 2.78 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature - °C Figure 9. Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTIC CURVES (continued) HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 70 -80 15 pF Load TA = 25°C -70 15 pF Load TA = 25°C 60 VCC = 5 V -60 50 VCC = 5 V IOUT - mA IOUT - mA -50 -40 -30 VCC = 3.3 V -20 40 VCC = 3.3 V 30 20 10 -10 0 0 0 2 4 6 0 1 2 3 VOUT - V VOUT - V Figure 10. Figure 11. Copyright © 2009–2012, Texas Instruments Incorporated 4 Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 5 13 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION Typical Applications V CC 1 V CC 2 0.1mF 2 mm max . from Vcc 1 INPUT 1 INA 2 INB INPUT 3 4 8 OUTA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF OUTPUT OUTPUT ISO 7220 GND 1 GND 2 Figure 12. Typical ISO7220 Application Circuit V CC 1 V CC 2 0.1mF 2 mm max . from Vcc 1 OUTA OUTPUT INB INPUT 1 2 3 4 8 INA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF INPUT OUTPUT ISO 7221 GND 1 GND 2 Figure 13. Typical ISO7221 Application Circuit WORKING LIFE -- YEARS 100 VIORM at 560 V 28 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (V IORM ) -- V Figure 14. Time-Dependent Dielectric Breakdown Test Results 14 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 ISOLATION GLOSSARY Creepage Distance — The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance — The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit — An internal circuit directly connected to an external supply mains or other equivalent source which supplies the primary circuit electric power. Secondary Circuit — A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials which is defined as the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 15 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 SLLS965C – JULY 2009 – REVISED MAY 2012 www.ti.com Insulation: Operational insulation — Insulation needed for the correct operation of the equipment. Basic insulation — Insulation to provide basic protection against electric shock. Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation — Insulation comprising both basic and supplementary insulation. Reinforced insulation — A single insulation system which provides a degree of protection against electric shock equivalent to double insulation. Pollution Degree: Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation which is to be expected. Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Installation Category: Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664. I: Signal Level — Special equipment or parts of equipment. II: Local Level — Portable equipment etc. III: Distribution Level — Fixed installation IV: Primary Supply Level — Overhead lines, cable systems Each category should be subject to smaller transients than the category above. 16 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 www.ti.com SLLS965C – JULY 2009 – REVISED MAY 2012 REVISION HISTORY Changes from Revision B (March 2010) to Revision C • Page Added storage temperature to Abs Max table. ..................................................................................................................... 3 Copyright © 2009–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7220A-Q1 ISO7221A-Q1 ISO7221C-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ISO7220AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7221AQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7221CQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1 : • Catalog: ISO7220A, ISO7221A, ISO7221C Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 22-May-2012 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7220AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7221AQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7221CQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7220AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 ISO7221AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 ISO7221CQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such components to meet such requirements. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated