TECHNICAL DATA IN74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger N SUFFIX PLASTIC The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The IN74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-toHIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 3.6 V • Low input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ • High Noise Immunity Characteristic of CMOS Devices 14 1 D SUFFIX SOIC 14 1 ORDERING INFORMATION IN74LV74N IN74LV74D IZ74LV74 Plastic DIP SOIC chip TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 1 14 V CC DATA 1 2 13 RESET 2 CLOCK 1 3 12 DATA2 SET 1 4 11 CLOCK 2 Q1 5 10 SET 2 Q1 6 9 Q2 GND 7 8 Q2 FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Outputs Set Reset Clock Data Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X No Change H H H X No Change H H X No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. H= high level L = low level X = don’t care Z = high impedance INTEGRAL 1 IN74LV74 MAXIMUM RATINGS * Symbol VCC IIK * Value Unit DC supply voltage -0.5 to +5.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±35 mA VCC current ±70 mA GND current ±70 mA Power dissipation per package: Plastic DIP * 4 SO * 4 750 500 IOK * IO * Parameter 3 ICC IGND PD Tstg mW Storage Temperature TL -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: - 8 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.2 3.6 V VCC DC Supply Voltage VI DC Input Voltage 0 VCC V VO DC Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, t f Input Rise and Fall Time except for Schmitttrigger inputs (Figure 1) 0 0 0 0 1000 700 500 400 ns VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must b e left open. INTEGRAL 2 IN74LV74 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C 125°C Unit min max min max min max VIH HIGH level input voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL LOW level output voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH HIGH level output voltage VI = VIH or VIL IO = -50 µÀ 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIH or VIL IO = -6mÀ 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = 50 µÀ 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIH or VIL IO = 6 mÀ 3.0 - 0.33 - 0.4 - 0.5 V Input current VI = VCC or 0 V * - ±0.1 - ±1.0 - ±1.0 µÀ Supply current VI =VCC or 0 V IO = 0 µÀ * - 4.0 - 40 - 80 µÀ VOL II ICC LOW level output voltage * VCC = 3.3 ± 0.3 V AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f=6.0 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C 125°C min max min max min max Unit tPHL, tPLH Propagation delay , Clock to Q or Q VI = 0 V or VCC Figures 1,3 1.2 2.0 * - 140 45 28 - 160 56 35 - 180 67 42 ns tPHL, tPLH Propagation delay , Set to Q or Q VI = 0 V or VCC Figures 2,3 1.2 2.0 * - 150 44 27 - 170 54 34 - 190 65 41 ns tPHL, tPLH Propagation delay , Reset to Q or Q VI = 0 V or VCC Figures 2,3 1.2 2.0 * - 160 47 29 - 180 58 37 - 200 70 44 ns tTHL, tTLH Output Transition Time, Any Output VI = 0 V or VCC Figures 1,3 1.2 2.0 * - 90 20 15 - 110 25 19 - 130 30 23 ns 3.0 - 7.0 - - - - pF CI Input capacitance INTEGRAL 3 IN74LV74 CPD Power dissipation capacitance (per flip-flop) INTEGRAL VI = 0 V or VCC - 48 - - - - pF 4 IN74LV74 TIMING REQUIREMENTS (CL=50 pF, t r=t f=6.0 ns) Test VCC conditions V Symbol Parameter tw Puls e Width, Clock, Set or Reset VI = 0 V or VCC Figures 1,2,3 tsu Setup Time, Data to Clock Guaranteed Limit 25°C -40°C to 85°C 125°C Unit min max min max min max 1.2 2.0 * 75 25 16 - 96 32 20 - 114 38 24 - ns VI = 0 V or VCC Figures 1,3 1.2 2.0 * 25 16 10 - 32 20 13 - 40 24 15 - ns Removal Time, Set or Reset to Clock VI = 0 V or VCC Figures 2,3 1.2 2.0 * 18 9 6 - 24 12 8 - 30 15 9 - ns th Hold Time, Clock to Data VI = 0 V or VCC Figures 1,3 1.2 2.0 * 3 3 3 - 5 3 3 - 5 3 3 - ns fc Clock Frequency VI = 0 V or VCC Figures 1,3 1.2 2.0 3.0 8 18 30 - 6 15 24 - 4 12 20 - MHz trem * VCC = 3.3 ± 0.3 V V M = 0.5 ∗ VCC VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms INTEGRAL 5 IN74LV74 V M = 0.5 ∗ VCC Figure 2. Switching Waveforms TEST POINT DEVICE UNDER TEST OUTPUT * CL * Includes all probe and jig capacitance Figure 3. Test Circuit EXPANDED LOGIC DIAGRAM (ONE FLIP-FLOP) INTEGRAL 6 IN74LV74 CHIP PAD DIAGRAM Chip marking 25LV74 12 11 10 13 09 08 1.17 + 0.03 14 01 02 Y (0,0) 07 04 03 05 06 1.32 + 0.03 X Location of marking (mm): left lower corner x=0.520, y=0.865. Chip thickness: 0.46 ± 0.02 mm. PAD LOCATION Pad No Symbol 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Reset 1 Data 1 Clock 1 Set 1 Q1 Q1 GND Q2 Q2 Set 2 Clock 2 Data 2 Reset 2 VCC Location (left lower corner), mm X 0.118 0.118 0.286 0.597 0.895 1.100 1.100 1.100 1.100 0.851 0.540 0.297 0.118 0.118 Y 0.436 0.125 0.125 0.125 0.125 0.125 0.423 0.721 0.930 0.949 0.949 0.949 0.830 0.604 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 Note: Pad location is given as per metallization layer INTEGRAL 7