ETC L4985

L4985
HIGH EFFICIENCY SWITCHING REGULATOR
PRODUCT PREVIEW
OPERATING INPUT VOLTAGE:
FROM 4.5V TO 21V
HIGHEFFICIENCY 3A STEP DOWN CONVERTER
3A @ 3.3V OUTPUT VOLTAGE FROM 4.5V
INPUT VOLTAGE
ADJUSTABLE OUTPUT VOLTAGE
FROM 1.28V
GATE DRIVER FOR SYNCHRONOUS
RECTIFICATION
100% MAXIMUM DUTY CYCLE
INTERNAL CURRENT LIMIT
SOFT START, RESET SIGNAL,
THERMAL SHUTDOWN
AUXILIARY CONVERTER WITH 40V
OPEN DRAIN SWITCH DELIVERING 5W
@ VIN = 12V
1.7A PEAK CURRENT INTERNALLY
LIMITED (TYP)
POWER MANAGEMENT
MULTIPOWER BCD TECHNOLOGY
—
—
—
—
—
POWERDIP 16+2+2
SO20
—
ORDERING NUMBERS: L4985 (Powerdip)
L4985D (SO20)
—
DESCRIPTION
This high efficiency DC-DC converter is a monolithic device developed to generate all the voltages required in multioutputs DC-DC converters,
in particular when the supply voltage is a battery,
and isolation is not needed.
Designed to start to operate at an input voltage as
low as 4.5V up to 21V, the device takes the advantages offered by our proprietary BCD Multipower technology to deliver 3A to the load on
the stepdown section, and to manage 1.5A peak
current on the open drain section.
The packages proposed are in plastic dual in line,
Powerdip 20 (16+2+2) for standard assembly,
and SO20L for SMD assembly.
This device is constitueed by two major sections:
one section is a stepdown regulator, and the
other one is a flexible regulator with open drain
output DMOS transistor, source grounded, for flyback/forward topologies for multioutputs, or stepup topology when a single voltage higher than the
supply one is requested.
March 1995
Step Down Converter Section
The stepdown section, delivering to the load up to
3A current, at an output voltage adjustable from
1.28V up to 16V, works in voltage mode, fixed frequency, with no limitation on the max duty cycle.
This section has been designed to maximise the
efficiency minimising the conduction losses and
the quiescent current.
An internal step-up converter using a small chip
inductor and a filter capacitor provides voltage
and energy the gate driver of the internal N-channel DMOS transistor of 0.1Ω typ of Rdson, and the
driver of an external DMOS transistor that should
require no more than 30nC of gate charge, at
100KHz.
The gate driver pin can be left open if the use of a
Schottky diode is preferred.
An internal pulse by pulse current limiting protects
the device it self and the load from overload and
short circuit conditions.
A reset block, monitoring the feedback voltage,
with an programmable reset delay time, generates a reset signal for the microprocessor.
The reset output is an open drain.
Moreover, the DIS1 pin, active low, will inhibit the
whole device, reducing to leakage only the current consumption from the battery.
1/23
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L4985
Open Drain Converter Section
It’s a low power converter, capable to deliver a global output power in excess of 5W
@ VIN = 12V.The max power delivered is depending on the supply voltage and on the topology used.
The open drain DMOS Rdson is 1Ω typ and a max
voltage breakdown is 40V.
This section required few components just a voltage dueder to fix the output voltage.
DIS2 pin, when low, inhibits this section, reducing
to zero the quiescent current consumption of this
section.
BLOCK DIAGRAM
DIS1
DIS2
3
ON/OFF
THERMAL
SHUTDOWN
SS
COMP
14
VFB
19
LBOOST
7
8
ON/OFF
STEP-UP
VA2
UVLO
SOFT
START
Vref
GOOD LOGIC
13
1.28V
VA1
VDD
2
CURRENT
LIMITING
Vref
1
+
E/A
-
3
-
VA1
2
S
DRIVER
Q
1
2
4
9
11
CURRENT
LIMITING
OSC
RESET
OUT
18
MAX D.C.
LIMITING
OSC
DIS1 VFB
1
3
S
1
Q
RESET
RESET DELAY
12
VFB AUX
GTDR
AUX
OUT
DRIVER
10
1.28V
OUT
Q
2
20
2/23
3
2
Vref
VA2
R
1
Vs
R Q
PWM
+
17
5,6,15,16
SGND
D95IN198
PWGND
L4985
ABSOLUTE MAXIMUM RATINGS
Symbol
Pins
VS
17
Value
Unit
Input Voltage
Parameter
25
V
VAUX OUT
11
Input Operating Voltage
20
V
Auxiliary Drain Voltage
40
IOUT
4
Maximum Output Current
internally limited
V
IAUX OUT
11
Maximum Auxiliary Output Current
internally limited
DIS 1
3
Disable 1 Voltage
25
V
DIS 2
2
Disable 2 Voltage
25
V
ROUT
1
Reset Output Voltage
25
V
12,13,14,19
Analog Inputs
3.5
V
COMP
13
Sink Current
5
mA
SS
14
Soft start Sink Current
5
mA
OUT
4
Output Peak Voltage at 0.1µs fsw = 100KHz
-2
V
GTDR
9
Output Gate Charge at fsw = 100KHz
30
nC
VDD
7
Step-up Output Voltage
VCC +14V
V
LBOOST
8
Step-up Input Voltage
VCC +14V
V
1.3
W
Power Dissipation at Tamb < 70°C (PDIP 20)
PTOT
Power Dissipation at Tamb < 70°C (SO 20L)
Tj ,Tstg
Junction and Storage Temperature
1
W
-40 to 150
°C
PIN CONNECTION
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction Ambient
max
PDIP 20
SO 20
Unit
60
80
°C/W
3/23
L4985
PIN FUNCTIONS
N.
Name
Function
1
RESET OUT
Open drain reset output. The output is high when the stepdown output voltage is nominal
2
DIS 2
A signal (active low) disables only the auxiliary DC-DC converter.
3
DIS 1
A signal (active low) disables the device (sleep mode operation)
4
OUT
Stepdown regulator output
5, 6,
15, 16
SGND
7
VDD
8
LBOOST
Signal Ground
Regulated step-up output. This output can deliver also 1mA for external function.
Step-up open drain, to be connected to the chip inductor.
9
GTDR
10
PWGND
Synchronous gate driver for external power MOS
Power ground
11
AUX OUT
Auxiliary output, open drain converter for boost or flyback / forward topologies
12
VFB AUX
Feedback of the auxiliary DC-DC converter
13
COMP
14
SS
E/A output to be used for frequency compensation
Soft start time constant. A capacitor connected between this pin and ground determinates
the soft start time.
Input supply voltage
17
VS
18
OSC
An external capacitor connected between this pin and ground fixes the switching
frequency.
19
VFB
Stepdown feedback input . It is directly connected to the output for 1.28V; a voltage
divider is requested for higher output voltages.
20
RESET DELAY
Connecting a capacitor between this terminal and ground,a delay time reset is fixed.
ELECTRICAL CHARACTERISTICS (V17 = 12V; Tj = 25°C; Cosc = 560pF;unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
20
V
DYNAMIC CHARACTERISTICS
VI
Input Voltage Range
IO = 3A; VO = VREF
4.5
VO
Output Voltage Range
IO = 3A; VS = 18V
VREF
fSW
V19
VL
Switching Frequency
Feedback Voltage
Line and Load Regulation on
Feedback Voltage
IO = 0.5A
V17 = 5 to 18V; IO = 0.5 to 3A;
VO = VREF
Dropout Voltage
V17 - V4
n
Efficiency
I4
Max Limiting Current
16
V
83
1.28
1.28
93
1.306
1.318
KHz
V
V
IO = 3A
0.3
0.4
V
IO = 3A 0 < Tj < 125°C
VO = 5V; IO = 3A
DIS 2 = LOW; DIS 1 = HIGH
V17 = 8 to 18V; VO = 5V
0.45
85
0.6
V
%
73
1.254
1.242
4.25
4.75
A
δfSW / δVS
Voltage Stability of Switching
Frequency
V17 = 5 to 18V
3.75
1
2
%
δfSW / δTj
Temperature Stability of
Switching Frequency
Tj = 0 to 70°C
4
6
%
0.26
0.5
V
1
10
9.5
2
V
V
V
70
70
100
100
ns
ns
GTDR GATE DRIVER OUTPUT
4/23
V9
Output Low Level
ISINK = 10mA
V9
Output High Level
ISINK = 30mA
ISOURCE = 3mA
ISOURCE = 10mA
tr
tf
Rise Time
Fall Ttime
C L = 1nF
C L = 1nF
8.3
8.3
L4985
ELECTRICAL CHARACTERISTICS (V17 = 12V; Tj = 25°C; Cosc = 560pF;unless otherwise specified.)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
AUXILIARY OUTPUT SECTION
V11 - V10
Dropout Voltage
I11
Maximum Limiting Current
V12
Internal Reference Voltage
IO2 = 0.5A
0.5
0.8
V
IO2 = 0.5A; 0 ≤ Tj ≤ 125°C
0.8
1.3
V
VO2 = 24V; IO2 = 50mA
1.2
1.7
2.2
A
1.244
1.28
1.316
V
6
9
RESET FUNCTION
V1
Output Saturation Voltage
I20
Delay Source Current
I1 = 10mA
0.4
V
12
µA
VdH
Delay High Level Threshold Vol.
VdL
Delay Low Level Threshold Vol.
0.4
V
Vtr
Rising Threshold Voltage
VREF
-70mV
V
Vtf
Falling Threshold Voltage
VREF
-210mV
V
I1
Leakage Current
2.5
V
50
µA
65
µA
SOFT START
I14
Soft Start Source Current
V14
Output Saturation Voltage
45
ISINK = 3mA
55
0.5
V
DISABLE (1&2) FUNCTION
VHL
High Level Voltage
VLL
Low Level Voltage
3
V
ISINK H
ISINK High Level
10
ISINK L
ISINK Low Level
1
0.9
V
90
µA
µA
DC CHARACTERISTICS
I17
Total Quiescent Current
V19 = 1.5V V17 = 20V
DIS1 = DIS2 = HIGH
3.5
7
mA
I4
Output Leakage Current
V17 = 20V;
DIS 1 = LOW; DIS2
10
80
µA
I11
Auxiliary Output Leakage
Current
V11 = 40V;
DIS 2 = LOW
20
100
µA
I17
Quiescent Current
V17 = 20V; V19 = 1.5V
DIS 2 = LOW DIS1 = HIGH
DIS 1 = LOW DIS2
3
70
5
150
mA
µA
0.3
V
ERROR AMPLIFIER
VOH
High Level Output Voltage
I13 = 0.5mA; V19 = 1.2V
VOL
Low Level Output Voltage
I13 = 1mA; V19 = 1.35V
Gv
Unit Gain Bandwith
1.5
Ib
Input Bias Current
0.5
DC Open Loop Gain
80
GDC
2.4
2.8
0.15
V
MHz
2
µA
dB
OSCILLATOR SECTION
V18
Ramp Valley
0.5
0.63
0.76
V18
Ramp Peak
1.9
2
2.1
Isink
Sink Current
3.2
mA
Source Current
60
µA
ISOURCE
V
V
5/23
L4985
Figure 1: Dropout voltage between Pin 17 and
Pin 4 vs. output current (step down
converter.
D95IN172
V17-V4
(V)
Figure 2: Dropout voltage between Pin 17 and
Pin 4 vs. Junction Temperature
V17-V4
(V)
D95IN173
0.5
Tj=125°C
0.4
0.4
Io=3A
Tj=25°C
0.3
0.2
0.2
Tj=-25°C
0.1
0.0
0.0
0.0
1.0
2.0
3.0
-50
Io(A)
Figure 3: Dropout voltage between Pin 11 and
Pin 10 vs. switch output current
(auxiliary converter)
V11-V10
(V)
D95IN174
2.5
0
50
100
Tj(°C)
Figure 4: Dropout voltage between Pin 11 and
Pin 10 vs. Junction Temperature
V11-V10
(V)
D95IN175
2.0
Tj=125°C
2.0
1.5
Tj=25°C
Io=1A
1.5
1.0
1.0
Tj=-25°C
0.5
0.5
0.0
0.0
0.0
0.5
1.0
1.5
Io(A)
Figure 5: Power dissipation (device only) vs.
supply voltage (refer to test circuit of
fig.29 with D1 = SB540, Pin 9 = open)
D95IN176
Pd
(W)
-50
0
50
100
Tj=(°C)
Figure 6: Power dissipation (device only) vs.
supply voltage (see test circuit fig. 28,
with D1 = SB540, pin 9 open
Pd
(W)
D95IN177
Cosc=560pF, Tamb=25°C
Vo=5.1V, DIS2=LOW
Cosc=560pF, Vout=3.3V
DIS2=LOW, Tamb=25°C
1.5
1.5
Io=3A
Io=3A
1.0
1.0
Io=2A
Io=2A
0.5
0.5
Io=1A
Io=1A
0.0
6/23
0.0
4
8
12
16
20
V17(V)
4
8
12
16
20
V17(V)
L4985
Figure 7:Power dissipation (device only) vs.
output current (see test circuit fig. 28/29
with D1 = SB540, pin 9 open).
D95IN178
Pd
(W)
V17=12V, Cosc=560pF
Tamb=25°C,DIS2=LOW
Figure 8: Current consumpion vs. junction
temperature.
D95IN183
I17
(µA)
80
1.5
DIS1=LOW
V 17=12V
60
1.0
40
Vo=5.1V
0.5
20
Vo=3.3V
0.0
0.0
1.0
2.0
3.0 Io(A)
Figure 9: Quiescent current vs. supply voltage.
I17
(mA)
D95IN180
0
-50
0
50
100
Tj(°C)
Figure 10: Quiescent current vs. supply voltage.
D95IN181
I17
(mA)
12
6
DIS1=HIGH
DIS2 =LOW
Tj=25°C, DC=50%
10
DIS1=HIGH
DIS2 =LOW
Tj=25°C, DC=0%
8
4
6
4
2
2
0
4
8
12
16
20
V17(V)
Figure 11: Quiescent current vs. junction
temperature
DIS1=HIGH
DIS2 =LOW
V17=12V, DC=0%
4.5
4
8
12
16
20
V17(V)
Figure 12: Current consumption vs. supply voltage
D95IN182
I17
(mA)
0
D95IN179
I17
(µA)
100
DIS1=LOW
Tj=25°C
80
60
3.0
40
1.5
20
0.0
-50
0
0
50
100
Tj(°C)
4
8
12
16
20
V17(V)
7/23
L4985
Figure 13: Oscillator frequency vs. supply voltage
D95IN184
fsw
(KHz)
Figure 14: Oscillator frequency vs. temperature
fsw
(KHz)
D95IN185
Cosc=560pF
Io=0.1A
V17=12V
90
Cosc=560pF, Io=0.1A
Tj=25°C
90
87
84
80
81
70
78
75
4
8
12
16
20
V17(V)
Figure 15: Reference voltage (pin 19) line regulation
D95IN186
V19
(V)
60
-50
0
V17=12V
1.325
1.29
1.300
1.28
1.275
1.27
12
16
20
V17(V)
Figure 17: Open loop frequency and phase response of error amplifier
G
(dB)
D95IN188
Phase
120
1.250
-50
0
100
Tj(°C)
SVRR
(dB)
D95IN189
70
V17=12V, Vo=3.3V
Io=0.1A
60
Gv
80
120
∅
80
20
40
0
-20
0.001 0.01
50
40
40
8/23
50
Figure 18: Supply voltage ripple rejection vs. frequency (from input to output voltage,
test circuit of fig. 28 with D1 = SB540,
pin 9 = Open)
160
100
60
Tj(°C)
D95IN187
V19
(V)
1.30
8
100
Figure 16: Reference voltage (pin 19) vs junction
temperature
Tj=25°C
4
50
30
20
10
0.1
1
10
0
100 1000 f(KHz)
0
1
10
100
1000
f(Hz)
L4985
Figure 19: Switching frequency vs. Cosc
D95IN190
fsw
(KHz)
160
Figure 20: Evaluation board efficiency of (Ref
fig. 29) with synchronous rectifier
D95IN191
eff
(%)
Vo=5.1V, DIS2=LOW
Cosc=560pF
96
1A
2A
120
3A
92
80
88
40
84
0
0
400
800
Cosc(pF)
Figure 21: Evaluation board efficiency (Ref. fig.
25) with synchronous rectifier
[V01 = 5V, V02 = 24V]
eff
(%)
D95IN193
(*) Io1=0.5A, Io2=0.2A
(**) Io1=3A, Io2=0.2A
(***) Io1=1A, Io2=0.2A
(****) Io1=2A, Io2=0.2A
95
4
8
12
16
20
V17(V)
Figure 22: Evaluation board efficiency (Ref. fig. 28)
with synchronous rectifier
eff
(%)
D95IN194
95
Io=1A
93
Io=2A
(****)
91
90
Io=3A
(***)
(**)
(*)
89
87
85
80
6
10
14
18
Figure 23: Evaluation board efficiency (Ref fig.28)
with D1 = SB540 and pin9 open.
eff
(%)
D95IN171
Vo = 3.3V
Cosc = 560pF
DIS2 = LOW
92
1A
90
4
22 Vin
8
12
16
20
Vin
Figure 24: PCB thermal characteristic
PDIS
(W)
D95IN202
3
2A
88
3A
2
86
84
1
82
80
4
8
12
16
20
V17(V)
0
25
50
75
100
125 Tpinc(°C)
9/23
L4985
APPLICATION INFORMATION
Figure 25: Dual converter evaluation board circuit (Fig.: 26-27)
L3
Vin = 8V to 20V
D2
VOUT2 = 24V/0.2A
C13
R1
DIS1
L1
DIS2
C3
LED
3
C14
1
8
17
11
R9
12
VOUT1 = 5.1V/3A
L2
4
L4985
2
C1
R8
MOS
9
5,6,15,16
18
20
14
10
7
(*)
19
13
R2
D1
C5
R3
C7
R6
C2
R11
R10
C8
C9
C10
R7
C12
C11
R4
D94IN166
C1 = 560µF / 25V NCC LXF
C2 = 10µF / 50V
C3 = 330nF film
C5 = 220µF / 10V SANYO OS CON
C7 = 2.2nF film
C8 = 560pF multilayer
C9 = C10 = 2.2µF / 10V
C11 = 3.9nF
C12 = 5.6nF
C13 = 330µF / 35V NCC LXF
C14 = 22nF
R1 = 3.3kΩ
R2 = 4.7Ω
R3 = 8.2kΩ
R4 = 2.7kΩ
R6 = 56kΩ
R7 = 39kΩ
R8 = 47kΩ
R9 = 2.7kΩ
R10 = 10kΩ
R11 = 10kΩ
L1 = 180µH axial
L2 = 50µH (Core Magnetics 58120, 27 turns,
0.8mm )
L3 = 50µH (Core Magnetics 58050, 27 turns,
0.6mm )
D2 = ST BYV 10 - 40
D1 = SB540
PIN 9 = OPEN
(*) OPTIONAL:
D1 = STBYV 10-40 AND
MOS = DY9410 SILICONIX
Table 1: Evaluation board test circuit results (using synchronous rectifier).
Symbol
η
Parameter
Efficiency
Value
Unit
Vin = 14V; DIS 2 = HIGH;
Iout1 = 1A; Iout2 = 0.2A;
Test Condition
92.0
%
Vin = 14V; DIS 2 = HIGH;
Iout1 = 3A; Iout2 = 0.2A;
91.8
%
∆Vout1
Line Regulation
Vin = 8 to 21V; DIS 2 = HIGH
Iout1 = 0.5A; Iout2 = 20mA;
4
mV
∆Vout1
Load Regulation
Vin = 8 to 21V; DIS 2 = HIGH
Iout1 = 0.5 to 3A ; Iout2 = 0.2A
10
mV
∆Vout2
Line Regulation
Vin = 8 to 21V; DIS 2 = HIGH
Iout1 = 0.5A; Iout2 = 20mA;
50
mV
∆Vout2
Load Regulation
Vin = 8 to 21V; DIS 2 = HIGH
Iout1 = 0.5 to 3A ; Iout2 = 0.2A
300
mV
10/23
L4985
Figure 26: PC Board (Component Side) and Components Layout of fig. 25 (scale 1:1)
Figure 27: PC Board (Back Side) and Components Layout of fig. 25 (scale 1:1)
11/23
L4985
Figure 28: L4985 single output: evaluation board circuit.
Vin = 4.5 to 20V
C3
R1
L1
LED
1
DIS1
C1
8
17
L2
VOUT = 3.3V/3A
4
3
L4985
MOS
9
2,5,6,15,16
C5
D1
20
18
14
7
10
13
R3
C6
19
R6
C2
C8
C9
R7
C12
C10
R4
C11
D94IN167
Figure 29: L4985 single output: evaluation board circuit (**).
Vin = 6V to 20V
C3
R1
L1
LED
1
DIS1
8
17
L2
VOUT = 5.1V/3A
4
3
C1
L4985
MOS
9
2,5,6,15,16
18
C5
D1
20
14
10
7
R3
19
13
R6
C2
C8
C9
R7
C12
C10
C11
R4
D94IN168
C1 = 470µF / 25V NCC LXF
C2 = 10µF / 50V
C3 = 330nF film
C5 = C6 = 220µF / 10V SANYO OS-CON
C8 = 560pF multilayer
C9 = C10 = 2.2µF / 10V
C11 = 4.7nF (3.9nF **)
C12 = 8.2nF (5.6nF **)
R1 = 3.3kΩ
R3 = 3.9kΩ (8.2kΩ **)
R4 = 2.4kΩ (27κΩ **)
R6 = 56kΩ
R7 = 33kΩ (39kΩ **)
L1 = 180µH axial
L2 = 45µH (Core Magnetics 58120, 24 turns,
0.9mm PCB copper thickness 70mm)
[L2 = 50µH (Core Magnetics - 27 turns, 0.8mm )
PCB copper thickness 70mm **]
D1 = SB540 (pin 9 open)
(*) OPTIONAL: D1 = ST BYV 10 - 40
MOS = DY9410 SILICONIX
Table 2: Step down converter using synchronous rectifier evaluation results.
Symbol
η
Parameter
Efficiency
Test Condition
Value
Unit
Vin = 5V; Iout = 1A ; Vout = 3.3V
94.0
%
Vin = 5V; Iout = 3A ; Vout = 3.3V
89.1
%
∆Vout
Line Regulation
Vin = 4.5 to 21V; Iout = 0.5A
2.0
mV
∆Vout
Load Regulation
Vin = 4.5 to 21V; Iout = 0.5 to 3A
5.0
mV
12/23
L4985
Figure 30: PC Board (Component Side) and Components Layout of Fig. 28 (scale 1:1)
Figure 31: PC Board (Back Side) and Components Layout of Fig. 28 (scale 1:1)
Figure 32: L4985 single output: Minimum external component count.
Vin
C3
L1
8
3
17
L2
VOUT
4
C1
2,5,6,15,16
L4985
D1
R3
C5
R1
19
14
18
7
10 13
R4
C4
C8
C7
R2
C2
C5
D94IN169
13/23
L4985
Figure 33 : Single chip converter generates 3.3V/3A for logic and 12V/100mA (flash eprom) from 5V bus
L3
Vin = 5V (DC bus)
D2
VOUT2 = 12V/100mA
C13
L1
R8
C3
C14
3
8
12
L2
VOUT1 = 3.3V/3A
4
L4985
2
C1
11
17
R9
R2
D1
5,6,15,16
14
18
10
7
C5
R3
19
13
C7
R6
C2
C8
R7
C12
C10
C11
R4
D95IN199
C1 = 560µF / 25V NCC LXF
C2 = 10µF / 50V
C3 = 330nF film
C5 = 220µF / 10V SANYO OS CON (2x220µF)
C7 = 2.2nF film
C8 = 560pF multilayer
C9 = C10 = 2.2µF / 10V
C11 = 4.7nF
C12 = 8.2nF
C13 = 330µF / 25V NCC LXF
C14 = 22nF
14/23
R1 = 3.3kΩ
R2 = 4.7Ω
R3 = 3.9kΩ
R4 = 2.4kΩ
R6 = 56kΩ
R7 = 33kΩ
R8 = 27kΩ
R9 = 2.7kΩ
R10 = 10kΩ
R11 = 10kΩ
L1 = 180µH axial
L2 = 20µH (Core Magnetics 55050, 19 turns,
0.8mm )
L3 = 15µH (Core Magnetics 58080, 16 turns,
0.6mm )
D2 = ST BYV 10 - 40
D1 = SB540
PIN 9 = OPEN
L4985
Figure 34 : Single chip converter generates 5V/2A for logic and 12V /100mA for flash eprom
VOUT2 = 12V/100mA
D2
Vin = 8V to 16V
C3
C13
R8
L1
C14
R9
L3
3
8
11
17
12
L2
4
VOUT1 = 5.1V/2A
L4985
2
R2
C1
14
18
C5
D1
5,6,15,16
10
7
13
R3
19
C7
R6
C2
C8
C10
R7
C12
R4
C11
D95IN200
C1 = 560µF / 25V NCC LXF
C2 = 10µF / 50V
C3 = 330nF film
C5 = 220µF / 10V SANYO OS CON (2x220µF)
C7 = 2.2nF film
C8 = 560pF multilayer
C9 = C10 = 2.2µF / 10V
C11 = 3.9nF
C12 = 5.6nF
C13 = 330µF / 25V NCC LXF
C14 = 22nF
R1 = 3.3kΩ
R2 = 4.7Ω
R3 = 8.2kΩ
R4 = 2.7kΩ
R6 = 56kΩ
R7 = 39kΩ
R8 = 27kΩ
R9 = 2.7kΩ
R10 = 10kΩ
R11 = 10kΩ
L1 = 180µH axial
L2 = 20µH (Core Magnetics 58120, 27 turns,
0.8mm )
L3 = 15µH (Core Magnetics 58050, 16 turns,
0.6mm )
D2 = ST BYV 10 - 40
D1 = SB540
PIN 9 = OPEN
15/23
L4985
Figure 35: Extremely compact one chip solution for inkjet printer.
L3
Vin = 5V (DC)
D2
VOUT2 = 24V/100mA
C13
L1
R8
C3
C14
3
8
11
17
12
L2
VOUT1 = 3.3V/1A
4
L4985
2
C1
R9
R2
D1
5,6,15,16
18
14
10
7
C5
R3
19
13
C7
R6
C2
R7
C12
C10
C8
R4
C11
D95IN201
R2
R3
R4
R6
R7
R8
R9
‘
C1 = 100µF / 16V NCC LXF
C2 = 10µF / 50V
C3 = 330nF film
C5 = 100µF / 16V (ESR = 0.045mΩ)
C7 = 2.2nF film
C8 = 560pF multilayer
C10 = 2.2µF / 10V
C11 = 3.9nF
C12 = 5.6nF
C13 = 220µF / 35V
C14 = 22nF
L1 = 180µH axial (RS = 2 to 5Ω)
L2 = 68µH (Core Magnetics 55050, 34 turns,
0.8mm )
L3 = 68µH (Core Magnetics 55050, 34 turns,
0.8mm )
= 4.7Ω
= 3.9kΩ
= 2.4kΩ
= 56kΩ
= 39kΩ
= 47kΩ
= 2.7kΩ
D1 = D2 = ST BYV 10 - 40
PIN 9 = OPEN
TYPICAL EFFICIENCY OF FIGURE 35
IOUT2 = 100mA
VIN
Unit
IOUT1 = 0.5A
IOUT1 = 1A
IOUT1 = 1.5A
5V
87.5
89
88.5
%
7.3V
85.5
88
85
%
Figure 36: Multioutputs idea in auxiliary converter only
VOUT3 = -24V/50mA
Vin = 8V to 12V
L1
C3
C1
D2
8
17
VOUT2 = 24V/100mA
11
C13
L4985
R8
12
C14
D95IN203
16/23
R9
L4985
Figure 37: Battery charger application circuit.
Vin = 14V to 20V
C3
L1
8
3
17
L2
VOUT = 12.5V
4
C1
2,5,6,15,16
Io max = 2A
L4985
D1
R3
C6
R1
19
14
18
7
10 13
R4
C4
C8
C7
C2
R2
C5
Io max =
R6
V+ =
R9
D2
C9
D3
1
4
8
C1 = 470µF / 25V NCC LXF
C2 = 10µF / 50V
C3 = 330nF /63V film
C4 = 3.9nF
C5 = 2.7nF
C6 = 220µF
C7 = 1µF
C8 = 560pF
C9 = 100nF
C10 = 1µF
+
-
3
R6
2.5 • 100
100 + R1O
~ 100mV
C10
R10
V+
V+
R7
2
TS27M2
R1 = 22kΩ
R2 = 2.4kΩ
R3 = R4 = 56kΩ
R6 = 55mΩ
R7 = R8 = 100Ω
R9 = 4.7kΩ
R10 = 2.4kΩ
D94IN170A
R8
L1 = 180µH axial
L2 = 50µH (Core Magnetics 58120, 27 turns,
0.8mm )
D1 = SB540
D2 = TL431
D3 = BYT1040
17/23
L4985
Figure 38: E/A Compensation Network
APPLICATION HINTS
Oscillator (pin 18)
An external capacitor, Cosc, connected between
pin 18 and SGND fixes the oscillator frequency
fsw. In the range from 25 kHz to 350 kHz, fsw is
given by:
fsw = 31 - 8 ⋅ Cosc + 32/Cosc,
[fsw]=kHz, [Cosc]=nF
A value of 85 kHz (Cosc = 560 pF) is suggested
as optimum trade-off between high efficiency and
output filter size reduction.
Comp (pin 13)
An E/A compensation networks providing two
pole-zero pairs is suggested for stabilizing the
control loop of the L4985. In fig. 38, an example
of such a kind of network is shown. In fig. 39 the
bode plot of its gain is drawn.
Figure 39: E/A Compensation Network Gain.
Power Management (pins 2 & 3)
Pin 3 (DIS1), controls the enabling/disabling of
the whole chip. A low level (below 0.9V) disables
it, reducing the current absorbed from the supply
to few A (sleep mode). A voltage above 3V en18/23
ables the chip operation.
Pin 2 (DIS2) works just like DIS1 but controls the
auxiliary converter only, leaving the main converter still operating.
Internal Boost (pins 7 & 8)
This low power converter is used to generate a
DC bus, delivering 10 V above the supply voltage,
needed for driving the internal NDMOS switches.
This solution does not put any limitation both to
maximum duty cycle and to minimum load current.
The internal boost uses, as external components,
a small chip or axial inductor (connected to the
VS) and a capacitor (connected to PWGND).
The inductance should be in the range 100 to 200
µH, with few ohms of series resistance to limit the
peak current.
The capacitor will be an electrolytic one (10 uF is
OK) without any particular requirement.
Gate Driver (pin 9)
This output can drive an external PowerMOS acting as a synchronous rectifier for achieving maximum efficiency at high load current.
The driver can deliver up to 30 nC per cycle with
a 10 V voltage, and that must be taken into account when selecting the external PowerMOS,
because of its gate charge.
A small Schottky diode in parallel to the external
PowerMOS is still used in order to avoid power
losses due to the turn-on of the PowerMOS inherent diode.
Reset Function (pins 1 & 20)
The RESET signal, delivered at pin 1 with an
open drain output (compatible to VS), indicates
with a low level either that the chip is disabled or
that an output voltage drop has occurred.
The high level appears, after a programmable delay, as the chip is enabled or the ouptut voltage
has recovered its correct value.
L4985
Figure 40: Auxiliary converter internal schematic.
Figure 41: Auxiliary converter: Principal waveforms
19/23
L4985
The delay (Trd) is programmed by an external capacitor connected to pin 20 and SGND according
to the approximate rate:
Trd = 250 ms/µF
Soft Start (pin 14)
Soft-start, essential to assure a correct and safe
start-up of converters, is performed by means of
an external capacitor, Css. The soft-start time is
related to Css by the approximate rate:
Tss = 30 Vout / Vin [ms/µF] .
Auxiliary Converter (pins 11 & 12)
The auxiliary section includes, as a power switch,
an NDMOS with grounded source and open
drain, thus allowing the implementation of either
boost or transformer coupled converters. That requires, besides the magnetics and the output
stage, only a resistor divider to fix the output voltage. No frequency compensation is needed.
BOARD LAYOUT CONSIDERATIONS.
To prevent degraded performances or, worse, instabilities and oscillations, a careful board layout
is mandatory. With this aim, the following points
should be considered.
1)Separate ground paths of signals and load
currents of the main converter. The two paths
should have their common point in the (-)
20/23
plate of the output capacitor.
2)Separate the ground path of the auxiliary converter from that of the main converter. The
former runs from the (-) plate of its output capacitor to PWGND. The (-) plates of the two
output capacitors should be connected.
3)Make separate supply paths for the IC (pin
17), the internal step-up and the auxiliary converter, all leading to the (+) plate of the input
capacitor.
4)The anode of the Schottky diode (the drain of
the synchronous rectifier, when used) should
be placed as close as possible to pin 4 in order to reduce stray inductance which causes
ringing spikes at MOS turn-off.
5)Place the input capacitor as close as possible
to the IC so to reduce the effect of the pulsed
current absorbed.
6)Make copper tracks carrying high currents
(either pulsed or DC) as large as possible, in
order not to impair efficiency and load regulation. Concerning this, it is important to use
copper layers as thick as possible. Some of
these tracks could be doubled on the other
side of the board.
7)Make copper tracks carrying small signals run
far from points with quickly swinging voltages.
8)Widen as much as possible the copper area
to which the four central ground pins are connected, in order to make easier heat dissipation. Also ground paths could be widened to
form ground planes.
L4985
POWERDIP 16+2+2 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.85
b
b1
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.40
0.033
0.50
0.38
0.020
0.50
D
0.055
0.015
0.020
24.80
0.976
E
8.80
0.346
e
2.54
0.100
e3
22.86
0.900
F
7.10
0.280
I
5.10
0.201
L
Z
3.30
0.130
1.27
0.050
21/23
L4985
SO-20 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
TYP.
2.65
0.1
MAX.
0.104
0.3
a2
0.004
0.012
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45 (typ.)
D
12.6
13.0
0.496
0.512
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.4
7.6
0.291
0.299
L
0.5
1.27
0.020
0.050
M
S
22/23
MIN.
0.75
0.030
8 (max.)
L4985
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1995 SGS-THOMSON Microelectronics - AllRights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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23/23