SANYO LC74760

Ordering number : EN4453A
CMOS IC
LC74760, 74760M
On-Screen Display IC
Overview
Package Dimensions
The LC74760 and LC74760M are on-screen display
CMOS ICs that superimpose text and low-level graphics
onto a TV screen (video signal) under microprocessor
control. The display characters have a 12 by 18 dot
structure, and 128 characters are provided. The display
area consists of 12 lines of 24 characters each.
unit: mm
3061-DIP30S
[LC74760]
Features
• Display structure: 12 lines by 24 characters (up to 288
characters)
• Number of displayed characters: Up to 288 characters
• Character configuration: 12 (W) by 18 (H) dot structure
• Character sizes: Three sizes (normal, double, and triple
sizes)
• Display starting positions: 64 horizontal and 64 vertical
locations
• Reverse video function: Characters can be inverted on a
per character basis.
• Flashing types: Two types with periods of 0.5 and 1.0
second on a per character basis (duty fixed at 50%)
• Background color: One of eight colors (when internal
synchronization used)
• External control input: Serial data input in 8-bit units
• Built-in horizontal/vertical sync separation circuit, AFC
circuit, and synchronization detector
• Video output: Composite video signal output in NTSC,
PAL, PAL-M, PAL-N, PAL60, NTSC4.43, or SECAM
format
SANYO:DIP30S
unit: mm
3073A-MFP30S
[LC74760M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13096HA (OT)/73093JN (OT) No. 4453-1/14
LC74760, 74760M
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Maximum supply voltage
VDD max
VDD1, VDD2 pins
VSS – 0.3 to VSS + 7.0
V
Maximum input voltage
VIN max
All input pins
VSS – 0.3 to VDD + 0.3
V
HSYNCOUT, VSYNCOUT,
SYNCDET pins
VSS – 0.3 to VDD + 0.3
Maximum output voltage
Allowable power dissipation
VOUT max
Condition
Rating
Pd max
Unit
V
300
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = –30 to +70°C
Parameter
Supply voltage
Input high level voltage
Input low level voltage
Input voltage
Composite video signal input voltage
Symbol
Rating
min
typ
Unit
max
VDD1
VDD1 pin
4.5
5.0
5.5
V
VDD2
VDD2 pin
4.5
5.0
1.27 VDD1
V
VIH1
RST, CS, SIN, SCLK pins
0.8 VDD1
VDD1 + 0.3
V
VIH2
SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins
0.7 VDD1
VDD1 + 0.3
V
VIL1
RST, CS, SIN, SCLK
VSS – 0.3
0.2 VDD1
V
VIL2
SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins
VSS – 0.3
0.3 VDD1
V
VSS – 0.3
VIN
FC, AMPIN pins
VIN1
CVIN pins
VIN2
CVCR pins
2 VPP
VIN3
SYNCIN pins
2 VPP
FOSC1
Oscillator frequency
Condition
FOSC2
VDD1 + 0.3
2 VPP
V
V
V
2.5 VPP
V
XtalIN1, XtalOUT1 pins; 4fsc: NTSC
14.318
MHz
XtalIN2, XtalOUT2 pins; 4fsc: PAL
17.734
MHz
XtalIN2, XtalOUT2 pins; 4fsc: PAL-M
14.302
MHz
XtalIN2, XtalOUT2 pins; 4fsc: PAL-N
14.328
MHz
Electrical Characteristics at Ta = –30 to +70°C, with VDD1 = VDD2 = 5 V unless otherwise specified
Parameter
Symbol
Condition
Rating
min
typ
max
Unit
Output off leakage current
Ileak1
CVOUT pin
10
µA
Input off leakage current
Ileak2
CVIN, CVCR pins
10
µA
Output high level voltage
VOH
HSYNCOUT, VSYNCOUT,
SYNCDET, SECAM, 525/625,
NTSC/PAL, 3.58/4.43, AMPOUT,
PDOUT pins; VDD1 = 4.5 V, IOH = –1.0 mA
Output low level voltage
VOL
HSYNCOUT, VSYNCOUT,
SYNCDET, SECAM, 525/625,
NTSC/PAL, 3.58/4.43, AMPOUT,
PDOUT pins; VDD1 = 4.5 V, IOL = 1.0 mA
IIH
RST, CS, SIN, SCLK, SECAM, 525/625,
NTSC/PAL, 3.58/4.43 pins; VIN = VDD1
IIL
SECAM, 525/625, NTSC/PAL,
3.58/4.43 pin; VIN = VSS1
Input current
Oscillator frequency
Operating current dissipation
3.5
V
1.0
V
1
µA
–1
µA
FOSC3
VCOIN, VCOOUT pins; FC = 1/2 VDD1
IDD1
VDD1 pin; All outputs open, Xtal: 4fsc
14.12
15
MHz
mA
IDD2
VDD2 pin; VDD2 = 5.0 V
20
mA
Timing Characteristics at Ta = –30 to +70°C, VDD = 5 ±0.5 V
Rating
Parameter
Minimum input pulse width
Data setup time
Data hold time
One word write time
Symbol
Condition
typ
max
Unit
200
ns
1
µs
CS pin
200
ns
tSU(SIN)
SIN pin
200
ns
th(CS)
CS pin
2
µs
th(SIN)
SIN pin
200
ns
tword
Write time for 8 bits of data
4.2
µs
1
µs
tW(SCLK)
SCLK pin
min
tW(CS)
CS pin (during periods when CS is high)
tSU(CS)
twt
RAM data write time
No. 4453-2/14
LC74760, 74760M
Pin Functions
Pin No.
Symbol
1
VSS
2
XtalIN1
3
XtalOUT1
4
HSYNCOUT
5
XtalIN2
6
XtalOUT2
7
VSYNCOUT
8
CS
Function
Description
Ground
Ground connection
Crystal oscillator connection
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. (For an NTSC crystal oscillator 4fsc = 14.318 MHz.)
Horizontal synchronization
output
Outputs the horizontal synchronization signal (AFC). The polarity can be selected with a
metal switch.
Crystal oscillator connection
Connection for the crystal and capacitor used to form the crystal oscillator that generates
the internal synchronization signal. (For a PAL crystal oscillator 4fsc = 17.734 MHz.)
Vertical synchronization output
Outputs the vertical synchronization signal. The polarity can be selected with a metal switch.
Enable input
Enables/disables serial data input. Serial data is enabled when this pin is low. Pull-up
resistor built in (hysteresis input).
9
SIN
Data input
Serial data input. Pull-up resistor built in (hysteresis input).
10
SCLK
Clock input
Clock input for serial data input. Pull-up resistor built in (hysteresis input).
11
SECAM
SECAM mode switch input
Switches between SECAM and other modes.
Low = other modes, high = SECAM mode
12
525/625
525/625 switch input
Switches between 525 scan lines and 625 scan lines.
Low = 525 lines, high = 625 lines
13
NTSC/PAL
NTSC/PAL switch input
Switches the color mode between NTSC and PAL.
Low = NTSC, high = PAL
14
3.58/4.43
3.58/4.43 switch input
Switch FSC between 3.58 MHz and 4.43 MHz.
Low = 3.58, high = 4.43
15
RST
Reset input
System reset input pin, low is active (reset).
Pull-up resistor built in (hysteresis input).
16
CVOUT
Video signal output
Composite video output
17
VDD2
Power supply connection
Power supply connection for composite video signal level generation
18
CVIN
Video signal input
Composite video input
19
CVCR
Video signal input
SECAM chroma signal input
20
SYNCIN
Sync separator circuit input
Built-in sync separator circuit video signal input
21
SEPC
Sync separator circuit
Built-in sync separator circuit (AMP out)
22
VSS
Ground
Ground connection
23
PDOUT
Control voltage output
AFC control voltage output
24
AMPIN
AFC filter connection
Filter connection
25
AMPOUT
Control voltage input
AFC control voltage input
LC oscillator connection
VCO LC oscillator circuit coil and capacitor connection
External synchronization signal
detection output
Outputs the exclusive NOR of the horizontal synchronization signal (AFC) and CSYNC (sync
separator).
Power supply connection
Power supply connection (+5 V: digital system power supply)
26
FC
27
VCOIN
28
VCOOUT
29
SYNCDET
30
VDD1
No. 4453-3/14
LC74760, 74760M
Pin Assignment
Serial Data Input Timing
No. 4453-4/14
LC74760, 74760M
System Block Diagram
No. 4453-5/14
LC74760, 74760M
Display Control Commands
Display control commands are input in an 8-bit serial format. Commands consist of a command identification code in the
first byte and data in the second and following bytes. The following commands are supported.
1
2
3
4
5
6
7
8
COMMAND0:
COMMAND1:
COMMAND2:
COMMAND3:
COMMAND4:
COMMAND5:
COMMAND6:
COMMAND7:
Display memory (VRAM) write address setting command
Display character data write command
Vertical display start position and character size (lines 1 and 2) setting command
Horizontal display start position and character size (lines 9 and 11) setting command
Display control setting command 1
Display control setting command 2
Display control setting command 3
Display control setting command 4
Display Control Command Table
First byte
Command
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
COMMAND0
Write address
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
COMMAND1
Character write
1
0
0
1
0
0
at2
at1
0
c6
c5
c4
c3
c2
c1
c0
COMMAND2
Vertical display start position
1
0
1
0
SZ
21
SZ
20
SZ
11
SZ
10
0
0
VP
5
VP
4
VP
3
VP
2
VP
1
VP
0
COMMAND3
Horizontal display start position
1
0
1
1
SZ
B1
SZ
B0
SZ
91
SZ
90
0
0
HP
5
HP
4
HP
3
HP
2
HP
1
HP
0
COMMAND4
Display control 1
1
1
0
0
RST
RAM
OSC
RND
0
I/N
BLK
1
BLK
0
BK
1
ATS
0
DSP
COMMAND5
Display control 2
1
1
0
1
PH
2
PH
1
PH
0
I/E
0
TST
CHAL
BLK
RSL
1
RSL
0
0
0
COMMAND6
Display control 3
1
1
1
0
0
0
0
0
IOS
BCL
1
BCL
0
CB
COMMAND7
Display control 4
1
1
1
1
0
0
LIN
5
LIN
4
LIN
3
LIN
2
LIN
1
LIN
0
MOD MOD MOD MOD
3
2
1
0
0
0
0
LINS
Once the command identification code in the first bite is written, it is stored internally until the first byte of the following
command is written. However, when the display character data write command (COMMAND1) is written, the system
becomes locked in display character data write mode, and the first byte cannot be overwritten.
When the CS pin is set high the command state is set to COMMAND0, i.e., display memory write address setting mode.
1
COMMAND0: Display Memory Write Address Setting Mode
First data byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
0
4
—
3
2
1
0
V3
V2
V1
V0
Function
Note
The command 0 identification code:
sets the display memory write address.
0
0
1
0
1
0
Display memory line address (from 0 to B (hexadecimal))
1
0
1
No. 4453-6/14
LC74760, 74760M
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
—
0
4
H4
3
H3
2
H2
1
H1
0
H0
Function
Note
Second byte identification code
0
1
0
1
0
1
Display memory character address (from 0 to 17 (hexadecimal))
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
2
COMMAND1: Display Character Data Write Command
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
0
4
—
1
3
—
0
2
—
0
1
at2
0
at1
Function
The command 1 identification code:
sets the display memory write address.
0
Turns character attribute 2 off.
1
Turns character attribute 2 on.
0
Turns character attribute 1 off.
1
Turns character attribute 1 on.
Note
When this command is entered, the
chip locks in display character write
mode until the CS pin is set high.
Specifies highlight or flashing.
Specifies reverse video.
Second byte
Register content
DA0 to DA7
Register name
7
—
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
State
Function
Note
0
0
1
0
1
0
1
Character code (from 00 to 7F (hexadecimal))
0
1
0
1
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 4453-7/14
LC74760, 74760M
3
COMMAND2: Vertical Display Position Setting Command
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
1
4
—
0
3
SZ21
2
SZ20
1
SZ11
0
SZ10
The command 2 identification code:
sets the vertical display position.
0
1
Note
Function
SZ20
0
SZ21
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
0
1
SZ10
0
SZ11
Character size for the second line
1
0
0
Normal size
Double size
1
1
Triple size
Normal size
Character size for the first line
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
VP5
(MSB)
0
4
VP4
3
VP3
2
VP2
1
VP1
0
VP0
(LSB)
1
Note
Function
Second byte identification code
The vertical display start position is given by
5
0
VS = H × ( Σ
1
where H is the horizontal synchronization pulse period.
2nVPn)
n=0
0
The six bits VP0 to VP5 specify the
vertical display start position.
The weight of the lsb is 1 × H.
1
0
1
0
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
4
COMMAND3: Horizontal Display Position Setting Command
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
0
5
—
1
4
—
3
SZB1
2
SZB0
1
SZ91
0
SZ90
Note
Function
The command 3 identification code:
sets the horizontal display position.
1
0
1
SZB0
SZB1
0
1
0
1
1
Normal size
Double size
1
Triple size
Normal size
0
1
0
0
SZ90
SZ91
0
The character size for the eleventh line.
1
0
Normal size
Double size
1
Triple size
Normal size
The character size for the ninth line.
No. 4453-8/14
LC74760, 74760M
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
HP5
(MSB)
0
4
HP4
3
HP3
2
HP2
1
HP1
0
HP0
(LSB)
Function
Note
Second byte identification code
1
0
1
0
1
The horizontal display start position is given by
5
HS = Tc × ( Σ
The six bits HP0 to HP5 specify the
vertical display start position.
The weight of the lsb is 1 x Tc.
2nHPn)
n=0
0
1
0
where Tc is the period of the OSCIN and OSCOUT oscillator in
operating mode.
1
0
1
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
5
COMMAND4: Display Control Setting Command 1
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
0
4
—
0
3
RSTSYS
2
RAMERS
1
OSCSTP
Function
The command 4 identification code:
sets display control parameters.
0
Resets all registers. (Clears all registers to 0.)
This reset occurs when the CS pin goes
low, and the reset state cleared when
the CS pin goes high.
1
Erases display RAM. (Sets display RAM to 7F (hexadecimal).)
The RAM erase function requires at
least 500 µs.
It is executed on DSPOFF.
0
Continues crystal oscillator operation.
1
Stops the crystal oscillator.
0
Turns off rounding.
1
Turns on rounding.
1
0
0
RNDSEL
Note
Only valid with character display off if
external synchronization is used.
Only valid for double and triple size
characters.
No. 4453-9/14
LC74760, 74760M
Second byte
Register content
DA0 to DA7
Register name
7
—
6
INT/NON
5
BLK1
4
BLK0
3
BK1
2
ATS
1
—
0
DSPON
State
0
Second byte identification code
0
Interlaced
1
Non-interlaced
0
1
Note
Function
Switches between interlaced and
non-interlaced display.
BLK0
0
BLK1
1
0
0
Blanking off
Character size blanking
1
1
Frame size blanking
Total area blanking
0
Flashing period about 0.5 s
1
Flashing period about 1 s
0
Highlight function
1
Flashing function
Changes the blanking size.
Sets the flashing period.
Selects at2.
0
0
Character display off
1
Character display on
Turns character output on and off.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
6 COMMAND5: Display Control Setting Command 2
First byte
Register content
State
7
—
1
6
—
1
5
—
0
4
—
1
3
PH2
The command 5 identification code:
sets display control parameters.
0
PHASE 1
PHASE 0
NTSC
PAL
0
0
0
π/2
±π/2
1
0
1
PH0
1
0
INT/EXT
0
0
1
In phase
In phase
0
1
0
3 π/2
π/2
0
1
1
π
±π
1
0
0
3 π/4
±3 π/4
1
0
1
π/4
±π/4
1
1
0
7 π/4
±
0
PH1
Background color
(phase)
PHASE 2
1
2
Note
Function
1
1
1
5 π/4
3 π/4
0
External synchronization mode
1
Internal synchronization mode
±
Register name
±
DA0 to DA7
Sets the phase of the background color
for color burst.sz
π/4
Switches between internal and external
synchronization.
No. 4453-10/14
LC74760, 74760M
Second byte
Register content
DA0 to DA7
Register name
7
—
6
TST
5
CHAL
4
3
State
0
Second byte identification code
0
Normal operation
1
Test mode
0
Sets the character intensity level to about 95 IRE (bright white).
1
Sets the character intensity level to about 75 IRE (white with a
touch of grey).
0
Sets the blanking intensity level to about 5 IRE (a deep black
as a frame level).
1
Sets the blanking intensity level to about 15 IRE (a dark grey
as a frame level).
BKL
RSL1
Note
Function
Test mode should not be used. This bit
should always be zero.
0
RSL1
RSL0
1
0
0
About 15 IRE
About 60 IRE
0
1
About 30 IRE
About 60 IRE
1
0
About 45 IRE
About 60 IRE
1
1
About 60 IRE
About 69 IRE
0
2
RSL0
1
—
0
0
—
0
1
Intensity level
Switches the character intensity level.
Switches the blanking intensity level.
Amplitude
Switches the background intensity level.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
7
COMMAND6: Display Control Setting Command 3
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
1
4
—
3
MOD3
2
MOD2
1
MOD1
0
MOD0
Function
Note
The command 6 identification code:
sets display control parameters.
0
0
Sets Fsc to 3.58 MHz.
1
Sets Fsc to 4.43 MHz.
0
Sets the color mode to NTSC.
1
Sets the color mode to PAL.
0
Sets the number of scan lines to 525 lines.
1
Sets the number of scan lines to 625 lines.
0
Sets the mode to a mode other than SECAM.
1
Sets the mode to SECAM mode.
The logical or of this bit and the Fsc
switching input pin (pin 14) is used.
The logical or of this bit and the color
mode switching input pin (pin 13) is
used.
The logical or of this bit and the scan
line count switching input pin (pin 12) is
used.
The logical or of this bit and the mode
switching input pin (pin 11) is used.
No. 4453-11/14
LC74760, 74760M
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
—
0
4
—
3
IOS
2
BCOL1
BCOL0
0
CBOFF
Second byte identification code
0
0
Sets the mode setting pin to be an input pin.
1
Sets the mode setting pin to be an output pin.
0
BCOL1
BCOL0
1
0
0
Background color displayed
0
1
No background color (about 15 IRE)
1
0
No background color (about 25 IRE)
1
1
Illegal value
0
1
Note
Function
1
Switches the input/output direction of
the mode setting pins. (11 pin to 14 pin)
Background color
0
Outputs a color burst signal.
1
Stops the output of color burst signals.
Determines whether a background color
is displayed. (Only valid in internal
synchronization mode.)
Only valid when either BCOL0 is 1 or
BCOL1 is 1.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
8
COMMAND7: Display Control Setting Command 4
First byte
Register content
DA0 to DA7
Register name
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
LINS
Function
Note
The command 7 identification code:
sets display control parameters.
0
0
Selects the lower 6 bits (bits 0 to 5)
1
Selects the upper 6 bits (bits 6 to B)
Selects the upper or lower six bits when
halftone output line mode is specified.
Second byte
Register content
DA0 to DA7
Register name
State
7
—
0
6
—
0
5
LIN5
4
LIN4
3
LIN3
2
LIN2
1
LIN1
0
LIN0
Function
Note
Second byte identification code
0
Turns off (low) sixth line halftone output.
1
Turns on (high) sixth line halftone output.
0
Turns off (low) fifth line halftone output.
1
Turns on (high) fifth line halftone output.
0
Turns off (low) fourth line halftone output.
1
Turns on (high) fourth line halftone output.
0
Turns off (low) third line halftone output.
1
Turns on (high) third line halftone output.
0
Turns off (low) second line halftone output.
1
Turns on (high) second line halftone output.
0
Turns off (low) first line halftone output.
1
Turns on (high) first line halftone output.
Used for the line 12 setting when LINS
is high.
Used for the line 11 setting when LINS
is high.
Used for the line 10 setting when LINS
is high.
Used for the line 9 setting when LINS is
high.
Used for the line 8 setting when LINS is
high.
Used for the line 7 setting when LINS is
high.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 4453-12/14
LC74760, 74760M
Display Configuration
The display consists of 12 rows of 24 characters each. Up to 288 characters can be displayed unless enlarged characters
are displayed. Display memory addresses are expressed as a row address in the range 0 to B (hexadecimal) and a column
address in the range 0 to 17 (hexadecimal).
Display Configuration and Display Memory Addresses
24 characters by 12 rows
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of January, 1996. Specifications and information herein are subject to
change without notice.
No. 4453-13/14
2.460
2.244
1.971
1.873
Background high level 2
Background high level 1
Burst high level
Frame level 2
2.702
Character level 2
Output voltage (VDC)
2.914
Output level
Character level 1
1.428
1.263
1.000
Burst low level
Sync level
1.597
Background low level 1
1.713
Output voltage (VDC)
Pedestal level
Output level
Frame level 1
LC74760, 74760M
Composite Video Signal Output Levels (internally generated levels)
PS No. 4453-14/14