Ordering number : ENN6144A CMOS IC LC75817NE, 75817NW 1/8 to 1/10 Duty Dot Matrix LCD Display Controllers/Drivers with Key Input Function Overview The LC75817NE and LC75817NW are 1/8 to 1/10 duty dot matrix LCD display controllers/drivers that support the display of characters, numbers, and symbols. In addition to generating dot matrix LCD drive signals based on data transferred serially from a microcontroller, the LC75817NE and LC75817NW also provide on-chip character display ROM and RAM to allow display systems to be implemented easily. These products also provide up to 4 general-purpose output ports and incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. • • • • • • • • Sleep mode can be used to reduce current drain. Built-in display contrast adjustment circuit Up to 4 general-purpose output ports are included. Serial data I/O supports CCB format communication with the system controller. Independent LCD driver block power supply VLCD A voltage detection type reset circuit is provided to initialize the IC and prevent incorrect display. The INH pin is provided. This pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. RC oscillator circuit Features • Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) • Controls and drives a 5 × 7, 5 × 8, or 5 × 9 dot matrix LCD. • Supports accessory display segment drive (up to 60 segments) • Display technique: 1/8 duty 1/4 bias drive (5 × 7 dots) 1/9 duty 1/4 bias drive (5 × 8 dots) 1/10 duty 1/4 bias drive (5 × 9 dots) • Display digits: 12 digits × 1 line (5 × 7 dots, 5 × 8 dots) 11 digits × 1 line (5 × 9 dots) • Display control memory CGROM: 240 characters (5 × 7, 5 × 8, or 5 × 9 dots) CGRAM: 16 characters (5 × 7, 5 × 8, or 5 × 9 dots) ADRAM: 12 × 5 bits DCRAM: 48 × 8 bits • Instruction function Display on/off control Display shift function • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 21202TN (OT) / 51099RM (OT) No. 6144-1/43 LC75817NE, 75817NW Package Dimensions unit: mm unit: mm 3151-QFP100E 3181B-SQFP100 0.825 [LC75817NE] 0.65 0.575 23.2 20.0 0.3 [LC75817NW] 16.0 14.0 1.6 0.575 80 81 0.5 1.0 0.15 1.0 75 51 50 76 0.5 16.0 14.0 31 21.6 0.1 100 1.0 30 0.8 1 1 0.2 25 2.7 0.8 SANYO: QFP100E 0.5 1.6max 26 100 3.0max 1.6 0.825 15.6 17.2 14.0 0.65 1.0 50 0.145 51 1.4 0.1 0.5 SANYO: SQFP100 No. 6144-2/43 LC75817NE, 75817NW KI3 KI2 KI1 KS6 KS5 KS4 KS3 KS2 KS1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 S60/COM10 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 Pin Assignments (Top View) 80 51 81 50 KI4 KI5 P1 P2 P3 P4 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VSS TEST OSCO OSCI INH DO CE S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 LC75817NE (QFP100E) 100 31 30 KS6 KS5 KS4 KS3 KS2 KS1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 S60/COM10 S59 S58 S57 S56 S55 S54 S53 S52 S51 CL DI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 1 75 51 76 50 KI1 KI2 KI3 KI4 KI5 P1 P2 P3 P4 VDD VLCD VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VSS TEST OSCO OSCI INH DO CE CL DI S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 LC75817NW (SQFP100) 100 26 25 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 1 No. 6144-3/43 LC75817NE, 75817NW Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings Unit VDD max VDD –0.3 to +7.0 VLCD max VLCD –0.3 to +11.0 Input voltage Output voltage Output current Allowable power dissipation VIN1 CE, CL, DI, INH VIN2 OSCI, KI1 to KI5, TEST VIN3 VLCD1, VLCD2, VLCD3, VLCD4 VOUT1 DO VOUT2 OSCO, KS1 to KS6, P1 to P4 VOUT3 VLCD0, S1 to S60, COM1 to COM10 –0.3 to +7.0 –0.3 to VDD + 0.3 V –0.3 to VLCD + 0.3 –0.3 to +7.0 –0.3 to VDD + 0.3 V –0.3 to VLCD + 0.3 IOUT1 S1 to S60 IOUT2 COM1 to COM10 3 IOUT3 KS1 to KS6 1 IOUT4 P1 to P4 5 Pd max V 300 Ta = 85°C 200 µA mA mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V Parameter Symbol VDD Supply voltage VLCD Output voltage Input voltage Input high level voltage Input low level voltage Conditions Ratings min typ max VDD 4.5 6.0 VLCD: When the display contrast adjustment circuit is used. 7.0 10.0 VLCD: When the display contrast adjustment circuit is not used. 4.5 10.0 VLCD0 VLCD0 VLCD1 VLCD1 VLCD4+4.5 3/4 (VLCD0–VLCD4) VLCD0 VLCD VLCD2 VLCD2 2/4 (VLCD0–VLCD4) VLCD0 VLCD3 VLCD3 1/4 (VLCD0–VLCD4) VLCD0 VLCD4 VLCD4 0 Unit V V V 1.5 VIH1 CE, CL, DI, INH 0.8 VDD 6.0 VIH2 OSCI 0.7 VDD VDD VIH3 KI1 to KI5 0.6 VDD VDD VIL1 CE, CL, DI, INH, KI1 to KI5 0 0.2 VDD VIL2 OSCI 0 0.3 VDD Recommended external resistance ROSC OSCI, OSCO 33 Recommended external capacitance COSC OSCI, OSCO 220 Guaranteed oscillation range fOSC OSC 150 300 V V kΩ pF 600 kHz Data setup time tds CL, DI: Figure 2 160 ns Data hold time tdh CL, DI: Figure 2 160 ns CE wait time tcp CE, CL: Figure 2 160 ns CE setup time tcs CE, CL: Figure 2 160 ns CE hold time tch CE, CL: Figure 2 160 ns High level clock pulse width tøH CL: Figure 2 160 ns Low level clock pulse width tøL CL: Figure 2 160 ns DO output delay time tdc DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2 1.5 µs DO rise time tdr DO, RPU = 4.7kΩ, CL = 10pF*1: Figure 2 1.5 µs Note: *1. Since DO is an open-drain output, these times depend on the values of the pull-up resistor RPU and the load capacitance CL. No. 6144-4/43 LC75817NE, 75817NW Electrical Characteristics for the Allowable Operating Ranges Parameter Hysteresis Power-down detection voltage Input high level current Symbol VH Conditions Input low level current IIL CE, CL, DI, INH, OSCI: VI = 0 V Input floating voltage VIF KI1 to KI5 Pull-down resistance RPD KI1 to KI5: VDD = 5.0 V Output low level voltage Output middle level voltage*2 Oscillator frequency Unit max 0.1 VDD 2.5 CE, CL, DI, INH, OSCI: VI = 6.0 V Output high level voltage typ CE, CL, DI, INH, KI1 to KI5 VDET IIH Output off leakage current Ratings min 3.0 V 3.5 V 5.0 µA –5.0 µA 0.05 VDD 50 IOFFH DO: VO = 6.0 V VOH1 S1 to S60: IO = –20 µA VLCD0 – 0.6 VLCD0 – 0.6 100 VOH2 COM1 to COM10: IO = –100 µA VOH3 KS1 to KS6: IO = –500 µA VDD – 1.0 VDD – 0.5 VOH4 P1 to P4: IO = –1 mA VDD – 1.0 VOH5 OSCO: IO = –500 µA VDD – 1.0 VOL1 S1 to S60: IO = 20 µA VOL2 COM1 to COM10: IO = 100 µA VOL3 KS1 to KS6: IO = 25 µA VOL4 P1 to P4: IO = 1 mA VOL5 OSCO: IO = 500 µA VOL6 DO: IO = 1 mA kΩ 6.0 µA VDD – 0.2 V VLCD4 + 0.6 VLCD4 + 0.6 0.2 0.5 1.5 1.0 V 1.0 0.1 0.5 VMID1 S1 to S60: IO = ±20 µA 2/4 (VLCD0 – VLCD4) – 0.6 2/4 (VLCD0 – VLCD4) + 0.6 VMID2 COM1 to COM10: IO = ±100 µA 3/4 (VLCD0 – VLCD4) – 0.6 3/4 (VLCD0 – VLCD4) + 0.6 VMID3 COM1 to COM10: IO = ±100 µA 1/4 (VLCD0 – VLCD4) – 0.6 1/4 (VLCD0 – VLCD4) + 0.6 fOSC OSCI, OSCO: ROSC = 33 kΩ, COSC = 220 pF IDD1 VDD: sleep mode 210 300 390 V kHz 100 IDD2 VDD: VDD = 6.0 V, output open, fOSC = 300 kHz ILCD1 VLCD: sleep mode ILCD2 VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz When the display contrast adjustment circuit is used. ILCD3 VLCD: VLCD = 10.0 V, output open, fOSC = 300 kHz When the display contrast adjustment circuit is not used. Current drain V 250 500 1000 450 900 200 400 5 µA Note: *2. Excluding the bias voltage generation divider resistor built into the VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4. (See Figure 1.) VLCD CONTRAST ADJUSTER VLCD0 VLCD1 VLCD2 To the common and segment drivers VLCD3 VLCD4 Excluding these resistors Figure 1 No. 6144-5/43 LC75817NE, 75817NW • When CL is stopped at the low level VIH1 CE VIL1 tøH CL tøL VIH1 50% VIL1 tcp DI tcs tch VIH1 VIL1 tds tdh tdc tdr D0 DO D1 • When CL is stopped at the high level VIH1 CE VIL1 tøH tøL VIH1 50% VIL1 CL tcp tcs tch VIH1 VIL1 DI tds tdh D0 DO D1 tdr tdc GENERAL PORT COMMON DRIVER S1 S58 S60/COM10 COM9 COM1 P4 P1 Block Diagram S59 Figure 2 SEGMENT DRIVER LATCH INSTRUCTION DECODER ADRAM 60 bits INSTRUCTION REGISTER ADDRESS COUNTER VLCD CONTRAST ADJUSTER VLCD0 CGRAM 5 × 9 × 16 bits CGROM 5 × 9 × 240 bits DCRAM 48 × 8 bits VLCD1 ADDRESS REGISTER VLCD2 VLCD3 VLCD4 SHIFT REGISTER KEY BUFFER CCB INTERFACE VDD VDET TIMING GENERATOR VSS KS6 KS5 KS4 KS3 KS2 KS1 KI5 KI4 KI3 KI2 KI1 CE CL DI DO KEY SCAN INH OSCO CLOCK GENERATOR OSCI TEST No. 6144-6/43 LC75817NE, 75817NW Pin Functions Pin No. Pin Active I/O Segment driver outputs. The S60/COM10 pin can be used as common driver output under the “set display technique” instruction. — O OPEN 69 to 61 Common driver outputs. — O OPEN — O OPEN H I GND LC75817NE LC75817NW S1 to S59 3 to 61 1 to 59 S60/COM10 62 60 COM1 to COM9 71 to 63 Function Handling when unused KS1 to KS6 72 to 77 70 to 75 Key scan outputs. Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. KI1 to KI5 78 to 82 76 to 80 Key scan inputs. These pins have built-in pull-down resistors. P1 to P4 83 to 86 81 to 84 General-purpose output ports — O OPEN OSCI 97 95 I GND OSCO 96 94 Oscillator connections. An oscillator circuit is formed by connecting an external resistor and capacitor at these pins. — — O OPEN CE 100 98 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE : Chip enable CL : Synchronization clock DI : Transfer data DO : Output data H I CL 1 99 DI 2 100 DO 99 97 I — I GND — O OPEN L I VDD INH 98 96 Input that turns the display off, disables key scanning, and forces the general-purpose output ports low. • When INH is low (VSS): • Display off S1 to S59 = “L” (VLCD4). S60/COM10 = “L” (VLCD4). COM1 to COM9 = “L” (VLCD4). • General-purpose output ports P1 to P4 = low (VSS) • Key scanning disabled: KS1 to KS6 = low (VSS) • All the key data is reset to low. • When INH is high (VDD): • Display on • The state of the general-purpose output ports can be set by executing a "Set general-purpose output port state" instruction. • Key scanning is enabled. However, serial data can be transferred when the INH pin is low. TEST 95 93 This pin must be connected to ground. — I — — O OPEN VLCD0 89 87 LCD drive 4/4 bias voltage (high level) supply pin. The level on this pin can be changed by the display contrast adjustment circuit. However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V. Also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. VLCD1 90 88 LCD drive 3/4 bias voltage (middle level) supply pin. This pin can be used to supply the 3/4 (VLCD0 – VLCD4) voltage level externally. — I OPEN VLCD2 91 89 LCD drive 2/4 bias voltage (middle level) supply pin. This pin can be used to supply the 2/4 (VLCD0 - VLCD4) voltage level externally. — I OPEN VLCD3 92 90 LCD drive 1/4 bias voltage (middle level) supply pin. This pin can be used to supply the 1/4 (VLCD0 – VLCD4) voltage level externally. — I OPEN — I GND VLCD4 93 91 LCD drive 0/4 bias voltage (low level) supply pin. Fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. However, (VLCD0 – VLCD4) must be greater than or equal to 4.5 V, and VLCD4 must be in the range 0 V to 1.5 V, inclusive. VDD 87 85 Logic block power supply connection. Provide a voltage of between 4.5 and 6.0 V. — — — VLCD 88 86 LCD driver block power supply connection. Provide a voltage of between 7.0 and 10.0 V when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 V when the circuit is not used. — — — VSS 94 92 Power supply connection. Connect to ground. — — — No. 6144-7/43 LC75817NE, 75817NW Block Functions • AC (address counter) AC is a counter that provides the addresses used for DCRAM and ADRAM. The address is automatically modified internally, and the LCD display state is retained. • DCRAM (data control RAM) DCRAM is RAM that is used to store display data expressed as 8-bit character codes. (These character codes are converted to 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns using CGROM or CGRAM.) DCRAM has a capacity of 48 × 8 bits, and can hold 48 characters. The table below lists the correspondence between the 6-bit DCRAM address loaded into AC and the display position on the LCD panel. • When the DCRAM address loaded into AC is 00H. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 DCRAM address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0A 0B However, when the display shift is performed by specifying MDATA, the DCRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 DCRAM address (hexadecimal) 01 02 03 04 05 06 07 08 09 0A 0B 0C Display digit DCRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 10 11 12 2F 00 01 02 03 04 05 06 07 08 09 0A (Shift left) (Shift right) Note: *3. The DCRAM address is expressed in hexadecimal. Least significant bit ↓ LSB DCRAM address DA0 Most significant bit ↓ MSB DA1 DA2 DA3 Hexadecimal DA4 DA5 Hexadecimal Example: When the DCRAM address is 2EH. DA0 DA1 DA2 DA3 DA4 DA5 0 1 1 1 0 1 Note: *4. 5 × 7 dots ... 12-digit display 5 × 8 dots ... 12-digit display 5 × 9 dots ... 12-digit display 5 × 7 dots 5 × 8 dots 4 × 9 dots No. 6144-8/43 LC75817NE, 75817NW • ADRAM (Additional data RAM) ADRAM is RAM that is used to store the ADATA display data. ADRAM has a capacity of 12 × 5 bits, and the stored display data is displayed directly without the use of CGROM or CGRAM. The table below lists the correspondence between the 4-bit ADRAM address loaded into AC and the display position on the LCD panel. • When the ADRAM address loaded into AC is 0H. (Number of digit displayed: 12) Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) 0 1 2 3 4 5 6 7 8 9 A B However, when the display shift is performed by specifying ADATA, the ADRAM address shifts as shown below. Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) 1 2 3 4 5 6 7 8 9 A B 0 Display digit 1 2 3 4 5 6 7 8 9 10 11 12 ADRAM address (hexadecimal) B 0 1 2 3 4 5 6 7 8 9 A (Shift left) (Shift right) Note: *5. The ADRAM address is expressed in hexadecimal. Least significant bit ↓ LSB ADRAM address RA0 Most significant bit ↓ MSB RA1 RA2 RA3 Hexadecimal Example: When the ADRAM address is AH RA0 RA1 RA2 RA3 0 1 0 1 Note: *6. 5 × 7 dots ... 12-digit display 5 × 8 dots ... 12-digit display 5 × 9 dots ... 12-digit display 5 dots 5 dots 4 dots • CGROM (Character generator ROM) CGROM is ROM that is used to generate the 240 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns from the 8-bit character codes. CGROM has a capacity of 240 × 45 bits. When a character code is written to DCRAM, the character pattern stored in CGROM corresponding to the character code is displayed at the position on the LCD corresponding to the DCRAM address loaded into AC. • CGRAM (Character generator RAM) CGRAM is RAM to which user programs can freely write arbitrary character patterns. Up to 16 kinds of 5 × 7, 5 × 8, or 5 × 9 dot matrix character patterns can be stored. CGRAM has a capacity of 16 × 45 bits. No. 6144-9/43 LC75817NE, 75817NW Serial Data Input • When CL is stopped at the low level CE CL DI 0 B0 1 B1 0 B2 0 B3 0 A0 0 A1 1 A2 0 A1 1 A2 0 A3 D0 D1 D2 D3 D4 D62 D63 Instruction data (Up to 64 bits) DO • When CL is stopped at the high level CE CL DI 0 B0 1 B1 0 B2 0 B3 0 A0 0 A3 D0 D1 D2 D3 D4 D62 D63 Instruction data (Up to 64 bits) DO • • B0 to B3, A0 to A3: CCB address 42H D0 to D63: Instruction data The data is acquired on the rising edge of the CL signal and latched on the falling edge of the CE signal. When transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. No. 6144-10/43 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 X D52 X D53 Notes: X *7. The data format differs when the “DCRAM data write” instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions .) *8. The data format differs when the “ADRAM data write” instruction is executed in the increment mode (IM = 1). (See detailed instruction descriptions.) *9. The execution times listed here apply when fosc = 300 kHz. The execution times differ when the oscillator frequency fosc differs. Example: When fosc = 210 kHz 300 27 µs ×—— = 39 µs 210 *10.When the sleep mode (SP = 1) is set, the execution time is 27 µs (when fosc = 300 kHz). X KC1 KC2 KC3 KC4 KC5 KC6 Set general-purpose output port state X X X X D54 X X X X X X X X X X X X CTC X X X X X PC1 PC2 PC3 PC4 X X X X 1 1 1 0 0 X X IM X 0 0 X X 0 0 IM R/L SP X 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 D59 D60 D61 D62 0 A M SC X D58 RA0 RA1 RA2 RA3 A M DT1 DT2 D55 D56 D57 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X Set key scan output state X X CT0 CT1 CT2 CT3 X RA0 RA1 RA2 RA3 Set display contrast X X CD41 CD42 CD43 CD44 CD45 X CGRAM data write X AD1 AD2 AD3 AD4 AD5 ADRAM data write *8 DA0 DA1 DA2 DA3 DA4 DA5 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 D40 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 CD1 CD2...CD40 D0 D1...D39 DCRAM data write *7 Set AC address Display shift Display on/off control Set display technique Instruction Instruction Table 0 1 0 1 0 1 0 1 0 1 D63 X: don’t care 0 µs 0 µs 0 µs 27 µs 27 µs 27 µs 27 µs 27 µs 0 µs/27 µs *10 0 µs Execution time *9 LC75817NE, 75817NW No. 6144-11/43 LC75817NE, 75817NW Detailed Instruction Descriptions • Set display technique ... <Sets the display technique> Code D56 D57 D58 D59 D60 D61 X X 0 0 DT1 DT2 D62 D63 0 1 X: don’t care DT1, DT2: Sets the display technique DT1 DT2 0 0 1 0 Output pins Display technique COM9 S60/COM10 1/8 duty, 1/4 bias drive Fixed at the VLCD4 level S60 0 1/9 duty, 1/4 bias drive COM9 S60 1 1/10 duty, 1/4 bias drive COM9 COM10 Note: *11 S60: Segment outputs COMn (n = 9, 10): Common outputs • Display on/off control ... <Turns the display on or off> Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 X X X X M A SC SP DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 DG10 DG11 DG12 0 D61 D62 D63 0 1 0 X: don’t care M, A: Specifies the data to be turned on or off M A 0 0 Both MDATA and ADATA are turned off (The display is forcibly turned off regardless of the DG1 to DG12 data.) Display operating state 0 1 Only ADATA is turned on (The ADATA of display digits specified by the DG1 to DG12 data are turned on.) 1 0 Only MDATA is turned on (The MDATA of display digits specified by the DG1 to DG12 data are turned on.) 1 1 Both MDATA and ADATA are turned on (The MDATA and ADATA of display digits specified by the DG1 to DG12 data are turned on.) Note: *12. MDATA, ADATA 5 × 7 dot matrix display 5 × 8 dot matrix display 5 × 9 dot matrix display .... ADATA . . . . ADATA .... ADATA ... MDATA . . . MDATA ... MDATA DG1 to DG12: Specifies the display digit Display digit Display digit data 1 2 3 4 5 6 7 8 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 9 10 11 12 DG9 DG10 DG11 DG12 For example, if DG1 to DG6 are 1, and DG7 to DG12 are 0, then display digits 1 to 6 will be turned on, and display digits 7 to 12 will be turned off (blanked). No. 6144-12/43 LC75817NE, 75817NW SC: Controls the common and segment output pins SC Common and segment output pin states 0 Output of LCD drive waveforms 1 Fixed at the VLCD4 level (all segments off) Note: *13. When SC is 1, the S1 to S60 and COM1 to COM10 output pins are set to the VLCD4 level, regardless of the M, A, and DG1 to DG12 data. SP: Controls the normal mode and sleep mode SP Mode 0 Normal mode 1 Sleep mode The common and segment pins go to the VLCD4 level and the oscillator on the OSCI, OSCO pins is stopped (although it operates during key scan operations) to reduce current drain. Although the “display on/off control”, “set display contrast”, “set key scan output state”, and “set general-purpose output port state” instructions can be executed in this mode, applications must return the IC to normal mode to execute any of the other instruction settings. • Display shift ... <Shifts the display> Code D56 D57 D58 D59 D60 D61 M A R/L X 0 0 D62 D63 1 1 X: don’t care M, A: Specifies the data to be shifted R/L: Specifies the shift direction M A 0 0 Neither MDATA nor ADATA is shifted Shift operating state R/L 0 Shift direction Shift left 0 1 Only ADATA is shifted 1 Shift right 1 0 Only MDATA is shifted 1 1 Both MDATA and ADATA are shifted • Set AC address... <Specifies the DCRAM and ADRAM address for AC> Code D48 D49 D50 D51 D52 D53 D54 D55 X X DA0 DA1 DA2 DA3 DA4 DA5 D56 D57 D58 D59 RA0 RA1 RA2 RA3 D60 D61 D62 D63 0 1 0 0 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 LSB ↑ Least significant bit DA2 DA3 DA4 DA5 MSB ↑ Most significant bit RA0 to RA3: ADRAM address RA0 RA1 LSB ↑ Least significant bit RA2 RA3 MSB ↑ Most significant bit This instruction loads the 6-bit DCRAM address DA0 to DA5 and the 4-bit ADRAM address RA0 to RA3 into the AC. No. 6144-13/43 LC75817NE, 75817NW • DCRAM data write ... <Specifies the DCRAM address and stores data at that address> Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 X X IM X X AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 D59 D60 X 0 D61 D62 D63 1 0 1 X: don’t care DA0 to DA5: DCRAM address DA0 DA1 DA2 DA3 DA4 LSB ↑ Least significant bit DA5 MSB ↑ Most significant bit AC0 to AC7: DCRAM data (character code) AC0 AC1 AC2 AC3 AC4 AC5 AC6 LSB ↑ Least significant bit AC7 MSB ↑ Most significant bit This instruction writes the 8 bits of data AC0 to AC7 to DCRAM. This data is a character code, and is converted to a 5 × 7, 5 × 8, or 5 × 9 dot matrix display data using CGROM or CGRAM. IM: Sets the method of writing data to DCRAM IM DCRAM data write method 0 Normal DCRAM data write (Specifies the DCRAM address and writes the DCRAM data.) 1 Increment mode DCRAM data write (Increments the DCRAM address by +1 each time data is written to DCRAM.) Notes: *14. · DCRAM data write method when IM = 0 CE CCB address DI CCB address CCB address CCB address (1) (1) (1) 24 bits 24 bits 24 bits Instruction execution time Instruction execution time (1) 24 bits DCRAM Instruction execution time DCRAM data write finishes DCRAM data write finishes Instruction execution time DCRAM data write finishes DCRAM data write finishes · DCRAM data write method when IM = 1 (Instructions other than the “DCRAM data write” instruction cannot be executed.) CE CCB address DI CCB address CCB address CCB address CCB address CCB address (1) (2) (2) (2) (2) (3) 24 bits 8 bits 8 bits 8 bits 8 bits 16 bits Instruction execution time Instruction execution time Instruction execution time Instruction execution time Instruction execution time DCRAM Instruction execution time DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes DCRAM data write finishes Instructions other than the “DCRAM data write” instruction cannot be executed. No. 6144-14/43 LC75817NE, 75817NW Data format at (1) (24 bits) Code D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 DA0 DA1 DA2 DA3 DA4 DA5 D54 D55 D56 D57 D58 X X IM X X D59 D60 X 0 D61 D62 D63 1 0 1 X: don’t care Data format at (2) (8 bits) Code D56 D57 D58 D59 D60 D61 D62 D63 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 Data format at (3) (16 bits) Code D48 D49 D50 D51 D52 D53 D54 D55 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 D56 D57 D58 D59 D60 D61 D62 D63 0 X X X 0 1 0 1 X: don’t care • ADRAM data write ... <Specifies the ADRAM address and stores data at that address> Code D40 D41 D42 D43 D44 AD1 AD2 AD3 AD4 AD5 D45 D46 D47 X X X D48 D49 D50 D51 RA0 RA1 RA2 RA3 D52 D53 D54 D55 D56 D57 D58 X X X X IM X X D59 D60 X 0 D61 D62 D63 1 1 0 X: don’t care RA0 to RA3: ADRAM address RA0 RA1 LSB RA2 RA3 MSB Least significant bit Most significant bit AD1 to AD5: ADATA display data In addition to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data (MDATA), this IC supports direct display of the five accessory display segments provided in each digit as ADATA. This display function does not use CGROM or CGRAM. The figure below shows the correspondence between the data and the display. When ADn = 1 (where n is an integer between 1 and 5) the segment corresponding to that data will be turned on. ADATA S5m+1 S5m+5 (m is an integer between 0 and 11) Corresponding output pin AD1 S5m + 1 (m is an integer between 0 and 11) AD2 S5m + 2 AD3 S5m + 3 AD4 S5m + 4 AD5 S5m + 5 No. 6144-15/43 LC75817NE, 75817NW IM: Sets the method of writing data to ADRAM IM ADRAM data write method 0 Normal ADRAM data write (Specifies the ADRAM address and writes the ADRAM data.) 1 Increment mode ADRAM data write (Increments the ADRAM address by +1 each time data is written to ADRAM.) Notes: *15. · ADRAM data write method when IM = 0 CE CCB address CCB address CCB address DI (4) CCB address (4) 24 bits (4) 24 bits (4) 24 bits 24 bits ADRAM ADRAM data write finishes Instruction execution time Instruction execution time Instruction execution time Instruction execution time ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes · ADRAM data write method when IM = 1 (Instructions other than the “ADRAM data write” instruction cannot be excuted.) CE CCB address CCB address CCB address CCB address CCB address CCB address (4) (5) (5) (5) (5) (6) 24 bits 8 bits 8 bits 8 bits 8 bits 16 bits Instruction execution time Instruction execution time Instruction execution time Instruction execution time DI ADRAM Instruction execution time ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes ADRAM data write finishes Instruction execution time ADRAM data write finishes ADRAM data write finishes Instructions other than the “ADRAM data write” instruction cannot be excuted. Data format at (4) (24 bits) Code D40 D41 D42 D43 D44 AD1 AD2 AD3 AD4 AD5 D45 D46 D47 X X X D48 D49 D50 D51 RA0 RA1 RA2 RA3 D52 D53 D54 D55 D56 D57 D58 X X X X IM X X D59 D60 X 0 D61 D62 D63 1 1 0 X: don’t care Data format at (5) (8 bits) Code D56 D57 D58 D59 D60 AD1 AD2 AD3 AD4 AD5 D61 X D62 D63 X X X: don’t care Data format at (6) (16 bits) Code D48 D49 D50 D51 D52 AD1 AD2 AD3 AD4 AD5 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 X X X 0 X X X 0 1 1 0 X: don’t care No. 6144-16/43 LC75817NE, 75817NW • CGRAM data write ... <Specifies the CGRAM address and stores data at that address> Code D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 X X X D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 X X X X 0 1 1 1 Code Code Code X: don’t care CA0 to CA7: CGRAM address CA0 CA1 CA2 CA3 LSB ↑ Least significant bit CA4 CA5 CA6 CA7 MSB ↑ Most significant bit CD1 to CD45: CGRAM data (5 × 7, 5 × 8, or 5 × 9 dot matrix display data) The bit CDn (where n is an integer between 1 and 45) corresponds to the 5 × 7, 5 × 8, or 5 × 9 dot matrix display data. The figure below shows that correspondence. When CDn is 1 the dots which correspond to that data will be turned on. CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CD32 CD33 CD34 CD35 CD36 CD37 CD38 CD39 CD40 CD41 CD42 CD43 CD44 CD45 Note: *16. CD1 to CD35: 5 × 7 dot matrix display data CD1 to CD40: 5 × 8 dot matrix display data CD1 to CD45: 5 × 9 dot matrix display data No. 6144-17/43 LC75817NE, 75817NW • Set display contrast ... <Sets the display contrast> Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 CT0 CT1 CT2 CT3 X X X X CTC X X X 1 0 0 0 X: don’t care CT0 to CT3: Sets the display contrast (11 steps) CT0 CT1 CT2 CT3 0 0 0 0 LCD drive 4/4 bias voltage supply VLCD0 level 0.94 VLCD = VLCD – (0.03 VLCD × 2) 1 0 0 0 0.91 VLCD = VLCD – (0.03 VLCD × 3) 0 1 0 0 0.88 VLCD = VLCD – (0.03 VLCD × 4) 1 1 0 0 0.85 VLCD = VLCD – (0.03 VLCD × 5) 0 0 1 0 0.82 VLCD = VLCD – (0.03 VLCD × 6) 1 0 1 0 0.79 VLCD = VLCD – (0.03 VLCD × 7) 0 1 1 0 0.76 VLCD = VLCD – (0.03 VLCD × 8) 1 1 1 0 0.73 VLCD = VLCD – (0.03 VLCD × 9) 0 0 0 1 0.70 VLCD = VLCD – (0.03 VLCD × 10) 1 0 0 1 0.67 VLCD = VLCD – (0.03 VLCD × 11) 0 1 0 1 0.64 VLCD = VLCD – (0.03 VLCD × 12) CTC: Sets the display contrast adjustment circuit state CTC Display contrast adjustment circuit state 0 The display contrast adjustment circuit is disabled, and the VLCD0 pin level is forced to the VLCD level. 1 The display contrast adjustment circuit operates, and the display contrast is adjusted. Note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is also possible to apply fine adjustments to the contrast by connecting an external variable resistor to the VLCD4 pin and modifying the VLCD4 pin voltage. However, the following conditions must be met: (VLCD0 – VLCD4) ≥ 4.5 V, and 1.5 V ≥ VLCD4 ≥ 0 V. No. 6144-18/43 LC75817NE, 75817NW • Set key scan output state ... <Sets the key scan output pin states> Code D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 KC1 KC2 KC3 KC4 KC5 KC6 X X X X X X 1 0 0 1 X: don’t care KC1 to KC6: Sets the key scan output pin KS1 to KS6 state Output pin KS1 KS2 KS3 KS4 KS5 KS6 Key scan output state setting data KC1 KC2 KC3 KC4 KC5 KC6 For example, if KC1 to KC3 are set to 1, and KC4 to KC6 are set to 0, then the output pins KS1 to KS3 will output high levels (VDD) and the output pins KS4 to KS6 will output low levels (VSS) in the key scan standby state. Note that key scan output signals are not output from output pins that are set low. • Set general-purpose output port state ... <Sets the states of the general-purpose output ports> Code D56 D57 D58 D59 PC1 PC2 PC3 PC4 D60 D61 1 0 D62 D63 1 0 PC1 to PC4: Sets the general-purpose output port P1 to P4 state Output pin General-purpose output port state setting data P1 P2 P3 P4 PC1 PC2 PC3 PC4 For example, if PC1 and PC2 are set to 1 and PC3 and PC4 are set to 0, then the output pins P1 and P2 will output high levels (VDD) and the output pins P3 and P4 will output low levels (VSS). No. 6144-19/43 LC75817NE, 75817NW Serial Data Output • When CL is stopped at the low level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 X DO KD1 KD2 KD27 KD28 KD29 KD30 SA Output data X: don't care • When CL is stopped at the high level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD3 KD28 KD29 KD30 SA X Output data X: don't care • • • B0 to B3, A0 to A3 : CCB address 43H KD1 to KD30 : Key data SA : Sleep acknowledge data Note: *17. If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid. No. 6144-20/43 LC75817NE, 75817NW Output Data • KD1 to KD30 : Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KS1 KI1 KI2 KI3 KI4 KI5 KD1 KD2 KD3 KD4 KD5 KS2 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 When the states of the KS1 to KS6 output pins during key scan standby are set to low for KS1 and KS2 and to high for KS3 to KS6 with the “set key scan output state” instruction and a key matrix of up to 20 keys is formed from the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. • SA : Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. No. 6144-21/43 LC75817NE, 75817NW Key Scan Operation Functions • Key scan timing The key scan period is 2304T(s). To reliably determine the on/off state of the keys, the LC75817NE/NW scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 4800T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75817NE/NW cannot detect a key press shorter than 4800T(s). KS1 *18 KS2 *18 KS3 *18 KS4 *18 KS5 *18 KS6 *18 1 1 *18 2 2 *18 3 3 *18 T= 4 4 5 *18 5 6 1 fosc *18 6 *18 4608T[s] Key on Note: *18. Note that the high/low states of these pins are determined by the “set key scan output state” instruction, and that key scan output signals are not output from pins that are set to low. • In normal mode • The pins KS1 to KS6 are set to high or low with the “set key scan output state” instruction. • If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 ) the LC75817NE/NW outputs a key data read request • If a key is pressed for longer than 4800T(s) (Where T= —— fosc (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75817NE/NW performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). Key input 1 Key input 2 Key scan 4800T[s] CE Serial data transfer 4800T[s] Serial data transfer Key address (43H) Serial data transfer Key address 4800T[s] Key address DI DO Key data read Key data read request Key data read Key data read Key data read request Key data read request T= 1 fosc No. 6144-22/43 LC75817NE, 75817NW • In sleep mode • The pins KS1 to KS6 are set to high or low with the “set key scan output state” instruction. • If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSCI, OSCO pins is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 ) the LC75817NE/NW outputs a key data read request • If a key is pressed for longer than 4800T(s)(Where T= —— fosc (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75817NE/NW performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). • Sleep mode key scan example Example: When a “display on/off control (SP = 1)” instruction and a “set key scan output state (KC1 to KC5 = 0, KC6 = 1)” instruction are executed (i.e. sleep mode with only KS6 high) "L"KS1 "L"KS2 "L"KS3 "L"KS4 "L"KS5 "H"KS6 When any one of these keys is pressed, the oscillator on the OSCI, OSCO pins is started and the keys are scanned. *19 KI1 KI2 KI3 KI4 KI5 Note: *19. These diodes are required to reliably recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Key input (KS6 line) Key scan 4800T[s] CE Serial data transfer 4800T[s] Serial data Key address transfer (43H) Serial data transfer Key address DI T= 1 fosc DO Key data read Key data read request Key data read Key data read request Multiple Key Presses Although the LC75817NE/NW is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. No. 6144-23/43 LC75817NE, 75817NW 1/8 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM1 COM2 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM8 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM8 are turned on 384T 3072T T = 1 fosc No. 6144-24/43 LC75817NE, 75817NW 1/9 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM1 COM2 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM9 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM9 are turned on 384T 3456T T = 1 fosc No. 6144-25/43 LC75817NE, 75817NW 1/10 Duty, 1/4 Bias Drive Technique VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM1 COM2 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 COM10 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 VLCD0 VLCD1 VLCD2 VLCD3 VLCD4 LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned off LCD driver output when only LCD segments corresponding to COM1 are turned on LCD driver output when only LCD segments corresponding to COM2 are turned on LCD driver output when all LCD segments corresponding to COM1 to COM10 are turned on 384T 3840T T = 1 fosc No. 6144-26/43 LC75817NE, 75817NW Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 3.0V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 3.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 3.) • Power on :Logic block power supply(VDD) on → LCD driver block power supply(VLCD) on • Power off:LCD driver block power supply(VLCD) off → Logic block power supply(VDD) off However, if the logic and LCD driver blocks use a shared power supply, then the power supplies can be turned on and off at the same time. System Reset 1. Reset function The LC75817NE/NW performs a system reset with the VDET. When a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose output ports are set to and held at the low level (VSS). These states that are created as a result of the system reset can be cleared by executing the instruction described below. (See Figure 3.) • Clearing the display off state Display operation can be enabled by executing a “display on/off control” instruction. However, since the contents of the DCRAM, ADRAM, and CGRAM are undefined, applications must set the contents of these memories before turning on display with the “display on/off control” instruction. That is, applications must execute the following instructions. Set display technique DCRAM data write • ADRAM data write (If the ADRAM is used.) • CGRAM data write (If the CGRAM is used.) • Set AC address • Set display contrast (If the display contrast adjustment circuit is used.) • • After executing the above instructions, applications must turn on the display with a “display on/off control” instruction. Note that when applications turn off in the normal mode, applications must turn off the display with a “display on/off control” instruction or the INH pin. • Clearing the key scan disable and key data reset states Executing a “set key scan output state” instruction not only creates a state in which key scanning can be performed, but also clears the key data reset. • Clearing the general-purpose output ports locked at the low level (VSS) state Executing a “set general-purpose output port state” instruction clears the general-purpose output ports locked at the low level (VSS) state and sets the states of the general-purpose output ports. No. 6144-27/43 LC75817NE, 75817NW VDD t1 t2 t3 t4 VDET VDET VLCD Initial state settings Instruction execution Key scan General-purpose output ports Display state Disabled Fixed at the low level (VSS) Execution enabled Can be set to either the high (VDD), or low (VSS) level Display off “Set key scan output “Set general-purpose output port state” state” instruction instruction execution execution Display on “Display on/off control” instruction execution (Turning the display on) Display off ”Display on/off control“ instruction execution (Turning the display off) • t1 ≥ 1 ms (Logic block power supply voltage VDD rise time) • t2 ≥ 0 ms • t3 ≥ 0 ms • t4 ≥ 1 ms (Logic block power supply voltage VDD fall time) • Initial state settings Set display technique DCRAM data write ADRAM data write (If the ADRAM is used.) CGRAM data write (If the CGRAM is used.) Set AC address Set display contrast (If the display contrast adjustment circuit is used.) Figure 3 No. 6144-28/43 LC75817NE, 75817NW 2. Block states during a system reset (1) CLOCK GENERATOR, TIMING GENERATOR When a reset is applied, the oscillator on the OSCI, OSCO pins is started forcibly. This generates the base clock and enables instruction execution. (2) INSTRUCTION REGISTER, INSTRUCTION DECODER When a reset is applied, these circuits are forcibly initialized internally. Then, when instruction execution starts, the IC operates according to those instructions. (3) ADDRESS REGISTER, ADDRESS COUNTER When a reset is applied, these circuits are forcibly initialized internally. Then, the DCRAM and the ADRAM addresses are set when “Set AC address” instruction is executed. (4) DCRAM, ADRAM, CGRAM Since the contents of the DCRAM, ADRAM, and CGRAM become undefined during a reset, applications must execute “DCRAM data write”, “ADRAM data write (If the ADRAM is used.)”, and “CGRAM data write (If the CGRAM is used.)” instructions before executing a “display on/off control” instruction. (5) CGROM Character patterns are stored in this ROM. (6) LATCH Although the value of the data in the latch is undefined during a reset, the ADRAM, CGROM, and CGRAM data is stored by executing a “display on/off control” instruction. (7) COMMON DRIVER, SEGMENT DRIVER These circuits are forced to the display off state when a reset is applied. (8) CONTRAST ADJUSTER Display contrast adjustment circuit operation is disabled when a reset is applied. After that, the display contrast can be set by executing a “set display contrast” instruction. (9) KEY SCAN, KEY BUFFER When a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. Also, the key data is all set to 0. After that, key scanning can be performed by executing a “set key scan output state” instruction. (10) GENERAL PORT The general-purpose output ports are fixed at the low level (VSS) when a reset is applied. (11) CCB INTERFACE, SHIFT REGISTER These circuits go to the serial data input wait state. No. 6144-29/43 GENERAL PORT S1 S58 S59 S60/COM10 COM9 COM1 P4 P1 LC75817NE, 75817NW SEGMENT DRIVER COMMON DRIVER LATCH CGRAM 5 × 9 × 16 bits INSTRUCTION DECODER ADRAM 60 bits INSTRUCTION REGISTER ADDRESS COUNTER CGROM 5 × 9 × 240 bits VLCD CONTRAST ADJUSTER VLCD0 DCRAM 48 × 8 bits VLCD1 ADDRESS REGISTER VLCD2 VLCD3 VLCD4 SHIFT REGISTER CCB INTERFACE VDD VDET KEY BUFFER TIMING GENERATOR VSS KS1 KS6 KS5 KS4 KS3 KS2 KI3 KI2 KI1 KI4 KI5 CE CL DI DO KEY SCAN INH OSCI OSCO CLOCK GENERATOR TEST Blocks that are reset 3. Output pin states during the system reset Output pin State during reset S1 to S59 L (VLCD4) S60/COM10 L (VLCD4)*20 COM1 to COM9 L (VLCD4) KS1 to KS6 L (VSS) P1 to P4 L (VSS) DO H *21 Notes: *20. This output pin is forcibly set to the segment output function and held at the low level (VLCD4). However, when a “set display technique” instruction is executed, the segment output or the common output function is selected as specified by that instruction. *21. Since this output pin is an open-drain output, a pull-up resistor (between 1 kΩ and 10 kΩ) is required. This pin is held at the high level even if a key data read operation is performed before executing a “set key scan output state” instruction. No. 6144-30/43 LC75817NE, 75817NW Sample Application Circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5V VDD COM1 TEST COM2 COM3 COM4 COM5 COM6 COM7 COM8 *22 VSS +8V VLCD OPEN C C VLCD0 VLCD1 VLCD2 VLCD3 C VLCD4 *23 C ≥ 0.047 µF OSCI COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 OPEN OSCO INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply S56 S57 S58 S59 COM10/S60 P1 KKKKKK P2 SSSSSS P3 6 5 4 3 2 1 P4 (general-purpose output ports) used with the backlight controller or other circuit *25 Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-31/43 LC75817NE, 75817NW Sample Application Circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5V VDD COM1 TEST VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 *22 +8V VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C C R VLCD4 *23 C ≥ 0.047 µF 10 kΩ ≥ R ≥ 2.2 kΩ OSCI OSCO INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply COM9 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 OPEN S56 S57 S58 S59 COM10/S60 P1 KKKKKK P2 SSSSSS P3 6 5 4 3 2 1 P4 (general-purpose output ports) used with the backlight controller or other circuit *25 Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-32/43 LC75817NE, 75817NW Sample Application Circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5V VDD COM1 TEST COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 *22 VSS +8V OPEN C C VLCD VLCD0 VLCD1 VLCD2 VLCD3 C VLCD4 *23 C ≥ 0.047 µF OSCI S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 OSCO INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply *25 S56 S57 S58 S59 COM10/S60 P1 KKKKKK P2 SSSSSS P3 6 5 4 3 2 1 P4 (general-purpose output ports) used with the backlight controller or other circuit Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-33/43 LC75817NE, 75817NW Sample Application Circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5V VDD COM1 TEST VSS COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 *22 +8V VLCD VLCD0 R VLCD1 R VLCD2 R VLCD3 C C C R VLCD4 *23 C ≥ 0.047 µF 10 kΩ ≥ R ≥ 2.2 kΩ OSCI OSCO INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S56 S57 S58 S59 COM10/S60 P1 KKKKKK P2 SSSSSS P3 6 5 4 3 2 1 P4 (general-purpose output ports) used with the backlight controller or other circuit *25 Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-34/43 LC75817NE, 75817NW Sample Application Circuit 5 1/10 duty, 1/4 bias drive technique (for use with normal panels) LCD panel +5V VDD COM1 *22 TEST VSS +8V OPEN C C VLCD VLCD0 VLCD1 VLCD2 VLCD3 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 S60/COM10 OSCO S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 S56 S57 S58 S59 P1 P2 P3 P4 C VLCD4 *23 C ≥ 0.047 µF OSCI From the controller To the controller To the controller power supply KKKKKK SSSSSS 6 5 4 3 2 1 (general-purpose output ports) used with the backlight controller or other circuit *25 Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-35/43 LC75817NE, 75817NW Sample Application Circuit 6 1/10 duty, 1/4 bias drive technique (for use with large panels) LCD panel +5V VDD COM1 *22 TEST VSS +8V VLCD VLCD0 R VLCD1 R COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 S60/COM10 VLCD2 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 R VLCD3 C C C R VLCD4 *23 C ≥ 0.047 µF 10 kΩ ≥ R ≥ 2.2 kΩ OSCI OSCO INH *24 CE CL DI K K K K K DO I I I I I 5 4 3 2 1 From the controller To the controller To the controller power supply KKKKKK SSSSSS 6 5 4 3 2 1 S56 S57 S58 S59 P1 P2 P3 P4 (general-purpose output ports) used with the backlight controller or other circuit *25 Key matrix (up to 30 keys) Notes: *22. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75817NE/NW is reset by the VDET. *23. If a variable resistor is not used for display contrast fine adjustment, the VLCD4 pin must be connected to ground. *24. If the function of INH pin is not used, the INH pin must be connected to the logic block power supply VDD. *25. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 6144-36/43 LC75817NE, 75817NW Sample Correspondence between Instructions and the Display (When the LC75817N-8721 is used) No. Instruction (hexadecimal) LSB MSB Display Operation D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 Power application 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 The display is in the off state. Set display technique 2 3 Initializes the IC. (Initialization with the VDET.) 0 8 DCRAM data write (increment mode) 0 2 0 0 1 A DCRAM data write (increment mode) 3 5 DCRAM data write (increment mode) 1 4 DCRAM data write (increment mode) E 4 DCRAM data write (increment mode) 9 5 DCRAM data write (increment mode) F 4 DCRAM data write (increment mode) 0 2 DCRAM data write (increment mode) C 4 DCRAM data write (increment mode) 3 5 DCRAM data write (increment mode) 9 4 DCRAM data write (increment mode) 0 2 DCRAM data write (increment mode) C 4 DCRAM data write (increment mode) 3 4 DCRAM data write (increment mode) 7 3 DCRAM data write (increment mode) 5 3 DCRAM data write (increment mode) 8 3 DCRAM data write (increment mode) 1 3 DCRAM data write (increment mode) 7 3 DCRAM data write (increment mode) E 4 0 A Sets to 1/8 duty 1/4 bias display drive technique Writes the display data “ ” to DCRAM address 00H Writes the display data “S” to DCRAM address 01H Writes the display data “A” to DCRAM address 02H Writes the display data “N” to DCRAM address 03H Writes the display data “Y” to DCRAM address 04H Writes the display data “O” to DCRAM address 05H Writes the display data “ ” to DCRAM address 06H Writes the display data “L” to DCRAM address 07H Writes the display data “S” to DCRAM address 08H Writes the display data “I” to DCRAM address 09H Writes the display data “ ” to DCRAM address 0AH Writes the display data “L” to DCRAM address 0BH Writes the display data “C” to DCRAM address 0CH Writes the display data “7” to DCRAM address 0DH Writes the display data “5” to DCRAM address 0EH Writes the display data “8” to DCRAM address 0FH Writes the display data “1” to DCRAM address 10H Writes the display data “7” to DCRAM address 11H Writes the display data “N” to DCRAM address 12H Continued on next page. No. 6144-37/43 LC75817NE, 75817NW Continued from preceding page. No. Instruction (hexadecimal) LSB MSB Display Operation D40 to D43 D44 to D47 D48 to D51 D52 to D55 D56 to D59 D60 to D63 Set AC address 22 23 0 F F F X 1 4 1 C 1 C 1 C 1 C 1 C 1 C 1 C 8 4 1 4 0 2 Display shift Display shift 26 Display shift 27 Display shift 28 Display shift 29 Display shift 30 33 2 Display shift 25 32 Loads the DCRAM address 00H and the ADRAM 0 address 0H into AC Display on/off control 24 31 0 S A N Y O S A N Y O Y O O L S I L C 7 Shifts the display (MDATA only) to the left L C 7 5 Shifts the display (MDATA only) to the left L C 7 5 8 Shifts the display (MDATA only) to the left L C 7 5 8 1 Shifts the display (MDATA only) to the left L C 7 5 8 1 7 Shifts the display (MDATA only) to the left L C 7 5 8 1 7 N Shifts the display (MDATA only) to the left L S I L S I L S I L S I Display on/off control 0 0 F F 0 X Display on/off control F X Set AC address 0 0 Turns on the LCD for all digits (12 digits) in MDATA Shifts the display (MDATA only) to the left L S I L S I L L C A N Y O N Y O L S I Set to sleep mode, turns off the LCD for all digits L S I L C 7 5 8 1 7 N S A N Y O L S I L Turns on the LCD for all digits (12 digits) in MDATA Loads the DCRAM address 00H and the ADRAM address 0H into AC Note: *26. This sample above assumes the use of 12 digits 5 × 7 dot matrix LCD. CGRAM and ADRAM are not used. X: don’t care No. 6144-38/43 LC75817NE, 75817NW Notes on the controller key data read techniques 1. Timer based key data acquisition • Flowchart CE = L NO DO = L YES Key data read processing • Timing chart Key on Key on Key input Key scan t5 t6 t5 t5 CE t8 t8 t8 Key address DI t7 Key data read t7 t7 DO Key data read request t9 Controller determination (Key on) t9 Controller determination (Key on) t9 Controller determination (Key off) t9 Controller determination (Key on) Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) t7: Key address (43H) transfer time t8: Key data read time 1 T = ——— fosc • Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. No. 6144-39/43 LC75817NE, 75817NW 2. Interrupt based key data acquisition • Flowchart CE = L NO DO = L YES Key data read processing Wait for at least t10 CE = L NO DO = H YES Key off • Timing chart Key on Key on Key input Key scan t5 t5 t6 t5 CE t8 t8 t8 t8 Key address DI Key data read t7 t7 t7 t7 DO Key data read request t10 Controller determination (Key on) Controller determination (Key off) t10 Controller determination (Key on) Controller determination (Key on) t10 Controller determination (Key on) t10 Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (4800T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600T(s)) t7: Key address (43H) transfer time t8: Key data read time 1 T = ——— fosc No. 6144-40/43 LC75817NE, 75817NW • Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. No. 6144-41/43 Lower 4bits Upper 4bits LC75817N-8721 Character Font (Standard) A10735 LC75817NE, 75817NW No. 6144-42/43 LC75817NE, 75817NW Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 2002. Specifications and information herein are subject to change without notice. PS No. 6144-43/43