Ordering number : ENN*7980 Preliminary SANYO Semiconductors DATA SHEET LC75857E LC75857W CMOS IC 1/3, 1/4 Duty LCD Display Drivers with Key Input Function Overview The LC75857E and LC75857W are 1/3 duty and 1/4 duty LCD display drivers that can directly drive up to 164 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features • • • • • • • • • • • • • Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) 1/3 duty and 1/4 duty drive schemes can be controlled from serial data. 1/2 bias and 1/3 bias drive schemes can be controlled from serial data. Capable of driving up to 126 segments using 1/3 duty and up to 164 segments using 1/4 duty. Sleep mode and all segments off functions that are controlled from serial data. Switching between key scan output and segment output can be controlled from the serial data. The key scan operation enabled/disabled state can be controlled from the serial data. Switching between segment output port and general-purpose output port can be controlled from serial data. The common and segment output waveform frame frequency can be controlled from the serial data. Switching between RC oscillator mode and external clock mode can be controlled from the serial data. Serial data I/O supports CCB format communication with the system controller. Direct display of display data without the use of a decoder provides high generality. Independent VLCD for the LCD driver block. (When the logic block supply voltage VDD is in the range 3.6 to 6.0 V, VLCD can be set to a voltage in the range 0.75 × VDD to 6.0 V, and when VDD is in the range 2.7 to 3.6 V, VLCD can be set to a voltage in the range 2.7 to 6.0 V.) • Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 92504TN (OT) No. 7980-1/39 LC75857E, LC75857W Specifications Absolute Maximum Ratings at Ta=25°C, VSS=0V Parameter Maximum supply voltage Input voltage Output voltage Output current Allowable power dissipation Symbol Conditions Ratings Unit VDD max VDD –0.3 to +7.0 VLCD max VLCD –0.3 to +7.0 VIN1 CE, CL, DI –0.3 to +7.0 VIN2 OSC,TEST –0.3 to VDD +0.3 VIN3 VLCD1, VLCD2, KI1 to KI5 V –0.3 to VLCD +0.3 VOUT1 DO VOUT2 OSC VOUT3 S1 to S42, COM1 to COM4, KS1 to KS6, P1 to P4 IOUT1 S1 to S42 IOUT2 COM1 to COM4 3 IOUT3 KS1 to KS6 1 IOUT4 P1 to P4 5 Pd max V –0.3 to +7.0 –0.3 to VDD +0.3 V –0.3 to VLCD +0.3 300 Ta = 85°C 200 µA mA mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = –40 to +85°C, VSS=0V Parameter Symbol VDD Supply voltage Input voltage Input high level voltage Input low level voltage VLCD Ratings Conditions min VDD typ Unit max 2.7 6.0 VLCD: VDD = 3.6 V to 6.0 V 0.75 VDD 6.0 VLCD: VDD = 2.7 V to 3.6 V 2.7 6.0 VLCD1 VLCD1 2/3 VLCD VLCD VLCD2 VLCD2 1/3 VLCD VLCD VIH1 CE, CL, DI 0.8 VDD 6.0 VIH2 KI1 to KI5 0.6 VLCD VLCD VIH3 OSC: External clock mode 0.7 VDD VDD VIL1 CE, CL, DI 0 0.2 VDD VIL2 KI1 to KI5 0 0.2 VLCD VIL3 OSC: External clock mode 0 0.3 VDD Recommended RC oscillator external resistor ROSC OSC: RC oscillator mode 39 Recommended RC oscillator external capacitor COSC OSC: RC oscillator mode 1000 Guaranteed RC oscillator operating range fOSC OSC: RC oscillator mode External clock frequency fCK OSC: External clock mode External clock duty DCK OSC: External clock mode V V V V kΩ pF 19 38 76 kHz :Figure 4 19 38 76 kHz :Figure 4 30 50 70 % Data setup time tds CL, DI :Figures 2,3 160 ns Data hold time tdh CL, DI :Figures 2,3 160 ns CE wait time tcp CE, CL :Figures 2,3 160 ns CE setup time tcs CE, CL :Figures 2,3 160 ns CE hold time tch CE, CL :Figures 2,3 160 ns High level clock pulse width tøH CL :Figures 2,3 160 ns Low level clock pulse width tøL CL :Figures 2,3 160 ns Rise time tr CE, CL, DI :Figures 2,3 160 Fall time tf CE, CL, DI :Figures 2,3 160 ns ns DO output delay time tdc DO RPU=4.7 kΩ, CL=10pF *1 :Figures 2,3 1.5 µs DO rise time tdr DO RPU=4.7 kΩ, CL=10pF *1 :Figures 2,3 1.5 µs Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL. No. 7980-2/39 LC75857E, LC75857W Electrical Characteristics for the Allowable Operating Ranges Parameter Symbol Hysteresis Power-down detection voltage Ratings Conditions min VH1 CE, CL, DI 0.1 VDD KI1 to KI5 0.1 VLCD Input low level current Input floating voltage Pull-down resistance 2.0 IIH2 OSC: VI = VDD External clock mode 5.0 IIL1 CE, CL, DI: VI = 0 V –5.0 IIL2 OSC: VI = 0 V External clock mode –5.0 VIF KI1 to KI5 Oscillator frequency 0.05 VLCD KI1 to KI5: VLCD = 5.0 V 50 100 250 KI1 to KI5: VLCD = 3.0 V 100 200 500 6.0 KS1 to KS6: IO = –500 µA VLCD = 3.6 to 6.0 V µA V kΩ µA VLCD – 1.0 VLCD – 0.5 VLCD – 0.2 KS1 to KS6: IO = –250 µA VLCD = 2.7 to 3.6 V VLCD – 0.8 VLCD – 0.4 VLCD – 0.1 VOH2 P1 to P4: IO = –1 mA VLCD – 0.9 VOH3 S1 to S42: IO = –20 µA VLCD – 0.9 VOH4 COM1 to COM4: IO = –100 µA VLCD – 0.9 V KS1 to KS6: IO = 25 µA VLCD = 3.6 to 6.0 V 0.2 0.5 1.5 KS1 to KS6: IO = 12.5 µA VLCD = 2.7 to 3.6 V 0.1 0.4 1.2 VOL2 P1 to P4: IO = 1 mA 0.9 VOL3 S1 to S42: IO = 20 µA 0.9 VOL4 COM1 to COM4: IO = 100 µA VOL5 DO: IO = 1 mA VMID1 COM1 to COM4: 1/2 bias, IO = ±100 µA 1/2 VLCD – 0.9 1/2 VLCD + 0.9 VMID2 S1 to S42: 1/3 bias,IO = ±20 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 VMID3 S1 to S42: 1/3 bias, IO = ±20 µA 1/3 VLCD – 0.9 1/3 VLCD + 0.9 VMID4 COM1 to COM4: 1/3 bias,IO = ±100 µA 2/3 VLCD – 0.9 2/3 VLCD + 0.9 VMID5 COM1 to COM4: 1/3 bias,IO = ±100 µA 1/3 VLCD – 0.9 fosc OSC: ROSC = 39 kΩ, COSC = 1000 pF IDD1 VDD :Sleep mode V 0.9 0.1 0.5 V 1/3 VLCD + 0.9 30.4 38 45.6 kHz 100 IDD2 VDD: VDD = 6.0 V, output open,fosc = 38 kHz ILCD1 VLCD : Sleep mode ILCD2 VLCD: VLCD = 6.0 V, output open, 1/2 bias, fosc = 38 kHz 100 200 ILCD3 VLCD: VLCD = 6.0 V, output open, 1/3 bias, fosc = 38 kHz 60 120 Current drain V µA DO: VO = 6.0 V VOL1 Output middle level voltage *2 2.4 5.0 VOH1 Output low level voltage 2.2 CE, CL, DI: VI = 6.0 V IOFFH Output high level voltage V IIH1 RPD Output off leakage current Unit max VH2 VDET Input high level current typ 300 600 5 µA Nete: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.) Package Dimensions unit: mm unit: mm 3159A-QIP64E 3190A-SQFP64 [LC75857E] [LC75857W] 33 48 0.5 48 12.0 10.0 0.8 17.2 14.0 33 32 49 32 10.0 12.0 17.2 14.0 49 64 64 17 16 0.8 0.35 0.18 0.15 SANYO: QIP64E 1.7max (1.5) (2.7) (1.25) 3.0max 0.1 16 (0.5) 0.15 (1.0) .1 1 17 1 SANYO: SQFP64 No. 7980-3/39 LC75857E, LC75857W VLCD VLCD1 To the common segment driver VLCD2 Excluding these registors. Figure 1 1. Serial data I/O timing when CL is stopped at the low level VIH1 CE CL VIL1 tø H VIH1 50% VIL1 tø L tr DI tf tch tcp tcs VIH1 VIL1 tds tdh tdc DO D0 tdr D1 Figure 2 2. Serial data I/O timing when CL is stopped at the high level VIH1 CE VIL1 tø L tø H VIH1 50% VIL1 CL tf tr tcp tcs tch VIH1 VIL1 DI tds tdh DO D0 D1 tdc tdr Figure 3 3. OSC pin clock timing in external clock mode tCKH OSC tCKL VIH3 50% VIL3 fCK = 1 [kHz] tCKH + tCKL DCK = tCKH ×100[%] tCKH + tCKL Figure 4 No. 7980-4/39 LC75857E, LC75857W KS6 KS5 KS4 KS3/S42 KS2/S41 KS1/S40 COM1 COM2 COM3 COM4/S39 S38 S37 S36 S35 S34 S33 Pin Assignments 48 33 49 32 KI1 KI2 KI3 KI4 KI5 VDD VLCD VLCD1 VLCD2 VSS TEST OSC DO CE CL DI S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 LC75857E/W 64 17 16 P1/S1 P2/S2 P3/S3 P4/S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 1 Top view No. 7980-5/39 LC75857E, LC75857W S1/P1 S2/P2 S3/P3 S5 S4/P4 S38 COM4/S39 COM3 COM2 COM1 Block Diagram VLCD SEGMENT DRIVER & LATCH VLCD1 COMMON DRIVER VLCD2 VSS TEST CLOCK GENERATOR OSC CONTROL REGISTER DO SHIFT REGISTER CCB INTERFACE DI CL KEY BUFFER CE VDD KS6 KS5 KS4 S42/KS3 S41/KS2 S40/KS1 KEY SCAN KI5 KI4 KI3 KI2 KI1 VDET No. 7980-6/39 LC75857E, LC75857W Pin Functions Pin Pin No. S1/P1 to S4/P4 S5 to S38 1 to 4 COM1 to COM3 COM4/S39 5 to 38 42 to 40 39 Active I/O Handling when unused Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control. — O OPEN Common driver outputs The frame frequency is fo [Hz] The COM4/S39 pin can be used as a segment output in 1/3 duty. — O OPEN — O OPEN Function KS1/S40 KS2/S41 KS3/S42 KS4 to KS6 43 44 45 46 to 48 Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S40 to KS3/S42 pins can be used as segment outputs when so specified by the control data. KI1 to KI5 49 to 53 Key scan inputs These pins have built-in pull-down resistors. H I GND OSC 60 The OSC pin can be used to form an oscillator circuit with an external resistor and an external capacitor. If external clock mode is selected with the control data, this pin is used to input an external clock signal. — I/O VDD CE 62 H I CL 63 DI 64 DO 61 Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data — O OPEN TEST 59 This pin must be connected to ground. — I — VLCD1 56 Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used. — I OPEN VLCD2 57 Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used. — I OPEN VDD 54 Logic block power supply connection. Provide a voltage of between 2.7 and 6.0V. — — — VLCD 55 LCD driver block power supply connection. A voltage in the range 0.75 × VDD to 6.0 V must be provided when VDD is in the range 3.6 to 6.0 V, and a voltage in the range 2.7 V to 6.0 V must be provided when VDD is in the range 2.7 to 3.6 V. — — — VSS 58 Power supply connection. Connect to ground. — — — I — I GND No. 7980-7/39 LC75857E, LC75857W Serial Data Input 1. 1/3 duty (1) When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D41 D42 0 0 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C 0 Display data Control data 0 DD DO 0 1 0 0 0 0 1 0 D43 D44 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 D83 D84 0 0 D85 D86 B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 0 0 0 0 Display data Display data 0 0 0 0 0 0 0 0 0 0 0 0 Fixed data D125 D126 0 0 0 0 0 0 0 0 0 0 0 Fixed data 0 1 DD 0 0 0 0 0 0 0 0 0 1 0 DD Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data No. 7980-8/39 LC75857E, LC75857W (2) When CL is stopped at the high level CE CL DI 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D1 D2 D41 D42 0 0 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C Display data 0 Control data 0 DD DO 0 0 1 0 0 0 0 1 B0 B1 B2 B3 A0 A1 A2 A3 D43 D44 D83 D84 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 D85 D86 D125 D126 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data 0 0 0 0 0 0 0 0 0 0 0 Fixed data Display data 0 0 0 0 0 0 0 0 0 0 0 Fixed data 0 1 DD 0 0 0 0 0 0 0 0 1 0 DD Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data CCB address ............ 42H D1 to D126 .............. Display data SP ............................ Normal mode/sleep mode control data KC0 to KC2 .............. Key scan output state setting data KSC .......................... Key scan operation enabled/disabled state setting data K0, K1 ...................... Key scan output/segment output selection data P0 to P2 .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data No. 7980-9/39 LC75857E, LC75857W 2. 1/4duty (1) When CL is stopped at the low level CE CL DI 0 1 0 0 0 0 1 0 D1 B0 B1 B2 B3 A0 A1 A2 A3 D40 D41 D42 D43 D44 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C 0 Control data Display data 0 DD DO 0 1 0 0 0 0 1 0 D45 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 D85 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 D84 0 0 0 0 0 0 0 0 0 D124 0 Display data D164 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fixed data 1 1 0 DD Fixed data 0 0 DD Fixed data Display data 0 D125 B0 B1 B2 B3 A0 A1 A2 A3 0 Display data 0 0 0 0 0 0 0 0 0 1 1 DD Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data No. 7980-10/39 LC75857E, LC75857W (2) When CL is stopped at the high level CE CL DI 0 1 0 0 0 0 1 0 D1 D40 D41 D42 D43 D44 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C Control data Display data B0 B1 B2 B3 A0 A1 A2 A3 0 0 DD DO 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D45 D84 0 0 0 0 0 0 0 0 0 0 Display data D85 D124 0 0 0 0 0 0 0 0 0 0 D164 0 Display data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DD 0 0 0 0 0 0 0 0 0 1 0 DD Fixed data Display data D125 0 Fixed data 0 Fixed data 0 0 0 0 0 0 0 0 0 1 1 DD Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data CCB address ............ 42H D1 to D164 .............. Display data SP ............................ Normal mode/sleep mode control data KC0 to KC2 .............. Key scan output state setting data KSC .......................... Key scan operation enabled/disabled state setting data K0, K1 ...................... Key scan output/segment output selection data P0 to P2 .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data No. 7980-11/39 LC75857E, LC75857W Control Data Functions 1. SP : Normal mode/sleep mode control data This control data bit switches the IC between normal mode and sleep mode. SP Mode 0 Normal 1 sleep OSC pin state RC oscillator mode External clock mode Common and segment pin output states Oscillator operating External clock signal accepted LCD drive waveforms are output Oscillator stopped Acceptance of the external (The oscillator operates clock signal is disabled. Key scan operating state General-purpose output port states The state can be set The state can be set L (VSS) during key scan operations.) (The external clock signal is accepted during key scan operations) Note: See the descriptions of the KC- to KC2, KSC, K0, K1, and P0 to P2 bits in the control data for details on setting the key scan operating state and setting the general-purpose output port state. 2. KC0 to KC2 : Key scan output state setting data These control data bits set the states of the key scan output pins KS1 to KS6. Control data Output pin states during key scan standby KC0 KC1 KC2 KS1 KS2 KS3 KS4 KS5 KS6 0 0 0 H H H H H H 0 0 1 L H H H H H 0 1 0 L L H H H H 0 1 1 L L L H H H 1 0 0 L L L L H H 1 0 1 L L L L L H 1 1 0 L L L L L L Note: This assumes that the KS1/S40 to KS3/S42 output pins are selected for key scan output. Also note that key scan output signals are not output from output pins that are set to the low level. 3. KSC : Key scan operation enabled/disabled state setting data This control data bit enables or disables key scan operation. KSC Key scan operating state 0 Key scan operation enabled (A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed .) Key scan operation disabled (No key scan operation is performed, even if any of the keys in the key matrix are pressed. If this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared. (DO is set high.)) 1 4. K0, K1 : Key scan output /segment output selection data These control data bits switch the functions of the KS1/S40 to KS3/S42 output pins between key scan output and segment output. Control data Output pin state K0 K1 KS1/S40 KS2/S41 KS3/S42 Maximum number of input keys 0 0 KS1 KS2 KS3 30 0 1 S40 KS2 KS3 25 1 0 S40 S41 KS3 20 1 1 S40 S41 S42 15 Note: KSn(n = 1 to 3) : Key scan output Sn (n = 40 to 42): Segment output No. 7980-12/39 LC75857E, LC75857W 5. P0 to P2 : Segment output port/general-purpose output port selection data These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port. Control data Output pin state P0 P1 P2 S1/P1 S2/P2 S3/P3 S4/P4 0 0 0 S1 S2 S3 S4 0 0 1 P1 S2 S3 S4 0 1 0 P1 P2 S3 S4 0 1 1 P1 P2 P3 S4 1 0 0 P1 P2 P3 P4 Note: Sn(n=1 to 4): Segment output port Pn(n=1 to 4): General-purpose output port The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Corresponding display data Output pin 1/3 duty 1/4 duty S1/P1 D1 D1 S2/P2 D4 D5 S3/P3 D7 D9 S4/P4 D10 D13 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data D13 is 1, and will output a low level (Vss) when D13 is 0. 6. SC : Segment on/off control data This control data bit controls the on/off state of the segments. SC Display state 0 on 1 off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 7. DR : 1/2 bias or 1/3 bias drive selection data This control data bit switches between LCD 1/2 bias or 1/3 bias drive. DR Bias drive scheme 0 1/3 bias drive 1 1/2 bias drive 8. DT : 1/3 duty or 1/4 duty drive selection data This control data bit switches between LCD 1/3 duty or 1/4 duty drive. DT Duty drive scheme Output pin state (COM4/S39) 0 1/4 duty drive COM4 1 1/3 duty drive S39 Note: COM4: Common output S39 : Segment output No. 7980-13/39 LC75857E, LC75857W 9. FC0 to FC2 : Common and segment output waveform frame frequency setting data These control data bits set the common and segment output waveform frequency. Control data FC0 FC1 Frame frequency, fo (Hz) FC2 0 0 0 fOSC/768, fCK/768 0 0 1 fOSC/576, fCK/576 0 1 0 fOSC/384, fCK/384 0 1 1 fOSC/288, fCK/288 1 0 0 fOSC/192, fCK/192 10. OC : RC oscillator mode/external clock mode switching selection data This control data bit selects the OSC pin function (RC oscillator mode or external clock mode). OC OSC pin function 0 RC oscillator mode 1 External clock mode Note: If RC oscillator mode is selected, connect an external resistor Rosc and an external capacitor Cosc to the OSC pin. Display Data and Output Pin Correspondence 1. 1/3 duty Output pin COM1 COM2 COM3 Output pin COM1 COM2 COM3 S1/P1 D1 D2 D3 S22 D64 D65 D66 S2/P2 D4 D5 D6 S23 D67 D68 D69 S3/P3 D7 D8 D9 S24 D70 D71 D72 S4/P4 D10 D11 D12 S25 D73 D74 D75 S5 D13 D14 D15 S26 D76 D77 D78 S6 D16 D17 D18 S27 D79 D80 D81 S7 D19 D20 D21 S28 D82 D83 D84 S8 D22 D23 D24 S29 D85 D86 D87 S9 D25 D26 D27 S30 D88 D89 D90 S10 D28 D29 D30 S31 D91 D92 D93 S11 D31 D32 D33 S32 D94 D95 D96 S12 D34 D35 D36 S33 D97 D98 D99 S13 D37 D38 D39 S34 D100 D101 D102 S14 D40 D41 D42 S35 D103 D104 D105 S15 D43 D44 D45 S36 D106 D107 D108 S16 D46 D47 D48 S37 D109 D110 D111 S17 D49 D50 D51 S38 D112 D113 D114 S18 D52 D53 D54 COM4/S39 D115 D116 D117 S19 D55 D56 D57 KS1/S40 D118 D119 D120 S20 D58 D59 D60 KS2/S41 D121 D122 D123 S21 D61 D62 D63 KS3/S42 D124 D125 D126 Note: This is for the case where the output pins S1/P1 to S4/P4, COM4/S74, KS1/S40 to KS3/S42 are selected for use as segment outputs. For example, the table below lists the segment output states for the S11 output pin. Display data Output pin state (S11) D31 D32 D33 0 0 0 The LCD segments for COM1, COM2 and COM3 are off. 0 0 1 The LCD segment for COM3 is on. 0 1 0 The LCD segment for COM2 is on. 0 1 1 The LCD segments for COM2 and COM3 are on. 1 0 0 The LCD segment for COM1 is on. 1 0 1 The LCD segments for COM1 and COM3 are on. 1 1 0 The LCD segments for COM1 and COM2 are on. 1 1 1 The LCD segments for COM1, COM2 and COM3 are on. No. 7980-14/39 LC75857E, LC75857W 2. 1/4 duty Output pin COM1 COM2 COM3 COM4 Output pin COM1 COM2 COM3 COM4 S1/P1 D1 D2 D3 D4 S22 D85 D86 D87 D88 S2/P2 D5 D6 D7 D8 S23 D89 D90 D91 D92 S3/P3 D9 D10 D11 D12 S24 D93 D94 D95 D96 S4/P4 D13 D14 D15 D16 S25 D97 D98 D99 D100 S5 D17 D18 D19 D20 S26 D101 D102 D103 D104 S6 D21 D22 D23 D24 S27 D105 D106 D107 D108 S7 D25 D26 D27 D28 S28 D109 D110 D111 D112 S8 D29 D30 D31 D32 S29 D113 D114 D115 D116 S9 D33 D34 D35 D36 S30 D117 D118 D119 D120 S10 D37 D38 D39 D40 S31 D121 D122 D123 D124 S11 D41 D42 D43 D44 S32 D125 D126 D127 D128 S12 D45 D46 D47 D48 S33 D129 D130 D131 D132 S13 D49 D50 D51 D52 S34 D133 D134 D135 D136 S14 D53 D54 D55 D56 S35 D137 D138 D139 D140 S15 D57 D58 D59 D60 S36 D141 D142 D143 D144 S16 D61 D62 D63 D64 S37 D145 D146 D147 D148 S17 D65 D66 D67 D68 S38 D149 D150 D151 D152 S18 D69 D70 D71 D72 KS1/S40 D153 D154 D155 D156 S19 D73 D74 D75 D76 KS2/S41 D157 D158 D159 D160 S20 D77 D78 D79 D80 KS3/S42 D161 D162 D163 D164 S21 D81 D82 D83 D84 Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S40 to KS3/S42 are selected for use as segment outputs. For example, the table below lists the segment output states for the S11 output pin. Display data D41 D42 D43 D44 Output pin state (S11) 0 0 0 0 The LCD segments for COM1,COM2,COM3 and COM4 are off. 0 0 0 1 The LCD segment for COM4 is on. 0 0 1 0 The LCD segment for COM3 is on. 0 0 1 1 The LCD segments for COM3 and COM4 are on. 0 1 0 0 The LCD segment for COM2 is on. 0 1 0 1 The LCD segments for COM2 and COM4 are on. 0 1 1 0 The LCD segments for COM2 and COM3 are on. 0 1 1 1 The LCD segments for COM2,COM3 and COM4 are on. 1 0 0 0 The LCD segment for COM1 is on. 1 0 0 1 The LCD segments for COM1 and COM4 are on. 1 0 1 0 The LCD segments for COM1 and COM3 are on. 1 0 1 1 The LCD segments for COM1,COM3 and COM4 are on. 1 1 0 0 The LCD segments for COM1 and COM2 are on. 1 1 0 1 The LCD segments for COM1,COM2 and COM4 are on. 1 1 1 0 The LCD segments for COM1,COM2 and COM3 are on. 1 1 1 1 The LCD segments for COM1,COM2,COM3 and COM4 are on. No. 7980-15/39 LC75857E, LC75857W Serial Data Output 1. When CL is stopped at the low level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO X KD1 KD2 KD27 KD28 KD29 KD30 SA Output data X: don't care Note: B0 to B3, A0 to A3······CCB address 2. When CL is stopped at the high level CE CL DI 1 1 0 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 DO KD28 KD29 KD30 SA X KD1 KD2 KD3 X Output data X: don't care Note: B0 to B3, A0 to A3······CCB address CCB address ...... 43H KD1 to KD30 ........ Key data SA ........................ Sleep acknowledge data Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid. No. 7980-16/39 LC75857E, LC75857W Output Data 1. KD1 to KD30 : Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. KS1/S40 KI1 KI2 KI3 KI4 KI5 KD1 KD2 KD3 KD4 KD5 KS2/S41 KD6 KD7 KD8 KD9 KD10 KS3/S42 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 When the KS1/S40 and KS2/S41 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3/S42,KS4 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 2. SA : Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. Sleep Mode Functions Sleep mode is set up by setting SP in the control data to 1. When sleep mode is set up, both the segment and the common outputs will go to the low level. In RC oscillator mode (OC = 0), the oscillator on the OSC pin will stop (although it will operate during key scan operations), and in external clock mode (OC = 1), the external clock signal reception on the OSC pin will stop (although the clock signal will be received during key scan operations). Thus this mode reduces power consumption. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under control of the P0 to P2 bits in the control data even in sleep mode. Sleep mode is cancelled by setting SP in the control data to 0. No. 7980-17/39 LC75857E, LC75857W Key Scan Operation Functions 1. Key scan timing The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75857E/W scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75857E/W cannot detect a key press shorter than 615T(s). KS1 *3 KS2 *3 KS3 *3 1 1 *3 2 2 *3 3 3 *3 T= KS4 *3 KS5 *3 KS6 *3 4 4 5 *3 5 6 Key on 1 1 = fCK fosc *3 6 *3 576T[s] Note: *3. These are set to the high or low level by the KC0 to KC2 bits in the control data. Key scan output signals are not output from pins that are set to the low level. 2. Normal mode, when key scan operations are enabled • The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the description of the control data.) • When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 ) the LC75857E/W outputs a key data read 1 = —— • If a key is pressed for longer than 615 T (s) (Where T= —— fCK fosc request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performes another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 to 10 kΩ). Key input 1 Key input 2 Key scan 615T[s] 615T[s] 615T[s] CE Serial data transfer (KSC = 0) Serial data transfer (KSC = 0) Key address (43H) Serial data transfer (KSC = 0) Key address Key address DI DO Key data read Key data read Key data read request Key data read request Key data read Key data read request T= 1 1 = fCK fosc No. 7980-18/39 LC75857E, LC75857W 3. Sleep mode, when key scan operations are enabled • The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the description of the control data.) • When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, either the OSC pin oscillator starts (if the IC is in RC oscillator mode) or the IC starts accepting the external clock signal (if the IC is in external clock mode), a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recoghized by determinig whether multiple key data bits are set. 1 = —— 1 ) the LC75857E/W outputs a key data read • If a key is pressed for longer than 615T(s)(Where T= —— fosc fCK request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. • After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 kΩ). • Sleep mode key scan example Example: KC0 = 1, KC1 = 0, KC2 = 1, (sleep with only KS6 high) [L] KS1 [L] KS2 [L] KS3 [L] KS4 [L] KS5 [H] KS6 When any one of these keys is pressed, either the OSC pin oscillator starts (if the IC is in RC oscillator mode) or the IC starts accepting the external clock signal (if the IC is in external clock mode) and a key scan operation is performed. *4 KI1 KI2 KI3 KI4 KI5 Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. Key input (KS6 line) Key scan 615T[s] 615T[s] CE Serial data transfer (KSC = 0) Serial data transfer (KSC = 0) Key address (43H) Serial data transfer (KSC = 0) Key address T= DI 1 1 = fosc fCK DO Key data read Key data read request Key data read Key data read request No. 7980-19/39 LC75857E, LC75857W 4. Normal/sleep mode, when key scan operations are disabled • The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. • No key scan operation is performed, whichever key is pressed. • If the key scan disabled state (KSC = 1 in the control data) is set during a key scan, the key scan is stopped. • If the key scan disabled state (KSC = 1 in the control data) is set when a key data read request (a low level on DO) is output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high). Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10 kΩ). • The key scan disabled state is cleared by setting KSC in the control data to 0. Key input 1 Key input 2 Key scan 615T[s] 615T[s] CE Serial data transfer Serial data transfer (KSC = 0) (KSC = 1) Serial data transfer (KSC = 0) Serial data transfer Serial data transfer (KSC = 1) (KSC = 0) Key address (43H) DI DO Key data read request Key data read request T= Key data read 1 1 = fosc fCK Multiple Key Presses Although the LC75857E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. No. 7980-20/39 LC75857E, LC75857W 1/3 Duty, 1/2 Bias Drive Technique fo[Hz] COM1 VLCD VLCD1,VLCD2 0V COM2 VLCD VLCD1,VLCD2 0V COM3 VLCD VLCD1,VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are turned off. VLCD VLCD1,VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on VLCD VLCD1,VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1,VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1,VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1,VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1,VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1,VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are on. VLCD VLCD1,VLCD2 0V 1/3 Duty, 1/2 Bias Waveforms Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data f0 = When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192 No. 7980-21/39 LC75857E, LC75857W 1/3 Duty, 1/3 Bias Drive Technique fo[Hz] COM1 VLCD VLCD1 VLCD2 0V COM2 VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V COM3 LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are turned off. VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on. VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1 VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1 VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are on. 1/3 Duty, 1/3 Bias Waveforms Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data f0 = When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192 No. 7980-22/39 LC75857E, LC75857W 1/4 Duty, 1/2 Bias Drive Technique fo[Hz] COM1 VLCD VLCD1, VLCD2 0V COM2 VLCD VLCD1, VLCD2 0V COM3 VLCD VLCD1, VLCD2 0V COM4 VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM1 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM2 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on. VLCD VLCD1, VLCD2 0V LCD driver output when only LCD segments corresponding to COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when LCD segments corresponding to COM2 and COM4 are on. VLCD VLCD1, VLCD2 0V LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. VLCD VLCD1, VLCD2 0V 1/4 Duty, 1/2 Bias Waveforms Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data f0 = When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192 No. 7980-23/39 LC75857E, LC75857W 1/4 Duty, 1/3 Bias Drive Technique fo[Hz] VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V COM1 COM2 COM3 COM4 LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on. LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on. LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on. 1/4 Duty, 1/3 Bias Waveforms Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data f0 = When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data f0 = When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192 No. 7980-24/39 LC75857E, LC75857W Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.2V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 5 and Figure 6.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 5 and Figure 6.) • Power on :Logic block power supply(VDD) on → LCD driver block power supply(VLCD) on • Power off:LCD driver block power supply(VLCD) off → Logic block power supply(VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. System Reset The LC75857E/W supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. 1. Reset methods If at least 1 ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/3 duty: the display data D1 to D126 and the control data, 1/4 duty: the display data D1 to D164 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. (See Figure 5 and Figure 6.) No. 7980-25/39 LC75857E, LC75857W • 1/3 duty t1 t2 t3 t4 VDD VDET VDET VLCD Internal data CE D1 to D42, SP, KC0 to KC2, KSC, K0, K1,P0 to P2, SC, DR, DT, FC0 to FC2, OC VIL1 Display and control data transfer Undefined Defined Undefined Internal data (D43 to D84) Undefined Defined Undefined Internal data (D85 to D126) Undefined Defined Undefined System reset period Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time) t2 ≥ 0 t3 ≥ 0 t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time) Figure 5 • 1/4 duty t1 t2 t3 t4 VDD VDET VDET VLCD CE D1 to D44, SP, KC0 to KC2, KSC, K0, Internal data K1, P0 to P2, SC, DR, DT,FC0 to FC2, OC Internal data (D45 to D84) VIL1 Display and control data transfer Defined Undefined Undefined Defined Undefined Internal data (D85 to D124) Undefined Defined Undefined Internal data (D125 to D164) Undefined Defined Undefined Undefined System reset period Note: t1 ≥ 1 [ms] (Logic block power supply voltage VDD rise time) t2 ≥ 0 t3 ≥ 0 t4 ≥ 1 [ms] (Logic block power supply voltage VDD fall time) Figure 6 No. 7980-26/39 LC75857E, LC75857W 2. LC75857E/W internal block states during the reset period • CLOCK GENERATOR A reset is applied and either the OSC pin oscillator is stopped or external clock input is stopped. • COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. • KEY SCAN Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. • KEY BUFFER Reset is applied and all the key data is set to low. S1/P1 S2/P2 S3/P3 S5 S4/P4 S38 COM4/S39 COM3 COM2 COM1 • CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER Since serial data transfer is possible, these circuits are not reset. VLCD SEGMENT DRIVER & LATCH VLCD1 COMMON DRIVER VLCD2 VSS TEST CLOCK GENERATOR OSC CONTROL REGISTER DO SHIFT REGISTER CCB INTERFACE DI CL KEY BUFFER CE VDD KS6 KS5 KS4 S42/KS3 S41/KS2 S40/KS1 KEY SCAN KI5 KI4 KI3 KI2 KI1 VDET Blocks that are reset No. 7980-27/39 LC75857E, LC75857W 3. Pin states during the reset period pin State during reset S1/P1 to S4/P4 L *5 S5 to S38 L COM1 to COM3 L COM4/S39 L *6 KS1/S40 to KS3/S42 L *5 KS4 to KS6 L *7 OSC Z *8 DO H *9 Notes:*5. These output pins are forcibly set to the segment output function and held low. *6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is transferred, either the common output or the segment output function is selected. *7. This output pin is forcibly held fixed at the low level. *8. This I/O pin is forcibly set to the high-impedance state. *9. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin remains high during the reset period even if a key data read operation is performed. Notes on the OSC Pin Peripheral Circuit 1. RC oscillator mode (control data bit OC = 0) When RC oscillator mode is selected, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground. OSC Rosc Cosc 2. External clock mode (control data bit OC = 1) When external clock mode is selected, the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). The value of this resistor is determined by the allowable current for the external clock output pin. Verify that the external clock waveform is not deformed significantly. External clock output pin OSC Rg External oscillator Note: The external clock output pin allowable current must be greater than VDD/Rg. No. 7980-28/39 LC75857E, LC75857W Sample Application Circuit 1 1/3 duty, 1/2 bias (for use with normal panels) OSC *11 VDD +3V *10 VSS TEST VLCD +5V VLCD1 VLCD2 C ≥ 0.047 µF CE CL DI DO From the controller To the controller To the controller power supply C KKKKK I I I I I 54321 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 COM4/S39 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 126 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-29/39 LC75857E, LC75857W Sample Application Circuit 2 1/3 duty, 1/2 bias (for use with large panels) OSC *11 VDD +3V *10 VSS TEST 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VLCD +5V R C VLCD2 S38 COM4/S39 CE CL DI DO From the controller To the controller To the controller power supply R VLCD1 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 KKKKK I I I I I 54321 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 126 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-30/39 LC75857E, LC75857W Sample Application Circuit 3 1/3 duty, 1/3 bias (for use with normal panels) OSC *11 VDD +3V *10 VSS TEST VLCD +5V VLCD1 VLCD2 C ≥ 0.047 µF C CE CL DI DO From the controller To the controller To the controller power supply C KKKKK I I I I I 54321 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 COM4/S39 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 126 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-31/39 LC75857E, LC75857W Sample Application Circuit 4 1/3 duty, 1/3 bias (for use with large panels) OSC *11 VDD +3V *10 VSS TEST 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VLCD +5V R VLCD1 R C VLCD2 R CE CL DI DO From the controller To the controller To the controller power supply C KKKKK I I I I I 54321 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 COM4/S39 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 126 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-32/39 LC75857E, LC75857W Sample Application Circuit 5 1/4 duty, 1/2 bias (for use with normal panels) OSC *11 VDD +3V *10 VSS TEST VLCD +5V VLCD1 VLCD2 C ≥ 0.047 µF To the controller To the controller power supply C S38 CE CL DI DO From the controller COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 KKKKK I I I I I 54321 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 164 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-33/39 LC75857E, LC75857W Sample Application Circuit 6 1/4 duty, 1/2 bias (for use with large panels) +3V OSC *11 VDD *10 VSS TEST 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VLCD +5V R C R VLCD1 VLCD2 COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 CE CL DI DO From the controller To the controller To the controller power supply KKKKK I I I I I 54321 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 164 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-34/39 LC75857E, LC75857W Sample Application Circuit 7 1/4 duty, 1/3 bias (for use with normal panels) OSC *11 VDD +3V *10 VSS TEST VLCD +5V VLCD1 C ≥ 0.047 µF VLCD2 C To the controller To the controller power supply C S38 CE CL DI DO From the controller COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 KKKKK I I I I I 54321 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 164 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. No. 7980-35/39 LC75857E, LC75857W Sample Application Circuit 8 1/4 duty, 1/3 bias (for use with large panels) OSC *11 VDD +3V *10 COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 VSS TEST 10 kΩ ≥ R ≥ 1 kΩ C ≥ 0.047 µF VLCD +5V R VLCD1 R C VLCD2 R S38 CE CL DI DO From the controller To the controller To the controller power supply C KKKKK I I I I I 54321 SSS 444 210 / / / KKKKKK SSSSSS 654321 (S40) (S41) (S42) (general-purpose output ports) Used with the backlight controller or other circuit. LCD panel (up to 164 segments) (P1) (P2) (P3) (P4) *12 Key matrix (up to 30 keys) Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 kΩ) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 kΩ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. Notes on transferring display data from the controller When using the LC75857E/W in 1/3 duty, applications transfer the display data (D1 to D126) in three operations, and in 1/4 duty, they transfer the display data (D1 to D164) in four operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of the displayed image. No. 7980-36/39 LC75857E, LC75857W Notes on the controller key data read techniques 1. Timer based key data acquisition (1) Flowchart CE = [L] NO DO = [L] YES Key data read processing (2) Timing chart Key on Key on Key input Key scan t5 t6 t5 t5 CE t8 t8 t8 Key address DI t7 Key data read t7 t7 DO Key data read request t9 Controller determination (Key on) t9 Controller determination (Key on) t9 Controller determination (Key off) t9 Controller determination (Key on) Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time 1 1 T =——— = —— t8: Key data read time fosc fCK (3) Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. No. 7980-37/39 LC75857E, LC75857W 2. Interrupt based key data acquisition (1) Flowchart CE = [L] NO DO = [L] YES Key data read processing Wait for at least t10 CE = [L] NO DO = [H] YES Key OFF (2) Timing chart Key on Key on Key input Key scan t5 t5 t6 t5 CE t8 t8 t8 t8 Key address DI t7 Key data read t7 t7 t7 DO Key data read request t10 Controller determination (Key on) Controller determination (Key off) t10 Controller determination (Key on) Controller determination (Key on) t10 Controller determination (Key on) t10 Controller determination (Key off) t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time 1 1 T =——— = —— t8: Key data read time fosc fCK No. 7980-38/39 LC75857E, LC75857W (3) Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2004. Specifications and information herein are subject to change without notice. PS No. 7980-39/39