LCX037BLT
3.4cm (1.35 Type) Black-and-White LCD Panel
Description
The LCX037BLT is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with a built-in peripheral
driving circuit. Use of three LCX037BLT panels
provides a full-color representation. The striped
arrangement suitable for data display is capable of
displaying fine text and vertical lines.
The adoption of a new developed dot-line inverse
drive system, CMP (Chemical Mechanical Polish)
and OCS (On Chip Spacer) structures contribute to
high picture quality.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing and
control signals.
Features
• Number of active dots: 1,049,088 (1.35 Type, 3.4cm in diagonal)
• High optical transmittance: 16% (typ.)
• Dot-line inverse drive circuit
• OCS structure
• CMP (Chemical Mechanical Polish) structure
• High contrast ratio with normally white mode: 300 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• Up/down and/or right/left inverse display function
• Antidust glass package
Element Structure
• Dots: 1366 (H) × 768 (V) = 1,049,088
• Built-in peripheral driver using polycrystalline silicon super thin film transistors
Applications
• Liquid crystal data projectors
• Liquid crystal multimedia projectors
• Liquid crystal rear-projector TVs, etc.
∗ The company's name and product's name in this data sheet is a trademark or a registered trademark of each company.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00231-PS
COM
PAD
Input Signal
Level Shifter
Circuit
V Shift Register
V Shift Register
Up/Down and/or Right/Left
Inversion Control Circuit
SOUT
ENB
COML
VSS
HCK2
RGT
HVDD
SIG12
34
33 32 31 30 29 28 27 26
25
24
23 22 21 20
19
18 17 16 15 14 13 12 11 10 9
COM
PAD
–2–
7
PSIG1
VSSG
5
PSIG3
6
PSIG2
COMR
8
PSIG4
SIG2
SIG1
SIG3
SIG4
SIG5
SIG6
SIG7
SIG8
SIG9
SIG10
SIG11
HST
HCK1
VCK
VST
DWN
PST
VSS
VVDD
VCOM
LCX037BLT
Block Diagram
4
3
2
1
COM
PAD
H Shift Register
P Shift Register
COM
PAD
LCX037BLT
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
HVDD
• V driver supply voltage
VVDD
• Common pad voltage
COM, COML, COMR
• H shift register input pin voltage HST, HCK1, HCK2,
RGT
• V shift register input pin voltage VST, VCK, PST,
ENB, DWN
• Video signal input pin voltage
SIG1 to 12, PSIG1 to 4
∗
• Operating temperature
Topr
• Storage temperature
Tstg
∗ Panel temperature inside the antidust glass
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
–1.0 to +17
V
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Operating Conditions (VSS = 0V)
• Supply voltage
HVDD
15.5 ± 0.3V
VVDD
15.5 ± 0.3V
• Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal)
Vin
5.0 ± 0.5V
–3–
LCX037BLT
Pin Description
Pin
No.
Symbol
Description
1
VSSG
GND for V gate
2
PSIG1
Uniformity improvement signal (for black)
3
PSIG2
Uniformity improvement signal (for black)
4
PSIG3
Uniformity improvement signal (for gray)
5
PSIG4
Uniformity improvement signal (for gray)
6
COMR
Voltage for right CS (Storage capacity) electrode line
7
SIG1
Video signal 1 to panel
8
SIG2
Video signal 2 to panel
9
SIG3
Video signal 3 to panel
10
SIG4
Video signal 4 to panel
11
SIG5
Video signal 5 to panel
12
SIG6
Video signal 6 to panel
13
SIG7
Video signal 7 to panel
14
SIG8
Video signal 8 to panel
15
SIG9
Video signal 9 to panel
16
SIG10
Video signal 10 to panel
17
SIG11
Video signal 11 to panel
18
SIG12
Video signal 12 to panel
19
HVDD
Power supply for H driver
20
RGT
Drive direction pulse for H shift register (H: normal, L: reverse)
21
HST
Start pulse for H shift register drive
22
HCK1
Clock pulse for H shift register drive 1
23
HCK2
Clock pulse for H shift register drive 2
24
VSS
GND (H, V, drivers)
25
COML
Voltage for left CS (storage capacity) electrode line
26
ENB
Enable pulse for gate selection
27
VCK
Clock pulse for V shift register drive
28
VST
Start pulse for V shift register drive
29
DWN
Drive direction pulse for V shift register (H: normal, L: reverse)
30
PST
Start pulse for P shift register drive
31
VSS
GND (H, V, P drivers)
32
VVDD
Power supply for V, P drivers
33
SOUT
Test pin; leave this pin open.
34
VCOM
Common voltage of panel
–4–
LCX037BLT
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal inputs. All pins are connected to VSS with a
high resistor of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistance value: typ.)
(1) VSIG1 to VSIG12, PSIG
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Input
Level conversion circuit
(2-phase input)
1MΩ
250Ω
250Ω
1MΩ
Level conversion circuit
(2-phase input)
(3) RGT
HVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(4) HST
HVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(5) PST, VCK
VVDD
250Ω
250Ω
Input
Level conversion circuit
(single-phase input)
1MΩ
(6) VST, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Input
Level conversion circuit
(single-phase input)
1MΩ
(7) VCOM, COML, COMR
VVDD
Input
LC
1MΩ
(8) HVDD, VSSG, VVDD
Input
are all Vss.
1MΩ
–5–
LCX037BLT
Input Signals
1. Input signal voltage conditions (VSS = 0V)
Item
Symbol
Min.
Typ.
Max.
Unit
H shift register input voltage (Low)
HST, HCK1, HCK2, RGT (High)
VHIL
–0.5
0.0
0.4
V
VHIH
4.5
5.0
5.5
V
V shift register input voltage (Low)
VB1, VB2, BLK, VST,
VCK, PCG, ENB, DWN
(High)
VVIL
–0.5
0.0
0.4
V
VVIH
4.5
5.0
5.5
V
Video signal center voltage
VVC
7.4
7.5
7.6
V
Vsig1, 3, 5, 7, 9, 11
VVC ± 4.4
VVC ± 4.5
VVC ± 4.6
V
Vsig2, 4, 6, 8
VVC ± 4.4
VVC ± 4.5
VVC ± 4.6
V
Common voltage of panel∗2
Vcom
VVC – 0.8
VVC – 0.7
VVC – 0.6
V
Uniformity improvement signal
input voltage∗3
Vpsig1, 3
VVC ± 4.4
VVC ± 4.5
VVC ± 4.6
V
Vpsig2, 4
VVC ± 2.3
VVC ± 2.5
VVC ± 2.7
V
Video signal input range∗1
∗1
∗2
Input video signal shall be symmetrical to VVC.
The typical value of the common pad voltage may lower its suitable voltage according to the set
construction to use. In this case, use the voltage of which has maximum contrast as typical value.
When the typical value is lowered, the maximum and minimum values may lower.
–6–
LCX037BLT
∗3
Input video signal, and a uniformity improvement signal as shown phase like below. And the rise time trPsig
and the fall time tfPsig of Psig1 to 4 are suppressed within 400ns.
Phase relationship between video signal and uniformity improvement signal
H blanking period
H effective period
Vsig1, 3, 5, 7, 9, 11
Sig1, 3, 5, 7, 9, 11
Sig-Center
Time
Vpsig1, 4
Psig1
Psig4
Sig-Center
Psig4
Psig1
Time
Vsig2, 4, 6, 8, 10, 12
Sig-Center
Sig2, 4, 6, 8, 10, 12
Time
Vpsig2, 3
Psig2
Psig3
Psig3
Sig-Center
Psig2
Time
Level Conversion Circuit
The LCX037BLT has a built-in level conversion circuit in the clock input unit on the panel. The input signal
level increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
–7–
LCX037BLT
2. Clock timing conditions (Ta = 25°C)
Item
HST
HCK
VST
VCK
ENB
PST
∗4
∗5
(fHckn = 6.67MHz, fVck = 25.6kHz, fv = 60Hz)
Symbol
Min.
Typ.
Max.
Hst rise time
trHst
—
—
30
Hst fall time
tfHst
—
—
30
Hst data set-up time
tdHst
–10
0
10
Hst data hold time
thHst
65
75
85
Hckn rise time∗4
trHckn
—
—
30
tfHckn
—
—
30
Hck1 fall to Hck2 rise time
to1Hck
–15
0
15
Hck1 rise to Hck2 fall time
to2Hck
–15
0
15
Vst rise time
trVst
—
—
100
Vst fall time
tfVst
—
—
100
Vst data set-up time
tdVst
5
10
15
Vst data hold time
thVst
5
10
15
Vck rise time
trVck
—
—
100
Vck fall time
tfVck
—
—
100
Enb rise time
trEnb
—
—
100
Enb fall time
tfEnb
—
—
100
Horizontal video period completed
to Enb fall time
tdEnb
800∗5
1000
1200
Enb width
twEnb
900
1000
1100
Vck rise/fall to Enb rise time
toEnb
300
400
500
Enb rise to Pst rise time
toPst
390
400
410
Pst rise time
trPst
—
—
30
Pst fall time
tfPst
—
—
30
Pst data set-up time
tdPst
–10
0
10
Pst data hold time
thPst
65
75
85
Pst rise to Hst rise time
toHst
—
4
—
Hckn fall
time∗4
Unit
ns
µs
ns
×4 cycles of Hck
Hckn means Hck1 and Hck2.
The minimum value of tdEnb is 800ns. When H-BLK has a long period and has some time to spare, take
more time prior to other value.
–8–
LCX037BLT
<Horizontal Shift Register Driving Waveform>
Item
Hst rise time
Symbol
Waveform
90%
trHst
Hst
Hst fall time
HST
tfHst
tdHst
90%
10%
10%
trHst
∗6
Hst data set-up time
Conditions
tfHst
50%
50%
Hst
Hck1
Hst data hold time
50%
50%
thHst
tdHst
Hckn rise time∗4
∗4
Hckn fall time∗4
tfHckn
Hck1 fall to Hck2 rise time
to1Hck
10%
trHckn
∗6
HCK
90%
10%
Hckn
50%
to2Hck
50%
50%
Hck2
to2Hck
∗6
tfHckn
Hck1
50%
Hck1 rise to Hck2 fall time
to1Hck
Definitions: The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
–9–
• Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
thHst
90%
trHckn
• Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
• Hckn∗4
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
LCX037BLT
<Vertical Shift Register Driving Waveform>
Item
Vst rise time
Symbol
Waveform
90%
trVst
Vst
Vst fall time
VST
Conditions
90%
10%
tfVst
10%
trVst
tfVst
∗6
Vst data set-up time
50%
tdVst
50%
Vst
50%
50%
Vck
Vst data hold time
Vck rise time
thVst
tdVst
thVst
90%
90%
trVck
10%
Vck
VCK
Vck fall time
tfVck
Enb rise time
trEnb
10%
trVckn
90%
tfVckn
10%
10%
90%
Enb
Enb fall time
tfEnb
Horizontal video period
completed to Enb fall time
tdEnb
ENB
tfEnb
trEnb
∗6
H video
period
H blanking period
twEnb
Enb width
twEnb
50%
Enb
50%
tdEnb
Vck rise/fall to Enb fall
time
toEnb
Vck
50%
toEnb
Pst
Enb rise to Pst rise time
toPst
50%
toPst
– 10 –
LCX037BLT
Item
Pst rise time
Symbol
Waveform
trPst
90%
Pst
Pst fall time
tfPst
Pst data set-up time
tdPst
Conditions
90%
10%
10%
trPst
tfPst
50%
Pst
50%
50%
50%
HCKn
PST
Pst data set-up time
thPst
tdPst
thPst
∗6
Pst
Pst rise to Hst rise time
toHst
50%
toPst
Hst
Hckn
50%
1
– 11 –
2
3
4
LCX037BLT
Electrical Characteristics (Ta = 25°C, HVDD = 15.5V, VVDD = 15.5V)
1. Horizontal drivers
Item
Input pin capacitance
Input pin current
Symbol
Min.
Typ.
Max.
Unit
HCKn
CHckn
—
15
20
pF
HST
CHst
—
15
20
pF
Condition
HCK1
–1000 –500
—
µA
HCK1 = GND
HCK2
–1000 –500
—
µA
HCK2 = GND
HST
–500
–170
—
µA
HST = GND
RGT
–150
–40
—
µA
RGT = GND
Video signal input pin capacitance
Csig
—
180
250
pF
Current consumption
IH
—
15
25
mA
HCKn: HCK1, HCK2 (6.67MHz)
Min.
Typ.
Max.
Unit
Condition
2. Vertical drivers
Item
Input pin capacitance
Input pin current
Symbol
VCK
CVck
—
15
20
pF
VST, PST
CVst
—
15
20
pF
–500
–150
—
µA
VCK = GND, PST = GND
–150
–35
—
µA
VST, ENB, DWN = GND
—
20
30
mA
VCK: (25.6kHz)
Min.
Typ.
Max.
Unit
—
550
1000
mW
Symbol
Min.
Typ.
Max.
Unit
Rpin
0.4
1
—
MΩ
Min.
Typ.
Max.
Unit
—
0.5
5.0
nF
VCK, PST
VST, ENB, DWN
Current consumption
IV
3. Total power consumption of the panel
Item
Symbol
Total power consumption of the panel PWR
4. Pin input resistance
Item
Pin – VSS input resistance
5. Uniformity improvement signal
Item
Symbol
Input pin capacitance for uniformity CPSIG1
improvement signal
to 4
– 12 –
LCX037BLT
Electro-optical Characteristics
Item
Symbol Measurement method Min.
Typ.
Max.
Unit
Contrast ratio
25°C
CR
1
200
300
—
—
Optical transmittance
25°C
T
2
13
16
—
%
RV90-25
0.9
1.3
1.6
GV90-25
1.0
1.4
1.7
BV90-25
1.2
1.6
1.9
RV90-60
0.9
1.3
1.6
GV90-60
1.0
1.4
1.7
BV90-60
1.1
1.5
1.8
RV50-25
1.3
1.7
2.0
GV50-25
1.4
1.8
2.1
1.5
1.9
2.2
RV50-60
1.2
1.6
1.9
GV50-60
1.3
1.7
2.0
BV50-60
1.4
1.8
2.1
RV10-25
1.7
2.1
2.4
GV10-25
1.8
2.2
2.5
BV10-25
1.9
2.3
2.6
RV10-60
1.7
2.1
2.4
GV10-60
1.8
2.2
2.5
BV10-60
1.8
2.2
2.5
0°C
ton0
—
24.0
80.0
25°C
ton25
—
9.0
40.0
0°C
toff0
—
99.0
200.0
25°C
toff25
—
27.0
70.0
Flicker
60°C
F
5
—
–82.0 –40.0
Image retention time
25°C
YT60
6
—
0
—
s
Cross talk
25°C
CTK
7
—
—
5
%
25°C
V90
60°C
25°C
V-T
characteristics
BV50-25
V50
60°C
25°C
V10
60°C
ON time
Response time
OFF time
3
4
V
ms
dB
Reflection Preventive Processing
When a phase substrate which rotates the polarization axis is used to adjust to the polarization direction of a
polarization screen or prism, use a phase substrate with reflection preventive processing on the surface. This
prevents characteristic deterioration caused by luminous reflection.
– 13 –
LCX037BLT
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.5V, VVDD = 15.5V
VVC = 7.5V, Vcom = 6.8V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Two types of measurement systems are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.5 ± VAC [V]
(VAC = signal amplitude)
• Measurement system I
Approx. 2000mm
Screen
Luminance
Meter
Measurement
Equipment
LCD Projector
Screen: Made by Sony (VPS-120FH: Gain 2.8, Glass Beaded Type) or equivalent
Projection lens: Focal distance 80mm, F1.9
Light source: 155W metal Haloid arc lamp (Color temperature 7500K ± 500)
(×24, Sensor area: 7mmφ)
Polarizer: Side of incidence-Nitto Denko’s EG-1224DU or Polatechno’s SKN-18242T
Side of output light-Polatechno's SHC-128 or equivalent
• Measurement system II
Optical fiber
Light receptor lens
Drive Circuit
Light Detector
Measurement
Equipment
LCD panel
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
CR =
L (White)
... (1)
L (Black)
L (White): Surface luminance of the center of the screen at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the center of the screen at VAC = 5.5V.
Both luminosities are measured by System I.
– 14 –
LCX037BLT
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
T=
White luminance
Luminance of light source
× 100 [%] ... (2)
3. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II by inputting the same signal
amplitude VAC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%,
and 10% of transmittance respectively.
Transmittance [%]
"White luminance" means the maximum luminance on the screen at the input signal amplitude VAC = 0.5V
on Measurement System I.
90
50
10
V90
V50 V10
VAC – Signal amplitude [V]
4. Response Time
Response time ton and toff are defined by
formulas (5) and (6) respectively.
ton = t1 – tON ...(5)
toff = t2 – tOFF ...(6)
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V
0.5V
7.0V
0V
Optical transmittance output waveform
100%
90%
10%
0%
tON
t1
ton
– 15 –
tOFF
t2
toff
LCX037BLT
5. Flicker
Flicker (F) is given by formula (7). DC and AC (SXGA: 30Hz, rms) components of the panel output signal
for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in System II.
F [dB] = 20log
∗ Each input signal voltage for gray raster mode
is given by Vsig = 7.0 ± V50 [V]
where: V50 is the signal amplitude which gives
50% of transmittance in V-T characteristics.
component
{ AC
} ...(7)
DC component
6. Image Retention Time
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.5 ± VAC (VAC: 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time till the residual image becomes indistinct.
∗ Monoscope signal conditions:
Vsig = 7.5 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.8V
Black level
5.5V
White level
2.0V
7.5V
2.0V
5.5V
0V
Vsig waveform
7. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and
Wi (i = 1 to 4) around a black window (Vsig = 4.5 V/1V).
Cross talk value CTK =
W2
W1 W1'
W2'
W4
W4'
W3 W3'
– 16 –
Wi' – Wi
× 100 [%]
Wi
LCX037BLT
Viewing angle characteristics (Typical Value)
90
AA
AAAA
AAAA
AA
CR = 5
10
Phi
20
50
100
180
150
0
250
10
200
30
50
70
Theta
270
θ0°
Z
θ
φ90°
Marking
φ
φ180°
X
φ270°
– 17 –
Y
φ0°
Measurement method
LCX037BLT
Optical transmittance of LCD panel (Typical Value)
30
Trans. [%]
20
10
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 18 –
6 dots
6 dots
1 dot
: Pixel of transistor open and close at the 767th gate
:
2
767
Up scan: For video 2 ,
: Pixel of transistor open and close at the 2nd gate
1
2
1
D1
4
1
D1
5
768
768
767
768
767
2
1
D1
1
(Lower)
1366 dots
1
6
768
767
2
1
D1
2
768
767
2
1
D1
3
Gate SW
768
767
2
1
D1
4
6 , input signal prior one line from video 1 ,
767
767
2
1
D1
5
6
6 .
1 dots
5 .
4 ,
3 ,
, input signal prior one line from video 2 ,
768
767
Active
2 area
767
1
D1
3
Gate SW
3 , 5
4 ,
<Signal input>
Down scan: For video 1 ,
: Pixel of transistor open and close at the D1st gate
: Pixel of transistor open and close at the 1st gate
D1
768
Gate: 768th
2
Gate: 2nd
767
1
2
Gate: 1st
1
D1
Video
Gate: D1st
Photo-Shielding
Gate SW
(Upper)
6 dots
Gate SW
6 dots
Gate SW
(Right)
2 dots
768 dots
(Left)
Gate SW
Gate: 767th
– 19 –
2 dots
1. Dot Arrangement
The dots are arranged in a stripe. The shaded area is used for the dark border around the display.
(TFT substrate view from com pad)
LCX037BLT
LCX037BLT
2. LCD Panel Operations
[Description of basic operations]
• To perform dot-line inverse drive, the pixel arrangement of the same gate is as shown in the diagram.
Therefore, the input signal matched to respective orrangement is requied for input signals SIG1 to 12.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 768 gate lines sequentially in a single horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1366 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs) turn
on to apply a video signal to the dot. The same procedures lead to the entire 1366 × 768 dots to display a
picture in a single vertical scanning period.
– 20 –
LCX037BLT
This LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
These modes are controlled by two signals (RGT and DWN). The right/left and/or up/down setting modes are
shown below.
RGT
Mode
DWN
Mode
H
Right scan
H
Down scan
L
Left scan
L
Up scan
Right/left and/or up/down mean the direction when the Pin 1 marking is located at the right side with the pin
block upside.
To locate the active area in the center of the panel in each mode, polarity of the start pulse and clock phase for
the H system must be varied. The phase relationship between the start pulse and the clock for each mode is
shown below.
Vertical direction display period (DWN = H)
Gate name
VST
VCK
D1
1
2
3
4
765 766 767 768
V effective display period 768H
Vertical direction display period (DWN = L)
Gate name
VST
VCK
768 767 766 765
4
3
2
1
D1
V effective display period 768H
Horizontal direction display period (RGT = H)
PST
HST
HCK1
1
2
3
4
225 226 227 228 D1 D2
HCK2
H display period 228V
Horizontal direction display period (RGT = L)
PST
HST
HCK1
228 227 226 225
HCK2
4
3
2
1
D1
H display period 228V
– 21 –
D2
LCX037BLT
3. 12-dot Simultaneous Sampling
The horizontal shift register samples signals VSIG1 to VSIG6, VSIG7 to VSIG12 simultaneously. This
requires phase matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from
deteriorating. Thus, phase matching between each signal is required using an external signal delaying
circuit before applying the video signal to the LCD panel.
VSIG1
S/H
CK1
VSIG2
S/H
CK2
VSIG3
S/H
CK3
VSIG4
S/H
CK4
VSIG5
S/H
S/H
7
VSIG1
S/H
8
VSIG2
S/H
9
VSIG3
S/H
10 VSIG4
S/H
11 VSIG5
S/H
12 VSIG6
CK5
VSIG6
CK6
VSIG7
S/H
CK7
VSIG8
S/H
CK8
VSIG9
S/H
CK9
VSIG10
S/H
S/H
13 VSIG7
S/H
14 VSIG8
S/H
15 VSIG9
S/H
16 VSIG10
S/H
17 VSIG11
S/H
18 VSIG12
CK10
S/H
VSIG11
CK11
VSIG12
CK12
– 22 –
LCX037BLT
The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following
phase relationship diagram indicates the phase setting for right scan (RGT = High). For left scan (RGT = Low),
the phase settings for signals VSIG1 to VSIG12 are exactly reversed.
LCX037BLT
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK1
CK2
CK3
CK4
CK5
CK6
CK7
CK8
CK9
CK10
CK11
CK12
Display System Block Diagram
An example of display system is shown below.
D/A
S/H Driver
CXA3197R
CXA3512R
6
LCX037
Digital
Signal
Driver
6
CXA3197R
CXA3512R
CXA3197R
CXA3512R
R-IN
16
Selection-type
Delay Line
G-IN
6
16
B-IN
16
VSYNC
CXD2467Q
CXD3504R
60
LCX037
60
6
CXA3197R
CXA3512R
CXA3197R
CXA3512R
HSYNC
6
LCX037
1/2
MCK
X'tal
– 23 –
Timing Pulse
CXA3512R
FRP, PRG, ENB
CXA3197R
6
LCX037BLT
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (glass panel) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the glass panel.
c) Do not touch the glass panel surface. The surface is easily scratched. When cleaning, use a cleanroom wiper with isopropyl alcohol. Be careful not to leave a stain on the surface.
d) Use ionized air to blow dust off the glass panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel.
c) Do not twist or bend the panel or panel frame.
d) Keep the panel away from heat sources.
e) Do not dampen the panel with water or other solvents.
f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel
damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 3kg · cm or less.
i) Use appropriate filter to protect a panel.
j) Do not pressure the portion other than mounting hole (cover).
– 24 –
LCX037BLT
Package Outline
Unit: mm
4.9 ± 0.1
0.3 ± 0.05
2.2 ± 0.1
17.5 ± 0.05
Thickness of the connector
1
2.5
4-R
Incident light
Polarizing Axis
Active Area
3
2
34.0 ± 0.1
39.0 ± 0.15
101.5 ± 1.4
3-φ2.3 ± 0.05
(62.6)
4
5
6
7
Incident
light
Output light
Polarizing Axis
9
1
P 0.5 ± 0.02 × 33 = 16.5 ± 0.03
0.5 ± 0.1
0.35 ± 0.03
4.0 ± 0.3
30.0 ± 0.1
42.0 ± 0.15
No
21.0 ± 0.15
6.0 ± 0.1
0.5 ± 0.15
(30.05)
φ2.1 ± 0.05
18.0 ± 0.15
2.5 ± 0.1
(16.90)
2.1 ± 0.05
8
PIN34
PIN1
Description
F P C
2
Molding material
3
Outside frame
4
Reinforcing board
5 Reinforcing material
electrode (enlarged)
The rotation angle of the active area relative to H and V is ± 1°.
6
Glass 1
7
Glass 2
8
Cover 1
9
Cover 2
weight 13.7g
– 25 –