June 2004 LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer General Description Features The LM2501 device is a Serializer/Deserializer that adapts existing video busses to Mobile Pixel Link (MPL). MPL is intended to replace wide LVCMOS video interfaces inside portable electronics equipment benefiting their cost, size, EMI and power consumption. By using the LM2501 SERDES chipset, the interconnect is reduced from 12 active signals to only 3 active signals providing a 75% reduction. This eases interconect and flex design, size and cost. Contained in a 24 lead Ultra Thin CSP Package, the Serializer resides beside the video source (camera) and translates the parallel bus from LVCMOS levels to serial MPL levels for transmission over a flex cable to the Deserializer located by the respective destination Video Input Port. An extra clock transport is provided to deliver a clock signal to the target. For example, from the main board to the flip board where the camera module is located. Transmission of the clock also benefits from MPL’s low power transmission and low EMI. The Power_Down (PD*) input controls the power state of the MPL interface. When PD* is asserted, the MD, MC and WC signals are powered down to save current and reduce power dissipation. n n n n n n n n n 160 Mbps Raw Throughput MPL-0 Meets MPL Physical Layer Specification Configurable as a Serializer or Deserializer Complete LVCMOS to MPL Translation Serializes 8-bit Camera Interface — 8-bit color data — plus VSYNC and HSYNC bits Link power down mode reduces quiescent power under ∼ 10 µA (actual TBD) 1.7V–3.1V and 2.9-3.1V Supply Voltage Interfaces to 1.8V–3.0V Logic Offered in a small 24L UCSP Package — 3.5 mm X 4.5 mm — 0.6 mm Max Height System Benefits n n n n n Reduced Wire Interface Low Power Low EMI Extra Clock Transport Intrinsic Level Translation Typical Application Diagram 20091601 Ordering Information NSID Package Type LM2501SL 24-Lead Ultra Thin CSP 3.5 X 4.5 X 0.6 mm Package ID SLE24A I2C ® is a registered trademark of Phillips Corporation. © 2004 National Semiconductor Corporation DS200916 www.national.com LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer ADVANCE INFORMATION LM2501 Connection Diagram 20091612 TOP VIEW General Block Diagrams: Serializer and Deserializer 20091613 www.national.com 2 LM2501 Pin Description Pin Name No. of Pins I/O, Type Description MPL SERIAL BUS PINS MD 1 IO, MPL MPL Data line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. MC 1 IO, MPL MPL Clock line. Serializer is a Line Driver. Deserializer is a Receiver. Configured by the Mode[1:0] pins. MG 1 Ground See VSSA below. CONFIGURATION/PARALLEL BUS PINS Mode[1:0] 2 I, LVCMOS Mode Configuration Input pins: Mode[1:0], NOTE - Applies to REV F/G Samples only. 00 : Deserializer 01 : Serializer with PD* input 10 : Reserved 11 : Reserved PD* 1 I, LVCMOS Power_Down. Input pin. Active Low. When PD* is Low the device is in the sleep state. D0–D7 8 IO, LVCMOS VS 1 IO, LVCMOS VSYNC – Serializer Input, Deserializer Output HS 1 IO, LVCMOS HSYNC – Serializer Input, Deserializer Output PCLK 1 IO, LVCMOS Pixel Clock. Serializer Input, Deserializer Output WCLKIO 1 IO, LVCMOS Extra Clock Input for WhisperClock Link – Deserializer Input. Serializer Output. WC 1 IO, MPL 8-bit Bi-directional Data Bus – Serializer Input, Deserializer Output WHISPER CLOCK Extra WhisperClock MPL signal – Serializer is an MPL input signal, Deserializer is an MPL output signal. POWER/GROUND PINS VDDA 1 Power Power Supply Pin for the MPL Interface. 3.0V ± 3% VSSA 1 Ground Ground Pin for the MPL Interface, also known as MG (MPL Ground) VDD 1 Power Power Supply Pin for the digital core and Serializer PLL. 3.0V ± 3% Ground Pin for the digital core and Serializer PLL. VSS 1 Ground VDDIO 1 Power Power Supply Pin for the parallel interface. 1.7V to 3.1V VSSIO 1 Ground Ground Pin for the parallel interface. Notes: I = Input, O = Output, IO = Input/Output Do NOT float unused inputs. ES Revision notes Rev D/E Sampled on MPL200EVK Use prior datasheet edition Rev F S/D* and TM pins changed to Mode[1:0] Use this datasheet edition Rev G MPL RX enhancements 3 www.national.com LM2501 Absolute Maximum Ratings (Note 1) Maximum Package Power Dissipation Capacity at 25˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDDA) −0.3V to +TBDV Supply Voltage (VDD) −0.3V to +TBDV Supply Voltage (VDDIO) −0.3V to +TBDV LVCMOS Input/Output Voltage −0.3V to (VDDIO +0.3V) MPL Input/Output Voltage 24L UCSP Package +150˚C Storage Temperature −65˚C to +150˚C Lead Temperature Soldering, 4 Seconds TBD mW/˚C Recommended Operating Conditions Min Typ Max Units Supply Voltage VDDA to VSSA and VDD to VSS 2.9 VDDIO to VSSIO 1.7 3.1 V 4 16 MHz 28 MHz 70 ˚C PLK Clock Frequency +260˚C ESD Ratings: ≥ ± 2 kV HBM, 1.5 kΩ, 100pF TBD W Derate TBD Package above 25˚C TBD Junction Temperature ≥ ± 200V EIAJ, 0Ω, 200 pF WC Clock Frequency 4 Ambient Temperature 0 3.0 3.1 25 V Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units 4.8 IB 5.0 IB 5.3 IB µA MPL IOLL Logic Low Current IOMS Mid Scale Current IOHL Logic High Current IB Current Bias 3.0 IB 0.8 IB 1.0 IB µA 1.2 IB 150 µA µA LVCMOS (1.7V to 3.1V) VIH Input Voltage High Level VDDIO +0.3 0.7 VDDIO V VIL Input Voltage Low Level 0.3 VDDIO V IIN Input Current (includes IOZ) −5 0 +5 µA IIH Input Current High Level −1 0 +1 µA IIL Input Current Low Level −1 0 +1 µA VOH Output Voltage High Level IOH = −2 mA VOL Output Voltage Low Level IOL = 2 mA IOS Output Short Circuit Current VOUT = 0V −0.3 0.8 VDDIO V 0.2 VDDIO TBD V mA SUPPLY CURRENT ICC ICCZ Total Supply Current — Enabled Supply Current — Disable www.national.com PCLK = 16MHz WC = 28MHz MD = 0101-1010 pattern CL = 15 pF Serializer TBD TBD µA TBD TBD µA Power_Down Mode PD* = L 1 10 µA PD* = L 1 10 µA Deserializer 4 LM2501 Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units PARALLEL BUS TIMING tSET Set Time - Data to Clock tHOLD Hold Time - Clock to Data Inputs Figure 2 TBD ns TBD ns ns tRISE Rise Time tFALL Fall Time PCLOW PCLK Low 50 PCHIGH PCLK High 50 tDVBC Data Valid before Clock tDVAC Data Valid after Clock Outputs, CL = 15 pF ns Figure 2 % % TBD ns TBD ns SERIAL BUS TIMING tDVBC Figure 1 tDVAC POWER UP TIMING (see Figures 5, 6) t1 WC Start Up Delay t2 WC Low Initialization Low State t3 WC Pulse Width High t4 WC Low State t5 WCIN to WCOUT Latency (SER) t6 TBD t7 SER PLL Lock Time t8 MC Low Initialization Low State 11 12 13 MCCYC t9 MC Pulse Width High 11 12 13 MCCYC t10 MC Low State 11 12 13 MCCYC t11 SER Latency TBD MCCYC t12 DES Latency TBD MCCYC Figure 5 Planned Rev G ES test Chip will double WC cyc counts on T1 to T4 (SER) parameters to support higher WC rates. 100 WCCYC 11 12 13 WCCYC 11 12 13 WCCYC 11 12 13 WCCYC 6 7 8 WCCYC Figure 6 9 WCCYC 4,096 MCCYC POWER OFF TIMING tPAZ Disable Time to Power Off µs tPZA Enable Time from Power Off µs 5 www.national.com LM2501 Input Timing Requirements Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units 28 MHz 55 % 6 ns 4 16 MHz 62.5 250 ns 55 % 6 ns REFERENCE CLOCK (WCLKIN) fWC Clock Frequency 4 WCDC Clock Duty Cycle 45 tT Clock Transition Times (Rise or Fall, 10%–90%) 1 50 PIXEL CLOCK (PCLK) fPCLK Clock Frequency tCP Clock Period CLKDC Clock Duty Cycle 45 tT Clock transition Time 1 50 Note 1: “Absolute Maximum Ratings“ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VDD = VDDA = 3.0V and VDDIO = 2.7V and TA = 25˚C. Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified. Timing Diagrams 20091610 FIGURE 1. Serial Data Valid 20091611 FIGURE 2. Parallel Set, Hold and Data Valid www.national.com 6 LM2501 Application Information Typical application connections for the LM2501 are shown below. 20091614 FIGURE 3. Camera Application The application shown in Figure 3 illustrates a connection between an Image sensor and a host utilizing an MPL-0 link. . 7 www.national.com LM2501 tion is provided internal to the MPL receiver. The MPL interface is designed to be used with common 50 Ω lines using standard materials and connectors. Lines may be microstrip or stripline construction. Total length of the interconnect is expected to be less than 0.3 meters. This device is meets the requirements of the MPL-0 Standard (PHY Layer only). Functional Description SERIAL BUS OPERATION Bus Overview The MPL bus is a simple 2-signal line interface that is intended to replace wide low voltage CMOS video busses inside handheld portable devices. The MPL physical layer is purpose-built for an extremely low power and low EMI data transmission while requiring the fewest number of signal lines. No external line components are required, as termina- SERIAL BUS TIMING Data valid is relative to both edges as shown in Figure 4. Data valid is specified as: Data Valid before Clock, Data Valid after Clock, (Note relative to both edges). 20091602 FIGURE 4. Master-to-Slave Timing (MC, MDm) SERIAL BUS PHASES There are three bus phases on the MPL serial bus. These are determined by the state of the MC and MD lines. Two of the bus phases have options. The MPL bus phases are shown in Table 1. TABLE 1. MPL Bus Phases Name WC State OFF (O) Initialization (I) Active (A) MC State MD State Phase Description Pre-Phase Post-Phase 0 0 0 Bus is Powered-Off na I (WC) WC A 0 0 WC Start Up O I (MC) MC/MD A A 0 MPL Start Up I (WC) A A A X Data Out (Write) I (MC) A or O Notes on Line State: 0 = no current (off), L = Logic Low, H = Logic High, X = Low or High, A — Active Clock www.national.com 8 ing their PD* inputs. The DES will then initialize the SER via the WC signal as shown inFigure 5. The DES waits 7 WC cycles before its WCLKout is active. Note, there is no phase or frequency relationship between WC and MC. (Continued) SERIAL BUS POWER-UP In the sleep state, WC, MC and MD are turned off with zero current flowing. Both devices need to be enabled by assert- 20091603 FIGURE 5. Bus Power Up Timing — WC 9 www.national.com LM2501 Functional Description LM2501 Functional Description (Continued) 20091604 FIGURE 6. Bus Power Up Timing — MC/MD In Figure 6, the Serializer timing is shown. For the part to establish lock, WCLKIO(out) must be active, and a valid PCLK applied. After lock is obtained, the MC and MD lines are initialized and then active transmission occurs. Table Switching Characteristics lists the timing parameters of Figures 5, 6. SERIAL BUS POWER-OFF In the power-off state, WC, MD and MC are turned off with zero current flowing. This is considered the Sleep state (Power-off) and the transition off may occur after the last data bit time or at any time afterwards from an Idle phase as shown in Figure 7. 20091605 FIGURE 7. Bus Power Down Timing www.national.com 10 rising edge of the MC line. PCLK is required and must be free-running. Data may be raw Bayer or BT656 color information. Data is strobed on the rising-edge on the input to the Serializer. Data is sent LSB first (D0). MPL provides the data transport path, control of the Camera device is provided by an I2C control bus. (Continued) CAMERA INTERFACE The Camera Interface provides serialization of color and control bits. The interface provides data transport in a single direction. Byte alignment is provided by the intrinsic first 20091606 FIGURE 8. Camera Mode Serial Interface 20091607 FIGURE 9. Parallel Bus Timing 11 www.national.com LM2501 Functional Description LM2501 PHASE-LOCKED LOOP Features and Operation When the device is configured as a Serializer, a PLL is provided to generate the serial link clock. The Phase-locked loop system generates the serial data clock at five times the input clock. The PLL operates with an input clock between 4 MHz and 16 MHz. The Deserializer does not utilize the PLL and its PLL is powered down. POWER DOWN/OFF The device may be powered by its PD* pin. A Low on this pin will power down the entire device. TABLE 2. Power Down Output States RESET Mode Pin Type Output State in Power Down SER WCLKIO LVCMOS LOW SER MC MPL OFF SER MD MPL OFF PD* should be held Low until the power supply has powered up and is stable. The PD* should then be de-asserted to generate a RESET and start up. Stopping the WCLKIO or the PCLK will not RESET the part. A power cycle or PD* cycle is requested to generate a RESET event. DES D[0:7] LVCMOS LOW SERIALIZER/DESERIALIZER SELECTION DES V, H LVCMOS LOW DES PCLK LVCMOS LOW DES WC MPL OFF The Mode[1:0] pins are used to configure the device as either a Serializer or Deserializer and other configuration options. WHISPERCLOCK An additional clock signal is sent from the Deserializer to the Serializer. This can be used to pass a clock reference (4 MHz to 28 MHz) up to the Camera device from the host. This link is independent of the Serial data path (opposite direction). See also Figure 5. The SER can only start up, if the WCLKIO(ser-out) has been active. UN-USED/OPEN INPUTS Un-used control/inputs pins must be driven to their appropriate logic states to set up the desired operating modes. UN-USED OUTPUTS Unused outputs should be left open to minimize power dissipation. POWERING UP The LM2501 should be powered up with all power supplies at the same time, alternately VDDIO may lag VDD and VDDA. Do not power up with VDDIO before VDD and VDDA. 20091608 FIGURE 10. Sleep to Active www.national.com 12 clock signal. Seven cycles later, the Serializer’s PLL will begin to lock if PCLK is present. When the Deserializer’s PD* signal is asserted, the WC signal is turned off. (Continued) When the Deserializer’s PD* signal is de-asserted, the WC output will power up and initialize the serializer and start transmitting the clock reference. Once the Serializer received the clock, it waits seven cycles, and then outputs the 20091609 FIGURE 11. Active to Sleep MISC. Definitions: Signals & Nomenclature: MD = MPL Data Signal, subscript denotes source, m = master, s = slave MC = MPL Clock Signal WC = MPL WhisperClock Signal *= Active Low Signal Bus States: Logic Low — 5Idata flowing from the Receiver to the Driver Logic High — Idata flowing from the Receiver to the Driver Power Off — No Current flowing in the interconnect 13 www.national.com LM2501 Features and Operation LM2501 Mobile Pixel Link (MPL) Camera Interface Serializer and Deserializer Physical Dimensions inches (millimeters) unless otherwise noted Order Number LM2501SL NS Package Number SLE24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. 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