MICROCIRCUIT DATA SHEET Original Creation Date: 08/03/95 Last Update Date: 11/23/98 Last Major Revision Date: 10/28/98 MNLM6161-X REV 2A1 HIGH SPEED OPERATIONAL AMPLIFIER General Description The LM6161 high-speed amplifier exhibits an excellent speed-power product in delivering 300 V/uS and 50 MHz unity gain stability with only 5 mA of supply current. Further, power savings and application convenience are possible by taking advantage of the wide dynamic range in operating supply voltage which extends all the way down to +5V. This amplifier is built with National's VIP[TM] (Vertically Integrated PNP) process which provides fast PNP transistors that are true complements to the already fast NPN devices. This advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation. Industry Part Number NS Part Numbers LM6161 LM6161E/883* LM6161J-QMLV ** LM6161J/883 *** LM6161W-SMD **** LM6161W/883 LM6161WG-QMLV ***** LM6161WG/883 ****** Prime Die LM6161B Controlling Document See Features Page Processing Subgrp Description MIL-STD-883, Method 5004 1 2 3 4 5 6 7 8A 8B 9 10 11 Quality Conformance Inspection MIL-STD-883, Method 5005 1 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at Temp ( oC) +25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Features - High slew rate 300V/uS High unity gain freq 50MHz Low supply current 5mA Fast settling 120nS to 0.1% Low differential gain <0.1% Low differential phase 0.1 degrees Wide supply range 4.75V to 32V Stable with unlimited capacitive load Well behaved; easy to apply SMD : 5962-89621012A*,VPA**,PA***,HA****,VXA*****,XA****** Applications - Video amplifier High-frequency filter Wide-bandwidth signal conditioning Radar Sonar 2 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 (Absolute Maximum Ratings) (Note 1) Supply Voltage (V+ - V-) Differential Input Voltage Range (Note 4) 36V +8V Common-Mode Voltage Range (Note 6) (V+ - 0.7V) to (V- - 7V) Output Short Circuit to Gnd (Note 3) Continuous Power Dissipation (Note 2) 400mW Soldering Information (Soldering, 10 seconds) Storage Temperature Range 260 C -65 C to +150 C Maximum Junction Temperature 150 C Thermal Resistance ThetaJA LCC CERDIP CERPAK CERAMIC SOIC (Still Air) (500LF/Min Air (Still Air) (500LF/Min Air (Still Air) (500LF/Min Air (Still Air) (500LF/Min Air flow) flow) flow) flow) ThetaJC LCC CERDIP CERPAK CERAMIC SOIC ESD Tolerance (Note 4, 5) 90 61 113 51 228 140 228 140 C/W C/W C/W C/W C/W C/W C/W C/W 20 21 21 21 C/W C/W C/W C/W +500V Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. The maximum power dissipation must be derated at elevated temperatures and is dictated by Tjmax (maximum junction temperature), ThetaJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is Pdmax = (Tjmax - TA)/ThetaJA or the number given in the Absolute Maximum Ratings, whichever is lower. Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 C. In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exceeding the maximum differential input voltage results in reverse breakdown of the base-emitter junction of one of the input transistors and probable degradation of the input parameters (especially Vio, Iio and Noise). The average voltage that the weakest pin combinations (those involving Pin 2 or Pin 3) can withstand and still conform to the datasheet limits. The test circuit used consists of the human body model of 100pF in series with 1500 Ohms. The voltage between V+ and either input pin must not exceed 36V. 3 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Recommended Operating Conditions (Note 1) Temperature Range -55 C < TA < +125 C Supply Voltage Range 4.75V to 32V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. 4 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Electrical Characteristics DC PARAMETERS (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vcc = +15V, Vcm = 0V, Rl > 100K Ohms, Rs = 10K Ohms. SYMBOL Vio Iib Iio +Vcmr PARAMETER CONDITIONS NOTES Input Offset Voltage Input Bias Current Input Offset Current Positive Common-Mode Voltage Range Negative Common-Mode Voltage Range PSRR Ios Common-Mode Rejection Ratio Power Supply Rejection Ratio Output Short Circuit Current Avs +Vop Positive Voltage Swing SUBGROUPS -7 7 mV 1 -10 10 mV 2, 3 -3 3 uA 1 -6 6 uA 2, 3 -350 350 nA 1 -800 800 nA 2, 3 1 Vcc = +15V 13.8 V 2, 3 2 3.9 V 1 2 3.8 V 2, 3 Vcc = +15V -12.9 V 1 Vcc = +15V -12.7 V 2, 3 2 2.0 V 1 2 2.2 V 2, 3 -12.9V < Vcm < 13.9V 80 dB 1 -12.7V < Vcm < 13.8V 74 dB 2, 3 +10V < Vcc < +16V 80 dB 1 +10V < Vcc < +16V 74 dB 2, 3 -30 mA 1 -20 mA 2, 3 30 mA 1 20 mA 2, 3 6.5 mA 1 6.8 mA 2, 3 Source Supply Current Large Signal Voltage Gain UNIT V Sink Icc MAX 13.9 Vcc = +5V CMRR MIN Vcc = +15V Vcc = +5V -Vcmr PINNAME Vout = +10V, Rl = 2K Ohms 1 550 V/V 1 Vout = +10V, Rl = 2K Ohms 1 300 V/V 2, 3 Vcc = +15V, Rl = 2K Ohms 13.5 V 1 Vcc = +15V, Rl = 2K Ohms 13.3 V 2, 3 Vcc = +5V, Rl = 2K Ohms 3.5 V 1 3.3 V 2, 3 5 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Electrical Characteristics DC PARAMETERS(Continued) (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vcc = +15V, Vcm = 0V, Rl > 100K Ohms, Rs = 10K Ohms. SYMBOL -Vop PARAMETER Negative Voltage Swing CONDITIONS NOTES PINNAME MIN MAX UNIT SUBGROUPS Vcc = +15V, Rl = 2K Ohms -13.0 V 1 Vcc = +15V, Rl = 2K Ohms -12.7 V 2, 3 Vcc = +5V, Rl = 2K Ohms 1.7 V 1 2.0 V 2, 3 40 Mhz 4 30 Mhz 5, 6 200 V/uS 4 180 V/uS 5, 6 200 V/uS 4 180 V/uS 5, 6 AC PARAMETERS (The following conditions apply to all the following parameters, unless otherwise specified.) AC: Vcc = +15V, Vcm = 0V, Rl > 100K Ohms, Rs = 10K Ohms. Gbw +Sr -Sr ts Gain Bandwidth Product Slew Rate Slew Rate Setting Time f = 20Mhz Output step = -4V to +4V, Av = +1, Vin = 8V step Output step = +4V to -4V, Av = +1, Vin = 8V step 10V step to 0.1% , Av = 1, Rl = 2K Ohms 300 nS 9 325 nS 10, 11 DC PARAMETERS: DRIFT VALUES (The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vcc = +15V, Vcm = 0V, Rl > 100K Ohms, Rs = 10K Ohms. Delta Calculations Performed on QMLV Devices at Group B, Subgroup 5 ONLY. Vio Input Offset Voltage -0.7 +0.7 mV 1 Iib Input Bias Current -0.5 +0.5 uA 1 Iio Input Offset Current -35 +35 nA 1 CMRR Common Mode Rejection Ratio -5 +5 dB 1 Note 1: Note 2: -12.9V < +Vcm < 13.9V Voltage gain is the total output swing (20V) divided by the signal required to produce that swing. For single supply operation, the following conditions apply: V+ = 5V, V- = 0V, Vcm = 2.5V, Vout = 2.5V. Vio adjust pins are each connected to V- to realize maximum output swing. This connection will degrade Vio. 6 MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Graphics and Diagrams GRAPHICS# DESCRIPTION 05885HRA4 CERDIP (J), 8 LEAD (B/I CKT) 06190HRA3 CERPACK (W, WG), 10LD (B/I CKT) 06191HRA2 LCC (E), TYPE C, 20 TERMINAL (B/I CKT) E20ARE LCC (E), TYPE C, 20 TERMINAL(P/P DWG) J08ARL CERDIP (J), 8 LEAD (P/P DWG) P000167A CERPACK (W), 10 LEAD (PINOUT) P000168B LCC (E), 20 LEAD, TYPE C (PINOUT) P000169A CERDIP (J), 8 LEAD (PINOUT) P000259A CERAMIC SOIC (WG), 10 LEAD (PINOUT) W10ARG CERPACK (W), 10 LEAD (P/P DWG) WG10ARC CERAMIC SOIC (WG), 10 LEAD (P/P DWG) See attached graphics following this page. 7 NC 1 10 VIO ADJUST 2 9 VIO ADJUST IN- 3 8 V+ IN+ 4 7 VOUTPUT V- 5 6 NC LM6161W 10 - LEAD CERPACK CONNECTION DIAGRAM TOP VIEW P000167A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 NC VIO ADJUST VIO ADJUST N/C N/C N/C 3 2 1 20 19 18 N/C 5 17 V+ N/C 6 16 N/C IN+ 7 15 VOUT N/C 8 14 N/C N/C 4 IN- 9 10 11 12 13 N/C V- N/C N/C N/C LM6161E 20 - LEAD LCC CONNECTION DIAGRAM TOP VIEW P000168B N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 1 8 VIO ADJUST IN- 2 7 V+ IN+ 3 6 VOUT V- 4 5 NC VIO ADJUST LM6161J 8 - LEAD DIP CONNECTION DIAGRAM TOP VIEW P000169A N MIL/AEROSPACE OPERATIONS 2900 SEMICONDUCTOR DRIVE SANTA CLARA, CA 95050 N MICROCIRCUIT DATA SHEET MNLM6161-X REV 2A1 Revision History Rev ECN # Originator Changes 1A1 M0002843 11/23/98 Rel Date Barbara Lopez Update MDS: MNLM6161-X Rev. 0B0 to MNLM6161-X Rev. 1A1. Updated NSID, deleted W-SMD and added WG ID. Added SMD number for WG package. Added WG package to thermal resistance, updated note 6, deleted note 7, added power dissipation limit in Absolute section. Updated Subgroups to match SMD, added note 2 to Electrical section. Added MKT graphic for WG package. Added Pinouts for all packages. Added Burn-In CKT for W and E packages. 2A1 M0003073 11/23/98 Rose Malone Update MDS: MNLM6161-X, Rev. 1A1 to MNLM6161-X, Rev. 2A1. 8