LR38630 Digital Signal Processor for CIF CMOS Image Cameras LR38630 DESCRIPTION The LR38630 is a CMOS digital signal processor for color camera systems of 110 k-pixel CMOS image sensor with primary color mosaic filters. The camera system consists of CIF CMOS image sensor (LZ34C10) and DSP IC (LR38630) with 2 kbit EEPROM. Depending on application, 1 M-bit SRAM can be added in order to get slower frame rate at video output. FEATURES • Designed for 110 k-pixel color CMOS image sensors with R, G, and B color mosaic filters • Compatible with CIF standard • External control interface input/output • Variable GAMMA and KNEE response • 8-bit digital input • Available for digital video 4 : 2 : 2 (U/Y/V/Y) output • Built-in synchronous signal generation circuit to drive CMOS image sensor • Built-in 2 k-bit EEPROM controller to set the camera adjustment data • Built-in auto exposure control • Built-in auto white balance control • Built-in auto carrier balance control • Built-in white blemish compensator • Lower power consumption by dual clocking signal process technology • Single +3.0 V power supply • Package : 80-pin LQFP (LQFP080-P-1212) 0.5 mm pin-pitch In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. 1 LR38630 PIN CONNECTIONS TOP VIEW 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 42 20 41 40 43 19 39 44 18 38 45 17 37 46 16 36 47 15 35 48 14 34 49 13 33 50 12 32 51 11 31 52 10 30 53 9 29 54 8 28 55 7 27 56 6 26 57 5 25 58 4 24 3 23 59 22 60 2 21 1 ADD16 ADD15 ADD14 GND VDD ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 GND ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 ACL CKI GND VDD AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND VDD TST3 ADDSEL SCLK SDI CHD CVD 79 80 ADJMODE IFMODE EEPCK EEPDA VDD GND VS OLSTEN HREF STANDBY CTLDCK CTLDEN CTLDOUT CTLDIN VDD GND DATA0 DATA1 DATA2 DATA3 80-PIN LQFP (LQFP080-P-1212) 2 DATA4 DATA5 DATA6 DATA7 RCLK VDD GND EXMCK MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 WE OE TST2 TST1 LR38630 BLOCK DIAGRAM SRAM CONTROL OE, WE MDIO7-MDIO0 PROCESSOR SSG EXMCK ADD16-ADD0 AD7-AD0 FPN SUPPRESSION OB CLAMP BLACK BALANCE WHITE BALANCE GAMMA 1H/2H DELAY LINE WHITE BALANCE CONTROL EXPOSURE CONTROL SDI, SCLK CVD, CHD ACL CMOS IMAGE SENSOR INTERFACE CMOS IMAGE SENSOR SSG INTERPOLATION COLOR MATRIX LUMINANCE SIGNAL PROCESS COLOR SUPPRESS IMAGE FORMAT CONVERTER DATA7-DATA0 RCLK EXTERNAL INTERFACE CTLDIN, CTLDOUT CTLDEN, CTLDCK IFMODE, ADJMODE EEPROM INTERFACE EEPDA, EEPCK SETUP CKI STANDBY HREF, OLSTEN, VS TST1, TST2 3 LR38630 PIN DESCRIPTION PIN NO. SYMBOL 1 ACL I/O IC POLARITY DESCRIPTION Initializing input. 2 3 CKI GND IC – Clock input. Connect to pin 14 of LZ34C10. A grounding pin. 4 5 VDD AD7 – IC Supply of +3.0 V power. Digital signal input, fed from pin 23 of LZ34C10 (MSB). 6 7 AD6 AD5 IC IC Digital signal input, fed from pin 22 of LZ34C10. Digital signal input, fed from pin 21 of LZ34C10. 8 AD4 IC Digital signal input, fed from pin 20 of LZ34C10. 9 10 AD3 AD2 IC IC Digital signal input, fed from pin 19 of LZ34C10. Digital signal input, fed from pin 18 of LZ34C10. 11 12 AD1 AD0 IC IC Digital signal input, fed from pin 17 of LZ34C10. Digital signal input, fed from pin 16 of LZ34C10 (LSB). 13 GND – A grounding pin. 14 15 VDD – Supply of +3.0 V power. TST3 IC A test pin. Connect to GND. IC Pin to set MSB to be added on serial address data. Low : MSB = 0 (address 00h-7Fh), 16 ADDSEL 17 18 SCLK SDI OBF4M OBF4M Clock output of serial data, connected to pin 28 of LZ34C10. Serial data output, connected to pin 27 of LZ34C10. 19 20 CHD CVD OBF4M OBF4M Horizontal drive pulse output, connected to pin 25 of LZ34C10. Vertical drive pulse output, connected to pin 26 of LZ34C10. 21 ADD16 OBF4M Address output to drive an external SRAM. 22 23 ADD15 ADD14 OBF4M OBF4M Address output to drive an external SRAM. Address output to drive an external SRAM. 24 25 GND VDD 26 27 ADD13 ADD12 OBF4M OBF4M Address output to drive an external SRAM. Address output to drive an external SRAM. 28 ADD11 OBF4M Address output to drive an external SRAM. 29 30 ADD10 ADD9 IO4M IO4M Address output to drive an external SRAM. Address output to drive an external SRAM. 31 32 ADD8 ADD7 IO4M IO4M Address output to drive an external SRAM. Address output to drive an external SRAM. 33 ADD6 IO4M Address output to drive an external SRAM. 34 35 GND ADD5 – IO4M A grounding pin. Address output to drive an external SRAM. 36 37 ADD4 ADD3 IO4M IO4M Address output to drive an external SRAM. Address output to drive an external SRAM. 38 ADD2 IO4M Address output to drive an external SRAM. 39 ADD1 IO4M Address output to drive an external SRAM. High : MSB = 1 (address 80h-FFh) – – A grounding pin. Supply of +3.0 V power. 4 LR38630 PIN NO. SYMBOL 40 ADD0 I/O POLARITY DESCRIPTION IO4M Address output to drive an external SRAM. 41 TST1 IC 42 43 TST2 OE IC OBF4M A test pin. Connected to GND. A test pin. Connected to GND. Output enable to drive an external SRAM. 44 WE OBF4M Write enable to drive an external SRAM. 45 MDIO7 IO4MU Address output to drive an external SRAM. 46 47 MDIO6 MDIO5 IO4MU IO4MU Address output to drive an external SRAM. Address output to drive an external SRAM. 48 MDIO4 IO4MU Address output to drive an external SRAM. 49 50 MDIO3 MDIO2 IO4MU IO4MU Address output to drive an external SRAM. Address output to drive an external SRAM. 51 52 MDIO1 MDIO0 IO4MU IO4MU Address output to drive an external SRAM. Address output to drive an external SRAM. 53 EXMCK IC External clock input. 54 55 GND VDD – – A grounding pin. Supply of +3.0 V power. 56 57 RCLK DATA7 OBF4M OBF4M Clock output for digital video output signal. Data input/output to drive an external SRAM. 58 DATA6 OBF4M Data input/output to drive an external SRAM. 59 60 DATA5 DATA4 OBF4M OBF4M Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. 61 62 DATA3 DATA2 OBF4M OBF4M Data input/output to drive an external SRAM. Data input/output to drive an external SRAM. 63 DATA1 OBF4M Data input/output to drive an external SRAM. 64 65 DATA0 GND OBF4M – Data input/output to drive an external SRAM. A grounding pin. 66 67 VDD CTLDIN – IC 68 69 CTLDOUT OBF4M CTLDEN IC Serial data input. The rising edge enables the serial data to be available. Supply of +3.0 V power. Serial data input. 70 CTLDCK IC Clock input to set the data. 71 STANDBY IC 72 HREF High level puts this IC and LZ34C10 in standby mode. Horizontal blanking pulse output keeping high level during the effective image 73 OLSTEN OBF4M 74 VS 75 GND – 76 VDD – 77 EEPDA OBF4M OBF4M IO4M period. Horizontal pulse output going to low level when starting in horizontal. Vertical blanking pulse output keeping high level during the effective image period. A grounding pin. Supply of +3.0 V power. Data input/output to/from EEPROM. Going to high-impedance with high level of pin 80. 5 LR38630 PIN NO. SYMBOL 78 79 EEPCK IFMODE I/O IO4M IC POLARITY DESCRIPTION Clock input/output to/from EEPROM. Going to high-impedance with high level of pin 80. The option of number of bits of serial data to adjust. High level : W/R flag + address 6 bits + data 16 bits Low level : W/R flag + address 8 bits + data 8 bits Void input of internal automatic control circuit, connected to low level normally. 80 IO4M IO4MU ADJMODE IC High level input stops automatic control function. Power-on with high level input stops automatic loading of EEPROM data. : Input/output pin (4 mA output, CMOS level input) : Input/output pin (4 mA output, CMOS level input with pull-up resistor) OBF4M IC 6 : Output pin (4 mA output) : Input pin (CMOS level input) LR38630 INTERNAL COEFFICIENT TABLE ADDRESS 00h NAME – 01h – – 2 MOS_MIR (7) (6) 02h MOS_SAD BITS – Not used. 2 (5) (4) 3 (3) MOS_AGC 03h (2) (1) FUNCTION Not used. Option of the output image type. 00 : Normal 10 : Reversed left and right Option of AD converter clock phase. 00 : Reference 10 : Delayed by 180˚ 01 : Inverted top and bottom 11 : Reversed all 01 : Delayed by 90˚ 11 : Delayed by 270˚ Option of AGC offset gain. 000 : 3 dB 001 : 4 dB 010 : 5 dB 100 : 7 dB 011 : 6 dB 101 : 8 dB 110 : 9 dB 111 : 10 dB MOS_STD 1 (0) Under low level at pin 71, this bit can make CMOS image sensor standby. 0 : Operating 1 : Standby QCIF_SEL 1 (7) Option of sampling position in QCIF. 0 : Red filter 1 : Green filter 1 (6) Carrier balance function. CA_HOLD BLC 1 (5) Option of exposure level reference. 0 : Data of address 06h 0 : Automatic added an offset (coefficient) 1 : 0h added an offset (coefficient) 1 : Data of address 09h 2 WB_MODE EE_HOLD (4) Option of white balance mode. 00 : Automatic 01 : Preset WB1 (3) 2 1X : Preset WB2 Option of electronic exposure mode. (2) (1) 00 : Automatic electronic shutter speed and AGC ON 01 : Fixed electronic shutter speed and AGC ON 10 : Automatic electronic shutter speed and AGC OFF OFSET_AUTO 1 (0) 11 : Fixed electronic shutter speed and AGC OFF Option of optical black level control. 0 : Automatic 1 : Fixed level 7 LR38630 ADDRESS 04h NAME OUT_SEL BITS 2 Option of output mode. (7) (6) 2 IN_TIM FUNCTION 00 : QCIF1 01 : CIF 10 : QVGA 11 : QCIF2 Clock timing for input. (5) (4) 00 : Delayed by one CK 10 : Not delayed 01 : Delayed by two CK 4 (3) 0000 : CIF image output with CKI clock of CMOS image sensor 0001 : 1 frame of image output per second with CKI clock (2) 0010 : 2 frames of image output per second with CKI clock (1) (0) 0011 : 15 frames of image output per second with CKI clock 0101 : 1 frame of image output per second with EXCK clock (1 frame data is written to RAM in vertical blanking.) 0110 : 2 frames of image output per second with EXCK clock ACT_MODE (2 frames data are written to RAM in vertical blanking.) 0111 : Image output with EXMCK clock (EXMCK should be lower than 4.5 MHz.) 1XXX : Except 0000, works with 30 frames after power-on. (example) 1001 : 1 frame of image output per second with CKI starting with 30 frames after power-on. 05h 06h ACT_TIM REF_IRIS 07h 8 1000 : Prohibited to use Setting a period to work with 30 frames after power-on. 8 A period = (Data + 1) x frame rate Electronic exposure reference level. 8 The second target area of electronic exposure control. CTLD_01 08h 09h In the case that exposure control data is within (data of address 06h ± data of address 07h), the exposure control is completed. CTLD_02 8 The first target area of electronic exposure control. If exposure control data is over (data of address 06h ± data of address 08h), the REF_BLC 8 exposure control is restarted. Exposure reference level in BLC (valid with BLC of address 03h = 1). 8 The second target area of electronic exposure control in BLC. 0Ah CTLD_11 0Bh In the case that exposure control data is within (data of address 09h ± data of address 0Ah), the exposure control is completed. 8 CTLD_12 The first target area of electronic exposure control in BLC. If exposure control data is over (data of address 09h ± data of address 0Bh), the exposure control is restarted. 8 LR38630 ADDRESS 0Ch NAME SH_MAX BITS FUNCTION 2 Option of maximum electronic shutter speed in automatic. (7) (6) Electronic exposure control. 00 : 1/9 900 s 01 : 1/4 950 s 10 : 1/1 980 s 11 : 1/1 100 s EE_SPD 2 (5) (4) 2 Option of electronic shutter speed and AGC speed change. 00 : Shutter speed is changed by 10-19 pitches. 01 : Shutter speed is changed by 8-10 pitches. 1X : Shutter speed is changed by 1 pitch (the finest) Window option of automatic electronic exposure control. EE_RATIO (3) (2) 2 Option of time constant in electronic exposure control. EE_LPF (1) (0) 00 : Longer time constant 01 : Long time constant 1X : No time constant 0Dh 0Eh SH_HOLD2 1 8 MSB of fixed electronic shutter speed. Lower bits of fixed electronic shutter speed. 0Fh AGC_HOLD OFSET_HOLD 8 Preset gain in making AGC OFF (EE_HOLD = 1X at address 03h). Fixed optical black level (OFSET_AUTO =1 at address 03h). 10h SH_HOLD1 11h OFSET_LPF 00 : Center weighted 1 10 : No window 01 : Center weighted 2 11 : Lower-position weighted Data between 000 and 149 can be set by address 0Dh and 0Eh. 8 2 (4) (3) Time constant option of automatic optical black level control. 00 : Longer time constant 01 : Long time constant 1X : No time constant WBFIX1 SEL_LPF 1 (2) 2 (1) (0) Option of automatic white balance control. 0 : Not accelerated 1 : Accelerated Time constant option of automatic white balance control. 00 : Longer time constant 01 : Long time constant 1X : No time constant 12h 8 KGBGR1 The first target area of automatic white balance control in minus direction of highspeed mode. In the case that white balance control data is within (data of address 12h + data of address 13h), high-speed mode control is completed and then changed to normalspeed control mode. 9 LR38630 ADDRESS 13h NAME BITS FUNCTION The first target area of automatic white balance control in plus direction of high8 speed mode. KGBGR2 In the case that white balance control data is within (data of address 12h + data of address 13h), high-speed mode control is completed and then changed to normalspeed control mode. 14h 8 The second target area of automatic white balance control in minus direction of high-speed mode. In the case that white balance control data is over (data of address 14h + data of KGBGR3 address 15h), high-speed mode control is restarted. 15h 8 KGBGR4 The second target area of automatic white balance control in plus direction of highspeed mode. In the case that white balance control data is over (data of address 14h + data of address 15h), high-speed mode control is restarted. 16h LIMIM 8 Limitation in making white balance data at minus I-axis. 17h 18h LIMIP LIMQM 8 8 Limitation in making white balance data at plus I-axis. Limitation in making white balance data at minus Q-axis. 19h 1Ah LIMQP 8 8 Limitation in making white balance data at plus Q-axis. Limitation in making white balance data. A pixel with lower luminance level than 8 Limitation in making white balance data. A pixel with higher luminance level than data of this address is neglected. 7 The first target area of auto white balance control in minus I-axis. In the case that white balance control data is within the area by address 1Ch, 1Dh, 1Eh and 1Fh, 1Bh YLCL YHCL 1Ch data of this address is neglected. LIMWIIM automatic white balance control is completed. 1Dh 1Eh 1Fh 20h LIMWIIP LIMWIQM LIMWIQP 7 7 The first target area of auto white balance control in plus I-axis. The first target area of auto white balance control in minus Q-axis. 7 7 The first target area of auto white balance control in plus Q-axis. The second target area of auto white balance control in I-axis. In the case that LIMWOI 21h white balance control data is over the area by address 20h and 21h, automatic white balance control is restarted. 7 LIMWOQ 22h 23h WBR_MAX WBR_MIN The second target area of auto white balance control in Q-axis. In the case that white balance control data is over the area by address 20h and 21h, automatic white balance control is restarted. 8 8 Maximum gain of red signal in automatic white balance control. Minimum gain of red signal in automatic white balance control. 24h WBB_MAX 8 Maximum gain of blue signal in automatic white balance control. 25h 26h WBB_MIN WBR1 8 8 Minimum gain of blue signal in automatic white balance control. White balance preset 1 : Red signal gain 27h 28h WBB1 WBR2 8 8 White balance preset 1 : Blue signal gain White balance preset 2 : Red signal gain 29h WBB2 8 White balance preset 2 : Blue signal gain 10 LR38630 ADDRESS NAME 2Ah GAM_SLOPE0 BITS FUNCTION 8 Gamma curve setting : First straight line slope 2Bh GAM_SLOPE1 8 Gamma curve setting : Second straight line slope 2Ch GAM_SLOPE2 8 2Dh GAM_SLOPE3 8 Gamma curve setting : Third straight line slope Gamma curve setting : Fourth straight line slope 2Eh GAM_SLOPE4 8 2Fh GAM_SLOPE5 8 Gamma curve setting : Fifth straight line slope Gamma curve setting : Sixth straight line slope 30h 31h GAM_SLOPE6 GAM_SLOPE7 8 8 Gamma curve setting : Seventh straight line slope Gamma curve setting : Eighth straight line slope 32h GAM_SLOPE8 8 Gamma curve setting : Ninth straight line slope 33h 34h GAM_SLOPE9 GAM_OFSET1 8 8 Gamma curve setting : Tenth straight line slope Gamma curve setting : Second straight line offset 35h 36h GAM_OFSET2 GAM_OFSET3 8 8 Gamma curve setting : Third straight line offset Gamma curve setting : Fourth straight line offset 37h GAM_OFSET4 8 Gamma curve setting : Fifth straight line offset 38h 39h GAM_OFSET5 GAM_OFSET6 8 8 Gamma curve setting : Sixth straight line offset Gamma curve setting : Seventh straight line offset 3Ah 3Bh GAM_OFSET7 GAM_OFSET8 8 8 Gamma curve setting : Eighth straight line offset Gamma curve setting : Ninth straight line offset 3Ch 3Dh GAM_OFSET9 8 8 Gamma curve setting : Tenth straight line offset 3Eh KCBR KCBB 8 Carrier balance : Red signal compensation Carrier balance : Blue signal compensation 3Fh 40h KCBG1 KCBG2 8 8 Carrier balance : Green signal compensation in RG line Carrier balance : Green signal compensation in BG line 41h 42h KY1 8 6 Gain in middle frequency components of luminance signal. 43h KHC KHGA 8 Horizontal aperture level compression in lower luminance level. Horizontal aperture gain. 44h 45h KVC KVGA 6 8 Vertical aperture level compression in lower luminance level. Vertical aperture gain. 46h 47h KLL KSU 8 6 Luminance level. Set up level. 48h K0_MAT1 8 AWB color matrix : R – Y 1 49h 8 4Ah K1_MAT1 K2_MAT1 8 AWB color matrix : R – Y 2 AWB color matrix : B – Y 1 4Bh 4Ch K3_MAT1 K0_MAT2 8 8 AWB color matrix : B – Y 2 WB1 color matrix : R – Y 1 4Dh K1_MAT2 8 WB1 color matrix : R – Y 2 4Eh 4Fh K2_MAT2 K3_MAT2 8 8 WB1 color matrix : B – Y 1 WB1 color matrix : B – Y 2 50h 51h K0_MAT3 K1_MAT3 8 8 WB2 color matrix : R – Y 1 WB2 color matrix : R – Y 2 52h K2_MAT3 8 WB2 color matrix : B – Y 1 11 LR38630 ADDRESS NAME 53h K3_MAT3 54h 55h KCRGA 56h KCBGA KCRGA1 57h 58h KCBGA1 KCRGA2 BITS 8 WB2 color matrix : B – Y 2 8 8 FUNCTION AWB color level : R – Y 8 AWB color level : B – Y WB1 color level : R – Y 8 8 WB1 color level : B – Y WB2 color level : R – Y 59h KCBGA2 8 WB2 color level : B – Y 5Ah KCCR 7 R – Y color signal base clip level. 5Bh KCCB 7 B – Y color signal base clip level. 5Ch 5Dh KCLC KLGL 8 4 Lower luminance level to suppress color signal level. Gain to suppress color signal level by data of address 5Ch. 5Eh 5Fh KCHC KLGH 8 4 Higher luminance level to suppress color signal level. Gain to suppress color signal level by data of address 5Eh. 60h KLGE 8 Gain to suppress color edge signal. 61h 62h KILL_AGC KILL_AGCG 8 4 AGC gain to start the suppression of color signal level. 63h 64h APT_AGC APT_AGCG 8 4 AGC gain to start the suppression of aperture level. Gain to suppress aperture level by data of address 63h. 65h 66h FPN_GA 8 8 Gain for fixed pattern noise signal. 67h 68h 69h AGC_SLP1 AGC_SLP2 AGC_SLP3 AGC_SLP4 8 8 8 Gain to suppress color signal level by data of address 61h. AGC gain compensation 1 for fixed pattern noise signal. AGC gain compensation 2 for fixed pattern noise signal. AGC gain compensation 3 for fixed pattern noise signal. AGC gain compensation 4 for fixed pattern noise signal. IN_OUT 1 (0) Option of output mode. 6Bh – – Not used. 6Ch 6Dh – – – – Not used. Not used. 6Eh 6Fh – TEST – 5 Not used. Data should be 00h. 70h R_DATA1 8 Lower 8 bits of red signal to control auto white balance. 71h 72h R_DATA2 G_DATA1 4 8 Upper 4 bits of red signal to control auto white balance. Lower 8 bits of green signal to control auto white balance. 73h 74h G_DATA2 B_DATA1 4 8 Upper 4 bits of green signal to control auto white balance. Lower 8 bits of blue signal to control auto white balance. 6Ah 0 : Normal processing 1 : Output of input signal1 75h B_DATA2 4 Upper 4 bits of blue signal to control auto white balance. 76h I_DATA1 8 Lower 8 bits of I signal to control auto white balance. 77h I_DATA2 1 Sign bit of I signal to control auto white balance. 78h 79h Q_DATA1 Q_DATA2 8 1 Lower 8 bits of Q signal to control auto white balance. Sign bit of Q signal to control auto white balance. 7Ah IRIS_DATA1 8 Lower 8 bits of luminance signal to control auto exposure. 12 LR38630 ADDRESS NAME BITS FUNCTION Upper 4 bits of luminance signal to control auto exposure. 7Bh IRIS_DATA2 4 Red signal to control auto carrier balance. 7Ch 7Dh RCA_DATA GRCA_DATA 8 8 Green signal in RG line to control auto carrier balance. 7Eh BCA_DATA 8 Blue signal to control auto carrier balance. 7Fh 80h GBCA_DATA WP00H1 8 8 Green signal in BG line to control auto carrier balance. Lower 8 bits of X-axis on the position of white blemish 1. 81h 82h WP00H2 WP00V1 1 8 MSB of X-axis on the position of white blemish 1. Lower 8 bits of Y-axis on the position of white blemish 1. 83h WP00V2 1 MSB of Y-axis on the position of white blemish 1. 84h 85h WP01H1 WP01H2 8 1 Lower 8 bits of X-axis on the position of white blemish 2. MSB of X-axis on the position of white blemish 2. 86h 87h WP01V1 WP01V2 8 1 Lower 8 bits of Y-axis on the position of white blemish 2. MSB of Y-axis on the position of white blemish 2. 88h WP02H1 8 Lower 8 bits of X-axis on the position of white blemish 3. 89h 8Ah WP02H2 WP02V1 1 8 MSB of X-axis on the position of white blemish 3. Lower 8 bits of Y-axis on the position of white blemish 3. 8Bh 8Ch WP02V2 WP03H1 1 8 MSB of Y-axis on the position of white blemish 3. Lower 8 bits of X-axis on the position of white blemish 4. WP03H2 1 8 8Dh 8Eh MSB of X-axis on the position of white blemish 4. 8Fh WP03V1 WP03V2 1 Lower 8 bits of Y-axis on the position of white blemish 4. MSB of Y-axis on the position of white blemish 4. 90h 91h WP04H1 WP04H2 8 1 Lower 8 bits of X-axis on the position of white blemish 5. MSB of X-axis on the position of white blemish 5. 92h WP04V1 8 Lower 8 bits of Y-axis on the position of white blemish 5. 93h WP04V2 WP05H1 1 94h 8 MSB of Y-axis on the position of white blemish 5. Lower 8 bits of X-axis on the position of white blemish 6. 95h 96h WP05H2 WP05V1 1 8 MSB of X-axis on the position of white blemish 6. Lower 8 bits of Y-axis on the position of white blemish 6. 97h 98h WP05V2 WP06H1 1 8 MSB of Y-axis on the position of white blemish 6. Lower 8 bits of X-axis on the position of white blemish 7. 99h WP06H2 1 MSB of X-axis on the position of white blemish 7. 9Ah 9Bh WP06V1 WP06V2 8 1 Lower 8 bits of Y-axis on the position of white blemish 7. MSB of Y-axis on the position of white blemish 7. 9Ch 9Dh WP07H1 WP07H2 8 1 Lower 8 bits of X-axis on the position of white blemish 8. MSB of X-axis on the position of white blemish 8. 9Eh WP07V1 8 Lower 8 bits of Y-axis on the position of white blemish 8. 9Fh A0h WP07V2 WP08H1 1 8 MSB of Y-axis on the position of white blemish 8. Lower 8 bits of X-axis on the position of white blemish 9. A1h A2h WP08H2 WP08V1 1 8 MSB of X-axis on the position of white blemish 9. Lower 8 bits of Y-axis on the position of white blemish 9. A3h WP08V2 1 MSB of Y-axis on the position of white blemish 9. 13 LR38630 ADDRESS NAME A4h WP09H1 A5h A6h WP09H2 BITS FUNCTION 8 Lower 8 bits of X-axis on the position of white blemish 10. 1 8 MSB of X-axis on the position of white blemish 10. A7h WP09V1 WP09V2 1 Lower 8 bits of Y-axis on the position of white blemish 10. MSB of Y-axis on the position of white blemish 10. A8h A9h WP0AH1 WP0AH2 8 1 Lower 8 bits of X-axis on the position of white blemish 11. MSB of X-axis on the position of white blemish 11. AAh ABh WP0AV1 WP0AV2 8 1 Lower 8 bits of Y-axis on the position of white blemish 11. MSB of Y-axis on the position of white blemish 11. ACh WP0BH1 8 Lower 8 bits of X-axis on the position of white blemish 12. ADh AEh WP0BH2 WP0BV1 1 8 MSB of X-axis on the position of white blemish 12. Lower 8 bits of Y-axis on the position of white blemish 12. AFh B0h WP0BV2 WP0CH1 1 8 MSB of Y-axis on the position of white blemish 12. Lower 8 bits of X-axis on the position of white blemish 13. B1h WP0CH2 1 MSB of X-axis on the position of white blemish 13. B2h B3h WP0CV1 WP0CV2 8 1 Lower 8 bits of Y-axis on the position of white blemish 13. MSB of Y-axis on the position of white blemish 13. B4h B5h WP0DH1 WP0DH2 8 1 Lower 8 bits of X-axis on the position of white blemish 14. MSB of X-axis on the position of white blemish 14. B6h B7h WP0DV1 8 1 Lower 8 bits of Y-axis on the position of white blemish 14. B8h WP0DV2 WP0EH1 8 MSB of Y-axis on the position of white blemish 14. Lower 8 bits of X-axis on the position of white blemish 15. B9h BAh WP0EH2 WP0EV1 1 8 MSB of X-axis on the position of white blemish 15. Lower 8 bits of Y-axis on the position of white blemish 15. BBh BCh WP0EV2 1 8 MSB of Y-axis on the position of white blemish 15. BDh WP0FH1 WP0FH2 1 Lower 8 bits of X-axis on the position of white blemish 16. MSB of X-axis on the position of white blemish 16. BEh BFh WP0FV1 WP0FV2 8 1 Lower 8 bits of Y-axis on the position of white blemish 16. MSB of Y-axis on the position of white blemish 16. C0h C1h WP10H1 WP10H2 8 1 Lower 8 bits of X-axis on the position of white blemish 17. MSB of X-axis on the position of white blemish 17. C2h WP10V1 8 Lower 8 bits of Y-axis on the position of white blemish 17. C3h C4h WP10V2 WP11H1 1 8 MSB of Y-axis on the position of white blemish 17. Lower 8 bits of X-axis on the position of white blemish 18. C5h C6h WP11H2 WP11V1 1 8 MSB of X-axis on the position of white blemish 18. Lower 8 bits of Y-axis on the position of white blemish 18. C7h WP11V2 1 MSB of Y-axis on the position of white blemish 18. C8h C9h WP12H1 WP12H2 8 1 Lower 8 bits of X-axis on the position of white blemish 19. MSB of X-axis on the position of white blemish 19. CAh CBh WP12V1 WP12V2 8 1 Lower 8 bits of Y-axis on the position of white blemish 19. MSB of Y-axis on the position of white blemish 19. CCh WP13H1 8 Lower 8 bits of X-axis on the position of white blemish 20. 14 LR38630 ADDRESS NAME CDh WP13H2 CEh WP13V1 CFh WP13V2 BITS FUNCTION 1 MSB of X-axis on the position of white blemish 20. 8 1 MSB of Y-axis on the position of white blemish 20. Lower 8 bits of Y-axis on the position of white blemish 20. D0h WP14H1 8 Lower 8 bits of X-axis on the position of white blemish 21. D1h D2h WP14H2 WP14V1 1 8 MSB of X-axis on the position of white blemish 21. Lower 8 bits of Y-axis on the position of white blemish 21. D3h D4h WP14V2 WP15H1 1 8 MSB of Y-axis on the position of white blemish 21. Lower 8 bits of X-axis on the position of white blemish 22. D5h WP15H2 1 MSB of X-axis on the position of white blemish 22. D6h D7h WP15V1 WP15V2 8 1 Lower 8 bits of Y-axis on the position of white blemish 22. MSB of Y-axis on the position of white blemish 22. D8h D9h WP16H1 WP16H2 8 1 Lower 8 bits of X-axis on the position of white blemish 23. MSB of X-axis on the position of white blemish 23. DAh WP16V1 WP16V2 8 Lower 8 bits of Y-axis on the position of white blemish 23. MSB of Y-axis on the position of white blemish 23. Lower 8 bits of X-axis on the position of white blemish 24. DBh DCh WP17H1 1 8 DDh DEh WP17H2 WP17V1 1 8 MSB of X-axis on the position of white blemish 24. Lower 8 bits of Y-axis on the position of white blemish 24. DFh E0h WP17V2 WP18H1 1 8 MSB of Y-axis on the position of white blemish 24. E1h WP18H2 1 Lower 8 bits of X-axis on the position of white blemish 25. MSB of X-axis on the position of white blemish 25. E2h E3h WP18V1 WP18V2 8 1 Lower 8 bits of Y-axis on the position of white blemish 25. MSB of Y-axis on the position of white blemish 25. E4h WP19H1 8 Lower 8 bits of X-axis on the position of white blemish 26. E5h WP19H2 1 MSB of X-axis on the position of white blemish 26. E6h WP19V1 8 Lower 8 bits of Y-axis on the position of white blemish 26. E7h E8h WP19V2 WP1AH1 1 8 MSB of Y-axis on the position of white blemish 26. Lower 8 bits of X-axis on the position of white blemish 27. E9h EAh WP1AH2 WP1AV1 1 8 MSB of X-axis on the position of white blemish 27. Lower 8 bits of Y-axis on the position of white blemish 27. EBh WP1AV2 1 MSB of Y-axis on the position of white blemish 27. ECh EDh 8 1 Lower 8 bits of X-axis on the position of white blemish 28. MSB of X-axis on the position of white blemish 28. EEh EFh WP1BH1 WP1BH2 WP1BV1 WP1BV2 8 1 Lower 8 bits of Y-axis on the position of white blemish 28. MSB of Y-axis on the position of white blemish 28. F0h WP1CH1 8 Lower 8 bits of X-axis on the position of white blemish 29. F1h F2h WP1CH2 WP1CV1 1 8 MSB of X-axis on the position of white blemish 29. Lower 8 bits of Y-axis on the position of white blemish 29. F3h F4h WP1CV2 WP1DH1 1 8 MSB of Y-axis on the position of white blemish 29. Lower 8 bits of X-axis on the position of white blemish 30. F5h WP1DH2 1 MSB of X-axis on the position of white blemish 30. 15 LR38630 ADDRESS NAME F6h WP1DV1 F7h F8h WP1DV2 BITS FUNCTION 8 Lower 8 bits of Y-axis on the position of white blemish 30. 1 8 MSB of Y-axis on the position of white blemish 30. F9h WP1EH1 WP1EH2 1 Lower 8 bits of X-axis on the position of white blemish 31. MSB of X-axis on the position of white blemish 31. FAh FBh WP1EV1 WP1EV2 8 1 Lower 8 bits of Y-axis on the position of white blemish 31. MSB of Y-axis on the position of white blemish 31. FCh FDh WP1FH1 WP1FH2 8 1 Lower 8 bits of X-axis on the position of white blemish 32. MSB of X-axis on the position of white blemish 32. FEh WP1FV1 8 Lower 8 bits of Y-axis on the position of white blemish 32. FFh WP1FV2 1 MSB of Y-axis on the position of white blemish 32. 16 LR38630 Default Data Table ADDRESS 00h DATA – ADDRESS 20h DATA 05 ADDRESS 40h DATA 00 ADDRESS 60h DATA 10 01h 02h – 10 21h 22h 05 FE 41h 42h 40 04 61h 62h E0 04 03h 04h 00 00 23h 24h 10 FE 43h 44h 00 04 63h 64h E0 04 05h 06h 00 30 25h 26h 10 40 45h 46h 00 80 65h 66h 20 06 07h 03 27h 40 47h 00 67h 0B 08h 09h 06 3A 28h 29h 40 40 48h 49h 2D F9 68h 69h 14 23 0Ah 0Bh 04 08 2Ah 2Bh 14 18 4Ah 4Bh 39 ED 6Ah 6Bh 00 – 0Ch 00 2Ch 20 4Ch 2D 6Ch – 0Dh 0Eh 00 E7 2Dh 2Eh 18 18 4Dh 4Eh F9 39 6Dh 6Eh – – 0Fh 10h 00 80 2Fh 30h 12 0F 4Fh 50h ED 2D 6Fh 70h 00 – 11h 00 31h 0F 51h F9 71h – 12h 13h 6B 9A 32h 33h 0E 07 52h 53h 39 ED 72h 73h – – 14h 15h 55 C0 34h 35h 14 20 54h 55h 40 40 74h 75h – – 16h 80 36h 30 56h 40 76h – 17h 18h 80 40 37h 38h 3C 48 57h 58h 40 40 77h 78h – – 19h 1Ah 40 04 39h 3Ah 5A 78 59h 5Ah 40 04 79h 7Ah – – 1Bh 1Ch FE 02 3Bh 3Ch B4 DE 5Bh 5Ch 04 00 7Bh 7Ch – – 1Dh 02 3Dh 00 5Dh 00 7Dh – 1Eh 1Fh 02 02 3Eh 3Fh 00 00 5Eh 5Fh F0 08 7Eh 7Fh – – 17 LR38630 ABSOLUTE MAXIMUM RATINGS PARAMETER Power supply voltage Input voltage Output voltage Storage temperature SYMBOL VDD RATING –0.3 to +4.3 UNIT V VI VO –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 V V TSTG –55 to +150 ˚C RECOMMENDED OPERATING CONDITIONS PARAMETER Power supply voltage SYMBOL VDD MIN. 2.7 TYP. 3.0 MAX. 3.3 UNIT V Operating temperature Input clock frequency TOPR fCK –20 +25 9.0 +70 ˚C MHz ELECTRICAL CHARACTERISTICS PARAMETER Input "Low" voltage SYMBOL VIL Input "High" voltage VIH Input "Low" current Input "High" current |IIL1| |IIH1| (VDD = 3.0±0.3 V, TOPR = –20 to +70 ˚C) CONDITIONS VIN = 0 V VIN = VDD |IIL2| VI = 0 V Input "High" current Output "Low" voltage |IIH2| VOL VIN = VDD IOL = 4 mA Output "High" voltage VOH IOH = –4 mA NOTES : Applied Applied Applied Applied to to to to TYP. 0.8VDD Input "Low" current 1. 2. 3. 4. MIN. input (IC) and inputs/outputs (IO4M, IO4MU). input (IC) and input/output (IO4M). input/output (IO4MU). output (OBF4M) and inputs/outputs (IO4M, IO4MU). 18 40 0.8VDD 100 MAX. UNIT 0.2VDD V V 1.0 1.0 µA µA 300 µA 2.0 0.2VDD µA V V NOTE 1 2 3 4 LR38630 (APPENDIX) Weighting area of exposure control 1 block = 44 pixels in horizontal and 36 lines in vertical q (Bit 3, Bit 2) of address 0Ch = (0, 0) 2/4 1 2/4 1 2/4 1 2/4 1 1 1 1 1 1 1 1 1 5/4 5/4 5/4 5/4 1 1 1 1 5/4 5/4 5/4 5/4 1 1 1 1 2/4 1 2/4 1 2/4 1 2/4 1 1 1 1 1 5/4 5/4 5/4 5/4 1 1 1 1 5/4 5/4 5/4 5/4 1 1 1 1 1 1 1 1 w (Bit 3, Bit 2) of address 0Ch = (0, 1) 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 3/4 3/4 3/4 5/4 3/4 5/4 3/4 5/4 3/4 5/4 3/4 5/4 3/4 5/4 3/4 3/4 3/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 3/4 3/4 3/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 3/4 3/4 3/4 5/4 5/4 5/4 5/4 5/4 5/4 3/4 e (Bit 3, Bit 2) of address 0Ch = (1, 0) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r (Bit 3, Bit 2) of address 0Ch = (1, 1) 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 2/4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 5/4 19 PACKAGES FOR CCD AND CMOS DEVICES PACKAGE (Unit : mm) 80 LQFP (LQFP080-P-1212) 0.08 M 0.2±0.08 21 12.0±0.2 (1.0) (1.0) 0.6375 1.70MAX. 1.40±0.2 14.0±0.3 Package base plane (1.0) 20 13.0±0.2 80 20 0.1±0.1 0.10 40 12.0±0.2 61 1 0.125±0.05 (1.0) 41 60 14.0±0.3 0.5TYP.