LINER LT5512EUF

LT5512
1kHz-3GHz High Signal Level
Down-Converting Mixer
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FEATURES
DESCRIPTIO
The LT®5512 is a broadband mixer IC optimized for high
linearity downconverter applications including cable and
wireless infrastructure. The IC includes a differential LO
buffer amplifier driving a double-balanced mixer. An integrated RF buffer amplifier improves LO-RF isolation and
eliminates the need for precision external bias resistors.
Broadband RF, LO and IF Operation
High Input IP3: +21dBm at 900MHz
+17dBm at 1900MHz
Typical Conversion Gain: 1dB at 1900MHz
SSB Noise Figure: 11dB at 900MHz
14dB at 1900MHz
Integrated LO Buffer: Insensitive to LO Drive Level
Single-Ended or Differential LO Signal
High LO-RF Isolation
Enable Function
4.5V to 5.25V Supply Voltage Range
4mm × 4mm QFN Package
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The LT5512 is a high-linearity alternative to passive diode
mixers. Unlike passive mixers, which have conversion
loss and require high LO drive levels, the LT5512 delivers
conversion gain and requires significantly lower LO drive
levels.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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APPLICATIO S
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Cellular/PCS/UMTS Infrastructure
CATV Downlink Infrastructure
High Linearity Mixer Applications
ISM Band Receivers
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TYPICAL APPLICATIO
High Signal-Level Downmixer for Wireless Infastructure
Output IF Power and Output IM3 vs
RF Input Power (Two Input Tones)
5V
100pF
1850MHz
TO
1910MHz
10
0
EN
1:2
+
RF
LNA
VCC1
VCC2
LT5512
IF
1.5pF
220nH
+
100pF
IF –
70MHz
(TYP)
–10
IF
VGA
LTC1748
ADC
8.2pF
RF –
220nH
POUT, IM3 (dBm/TONE)
1850MHz
TO
1910MHz
1µF
–30
–40
–50
–60
LO
LO
INPUT
–10dBm
100pF
+
5.6nH
LO–
IFOUT
–20
–70
IM3
TA = 25°C
PLO = –10dBm
fLO = 1830MHz
fRF1 = 1899.9MHz
fRF2 = 1900.1MHz
–80
3
–21 –18 –15 –12 –9 –6 –3 0
RF INPUT POWER (dBm/TONE)
100pF
6
5512 F01b
5512 F01a
5512f
1
LT5512
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W W
W
ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
NUMBER
NC
LO –
NC
LO+
TOP VIEW
Supply Voltage ....................................................... 5.5V
Enable Voltage ............................... –0.3V to VCC + 0.3V
LO + to LO – Differential Voltage ............................ ±1.5V
................................................... (+6dBm equivalent)
+
RF to RF – Differential Voltage ............................. ±0.7V
.................................................. (+10dBm equivalent)
Operating Temperature Range .................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Junction Temperature (TJ)................................... 125°C
LT5512EUF
16 15 14 13
NC 1
12 GND
RF + 2
RF –
11 IF+
17
10 IF –
3
NC 4
5
6
7
8
EN
VCC1
VCC2
NC
9
GND
PART MARKING
5512
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD IS GROUND (PIN 17)
(MUST BE SOLDERED TO PCB)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
RF Input Frequency Range2
MIN
TYP
MAX
UNITS
Requires Appropriate Matching
0.001 to 3000
MHz
LO Input Frequency Range2
Requires Appropriate Matching
0.001 to 3000
MHz
IF Output Frequency Range2
Requires Appropriate Matching
0.001 to 2000
MHz
Downmixer Application: (Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25°C, PRF = –10dBm (–10dBm/tone for two-tone
IIP3 tests, ∆f = 200kHz), fLO = fRF – 170MHz, PLO = –10dBm, IF output measured at 170MHz, unless otherwise noted. (Notes 2, 3)
PARAMETER
CONDITIONS
Conversion Gain
fRF = 900MHz
fRF = 1900MHz
Conversion Gain vs Temperature
TA = – 40°C to 85°C
Input 3rd Order Intercept
MIN
TYP
–1
0
1
MAX
UNITS
dB
dB
–0.011
dB/°C
fRF = 900MHz
fRF = 1900MHz
21
17
dBm
dBm
Single-Sideband Noise Figure
fRF = 900MHz
fRF = 1900MHz
11
14
dB
dB
LO to RF Leakage
fLO = 730MHz
fLO = 1730MHz
–60
–53
dBm
dBm
LO to IF Leakage
fLO = 730MHz and 1730MHz
–46
dBm
RF to LO Isolation
fRF = 900MHz
fRF = 1900MHz
57
50
dB
dB
2RF-2LO Output Spurious Product
(fRF = fLO + fIF/2)
900MHz: fRF = 815MHz at –12dBm
1900MHz: fRF = 1815MHz at –12dBm
–66
–59
dBc
dBc
3RF-3LO Output Spurious Product
(fRF = fLO + fIF/3)
900MHz: fRF = 786.67MHz at –12dBm
1900MHz: fRF = 1786.67MHz at –12dBm
–83
–58
dBc
dBc
Input 1dB Compression
fRF = 900MHz
fRF = 1900MHz
10.1
6.2
dBm
dBm
5512f
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LT5512
ELECTRICAL CHARACTERISTICS
1230MHz Cable Infrastructure Downmixer Application: (Test Circuit Shown
in Figure 3) VCC = 5VDC, EN = High, TA = 25°C, RF input = 1230MHz at –10dBm, LO input swept from 1500MHz to 2100MHz,
PLO = –10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Conversion Gain
fLO = 1800MHz, fIF = 570MHz
2.8
dB
Input 3rd Order Intercept
2-Tone RF Input, –10dBm/Tone, ∆f = 1MHz,
fLO = 1800MHz, fIF = 570MHz
17.9
dBm
LO to RF Leakage
–56
dBm
LO to IF Leakage
– 40
dBm
RF to LO Isolation
51
dB
2RF – LO Output Spurious Product
fIF = 570MHz, PRF = –18dBm, fLO = 1800MHz
– 60
dBc
Single-Sideband Noise Figure
fLO = 1800MHz, fIF = 570MHz
13.3
dB
DC ELECTRICAL CHARACTERISTICS
(Note 3), unless otherwise noted.
PARAMETER
(Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25°C
CONDITIONS
MIN
TYP
MAX
UNITS
Enable (EN) Low = Off, High = On
Turn On Time
3
µs
Turn Off Time
13
µs
50
µA
Input Current
VENABLE = 5VDC
Enable = High (On)
3
VDC
Enable = Low (Off)
0.3
VDC
5.25
VDC
74
mA
100
µA
Power Supply Requirements (VCC)
Supply Voltage
4.50
Supply Current
57
Shutdown Current
EN = Low
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: External components on the final test circuit are optimized for
operation at fRF = 1900MHz, fLO = 1730MHz and fIF = 170MHz (Figure 2).
Note 3: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
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TYPICAL PERFOR A CE CHARACTERISTICS
(Test Circuit Shown in Figure 2)
Shutdown Current vs Supply Voltage
Supply Current vs Supply Voltage
59
100
58
SUPPLY CURRENT (mA)
SHUTDOWN CURRENT (µA)
TA = 85°C
57
56
TA = 25°C
55
54
53
TA = –40°C
52
51
10
TA = 85°C
TA = 25°C
1
TA = –40°C
50
49
4.5
4.75
5.25
5.0
SUPPLY VOLTAGE (V)
5.5
5512 G01
0.1
4.5
5.0
5.25
4.75
SUPPLY VOLTAGE (V)
5.5
5512 G02
5512f
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LT5512
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TYPICAL PERFOR A CE CHARACTERISTICS
(1900MHz Downmixer Application)
VCC = 5VDC, EN = High, TA = 25°C, 1900MHz RF input matching, RF input = 1900MHz at –10dBm, LO input = 1730MHz at –10dBm, IF
output measured at 170MHz, unless otherwise noted. (Test circuit shown in Figure 2).
Conv Gain, IIP3 and SSB NF vs
RF Frequency (Low-Side LO)
18
14
SSB NF
12
10
8
fIF = 170MHz
TA = 25°C
6
4
CONV GAIN
2
0
1700
1900
2000
1800
RF FREQUENCY (MHz)
20
16
14
SSB NF
12
10
fIF = 170MHz
TA = 25°C
8
6
4
CONV GAIN
2
0
1700
2100
18
IIP3
CONV GAIN (dB), IIP3 (dBm)
IIP3
16
CONV GAIN (dB), NF (dB), IIP3 (dBm)
TA = –40°C
6
TA = –40°C
TA = 25°C TA = 85°C
0
–18 –16 –14 –12 –10 –8 –6
LO INPUT POWER (dBm)
–4
HIGH-SIDE LO
14.0
LOW-SIDE LO
13.5
TA = –40°C
12.5
–55
–4
–60
–18 –16 –14 –12 –10 –8 –6
LO INPUT POWER (dBm)
–2
5512 • G08
RF, LO and IF Port Return Loss
vs Frequency
TA = –40°C
2
TA = 85°C
4.75
5.25
5.0
SUPPLY VOLTAGE (V)
5.5
5512 • G09
TA = 25°C
LO
TA = 85°C
–50
–70
–80
0
4.5
–5
TA = 85°C
–40
–60
–2
0
–20
–30
–4
TA = –40°C
0
CONV GAIN
TA = 25°C
–45
–50
–10 POUT
TA = 85°C
POUT, IM3 (dBm/TONE)
CONV GAIN (dB), IIP3 (dBm)
4
LO-IF
–40
13.0
10
6
100
–35
5512 • G07
18
8
75
–30
Output IF Power and Output IM3 vs
RF Input Power (Two Input Tones)
10
0
25
50
TEMPERATURE (°C)
fLO = 1730MHz
TA = 25°C
–25
12.0
–18 –16 –14 –12 –10 –8 –6
LO INPUT POWER (dBm)
–2
IIP3
–25
–20
fRF = 1900MHz
fIF = 170MHz
TA = 25°C
14.5
Conv Gain and IIP3 vs
Supply Voltage
14
HIGH-SIDE LO
LOW-SIDE LO
LO-IF and LO-RF Leakage vs
LO Input Power
5512 • G06
16
CONV GAIN
4
LO-RF
2
TA = 25°C
6
5512 • G05
LO LEAKAGE (dBm)
8
CONV GAIN
8
–50
15.0
TA = 85°C
SSB NF (dB)
CONV GAIN (dB), IIP3 (dBm)
15.5
10
12
2100
16.0
TA = 25°C
12
4
10
SSB Noise Figure vs
LO Input Power
20
IIP3
HIGH-SIDE LO
12
5512 • G04
Conv Gain and IIP3 vs
LO Input Power
16
LOW-SIDE LO
14
0
1800
2000
1900
RF FREQUENCY (MHz)
5512 • G03
18
IIP3
16
2
RETURN LOSS (dB)
CONV GAIN (dB), NF (dB), IIP3 (dBm)
18
14
Conv Gain and IIP3 vs Temperature
RF = 1900MHz, IF = 170MHz
Conv Gain, IIP3 and SSB NF vs
RF Frequency (High-Side LO)
TA = –40°C
IM3
–10
–15
IF
–20
RF
–25
TA = 25°C
–90
0
–21 –18 –15 –12 –9 –6 –3
RF INPUT POWER (dBm/TONE)
–30
3
5512 G10
TA = 25°C
0
500
1000 1500 2000
FREQUENCY (MHz)
2500
3000
5512 G11
5512f
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LT5512
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TYPICAL PERFOR A CE CHARACTERISTICS
(1900MHz Downmixer Application, continued)
VCC = 5VDC, EN = High, TA = 25°C, 1900MHz RF input matching, RF input = 1900MHz at –10dBm, LO input = 1730MHz at –10dBm, IF
output measured at 170MHz, unless otherwise noted. (Test circuit shown in Figure 2).
IF Output Power, 2RF-2LO and
3RF-3LO vs RF Input Power
2RF-2LO (Half-IF) Spur Level vs
LO Input Power
–50
–30
POUT
(RF = 1900MHz)
3RF-3LO
(RF = 1786.67MHz)
–50
2RF-2LO
(RF = 1815MHz)
–70
–65
PRF = –10dBm
–70
–75
–1
5512 G18
PRF = –10dBm
–65
–70
–75
PRF = –16dBm
–85
–90
–18 –16 –14 –12 –10 –8 –6
LO INPUT POWER (dBm)
2
–60
–80
PRF = –16dBm
–85
–110
–22 –19 –16 –13 –10 –7 –4
RF INPUT POWER (dBm)
TA = 25°C
fLO = 1730MHz
fRF = 1786.67MHz
–55
–60
–80
–90
–50
TA = 25°C
fLO = 1730MHz
fRF = 1815MHz
–55
SPUR LEVEL (dBm)
IF OUTPUT POWER (dBm)
TA = 25°C
fLO = 1730MHz
–10 PLO = –10dBm
SPUR LEVEL (dBm)
10
3RF-3LO Spur Level vs
LO Input Power
–4
–90
–18 –16 –14 –12 –10 –8 –6
LO INPUT POWER (dBm)
–2
5512 G19
–2
–4
5512 G20
(1230MHz Cable Infrastructure Downmixer Application) VCC = 5VDC, EN = High, TA = 25°C, RF input = 1230MHz at –10dBm, LO input
swept from = 1500MHz to 2100MHz, PLO = –10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted. (Test circuit
shown in Figure 3.)
Conv Gain, IIP3 and SSB NF
vs IF Output Frequency
0
TA = 25°C
16
–20
SSB NF
TA = 25°C
CONV GAIN
–40
–50
TA = 25°C
2
TA = –40°C
–60
470
570
770
370
670
IF OUTPUT FREQUENCY (MHz)
–70
1500
870
CONV GAIN (dB), IIP3 (dBm), NF (dB)
TA = –40°C
14
SSB NF
TA = 25°C
fLO = 1800MHz
fIF = 570MHz
8
CONV GAIN
TA = 25°C
TA = –40°C
4
TA = 85°C
2
–20
–15
–5
–10
LO INPUT POWER (dBm)
0
5512 G15
TA = 25°C
–90
–21 –18
2100
5512 G13
fLO = 1800MHz
fIF = 570MHz
–15 –12 –9
–6
RF INPUT POWER (dBm)
0
–3
5512 G14
RF, LO and IF Port Return Losses
vs Frequency
20
TA = 25°C
IIP3
16
1700 1800 1900 2000
LO FREQUENCY (MHz)
Conv Gain and IIP3 vs
Temperature
TA = 85°C
18
1600
5512 G12
Conv Gain, IIP3 and SSB NF
vs LO Input Power
20
TA = 85°C
–80
0
5.5VDC
18
4.5VDC
IIP3
–5
16
IF
14
RETURN LOSS (dB)
270
2RF-LO
–70
TA = 85°C
0
CONV GAIN (dB), IIP3 (dBm), NF (dB)
–40
–60
LO-RF
TA = –40°C
4
6
TA = 25°C
–50
6
10
TA = 85°C
–30
LO-IF
8
12
TA = –40°C
POUT
–20
–30
dBm
10
–10
TA = –40°C
14
12
10
–10
TA = 85°C
IIP3
18
dBm
CONV GAIN (dB), NF (dB), IIP3 (dBm)
20
IF Output Power and 2RF-LO Spur
vs RF Input Power
LO Leakage vs LO Frequency
5VDC
12
fLO = 1800MHz
fIF = 570MHz
10
8
RF
–10
LO
–15
–20
6
4
–25
CONV GAIN
4.5, 5.0 AND 5.5VDC
2
–50 –35 –20 –5 10 25 40 55
TEMPERATURE (°C)
70
85
5512 G16
–30
0
500
1000
1500
2000
FREQUENCY (MHz)
2500
5512 G17
5512f
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LT5512
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PI FU CTIO S
NC (Pins 1, 4, 8, 13, 16): Not connected internally. These
pins should be grounded on the circuit board for improved
LO to RF and LO to IF isolation.
RF +, RF – (Pins 2, 3): Differential Inputs for the RF Signal.
These pins must be driven with a differential signal. Each
pin must be connected to a DC ground capable of sinking
15mA (30mA total). This DC bias return can be accomplished through the center-tap of a balun, or with shunt
inductors. An impedance transformation is required to
match the RF input to 50Ω (or 75Ω).
EN (Pin 5): Enable Pin. When the input voltage is higher
than 3V, the mixer circuits supplied through Pins 6, 7, 10,
and 11 are enabled. When the input voltage is less than
0.3V, all circuits are disabled. Typical enable pin input
current is 50µA for EN = 5V and 0µA when EN = 0V.
VCC1 (Pin 6): Power Supply Pin for the LO Buffer Circuits.
Typical current consumption is 22mA. This pin should be
externally connected to the other VCC pins, and decoupled
with 100pF and 0.01µF capacitors.
VCC2 (Pin 7): Power Supply Pin for the Bias Circuits.
Typical current consumption is 4mA. This pin should be
externally connected to the other VCC pins, and decoupled
with 100pF and 0.01µF capacitors.
GND (Pins 9 and 12): Ground. These pins are internally
connected to the backside ground for better isolation.
They should be connected to RF ground on the circuit
board, although they are not intended to replace the
primary grounding through the backside contact of the
package.
IF –, IF + (Pins 10, 11): Differential Outputs for the IF
Signal. An impedance transformation may be required to
match the outputs. These pins must be connected to VCC
through impedance matching inductors, RF chokes or a
transformer center-tap.
LO –, LO + (Pins 14, 15): Differential Inputs for the Local
Oscillator Signal. They can also be driven single-ended by
connecting one to an RF ground through a DC blocking
capacitor. These pins are internally biased to 2V; thus, DC
blocking capacitors are required. An impedance transformation is required to match the LO input to 50Ω (or 75Ω).
GROUND (Pin 17) (Backside Contact): Circuit Ground
Return for the Entire IC. This must be soldered to the
printed circuit board ground plane.
W
BLOCK DIAGRA
BACKSIDE
GROUND
17
+
RF
2
LINEAR
AMPLIFIER DOUBLE-BALANCED
MIXER
15mA
15mA
RF – 3
12 GND
11 IF
+
10 IF –
9 GND
+
LO
15
HIGH-SPEED
LO BUFFER
LO– 14
BIAS
5 EN
6
VCC1
7
VCC2
5512 BD
Figure 1.
5512f
6
LT5512
TEST CIRCUITS
C6
LOIN
1500MHz
TO
2300MHz
C7
RFIN
1700MHz
TO
2100MHz
2
C4
RF
4
TL2
0.018"
13
LO–
NC
GND
+
IF
LT5512
3
3
5
LO
+
14
NC
TL1
4
DC
15
NC
1
T1
1
0.062"
L3
17 16
IF –
NC
GND
EN
6
T2
1
L1
C8
10
IFOUT
170MHz
6
2
C5
4
3
L2
9
NC
VCC1 VCC2
5
GND
12
+ 11
RF –
EN
RF
GND
ER = 4.4
0.018"
7
8
R1
VCC
900MHz MATCHING:
T1 = LDB21881M05C-001
C4 = 3.9pF
L3 = 22nH
C1
C3
C2
GND
5512 F02
REF DES
VALUE
SIZE
PART NUMBER
REF DES
VALUE
SIZE
PART NUMBER
C1, C5, C6, C7
100pF
0402
Murata GRP1555C1H101J
L1, L2
47nH
0402
Coilcraft 0402CS-47NX
C2
0.01µF
0402
Murata GRP155R71C103K
L3
5.6nH
0402
Toko LL1005-FH5N6
0402
C3
1.0µF
0603
Taiyo Yuden LMK107F105ZA
R1
10
C4
1.5pF
0402
Murata GRP1555C1H1R5C
T1
2:1
Murata LDB211G9010C-001
C8
6.8pF
0402
Murata GRP1555C1H6R8D
T2
8:1
Mini-Circuits TC8-1
TL1, TL2
θ = 8.1°
ZO = 72Ω
(W = 0.4mm, L = 2mm)
Figure 2. Test Schematic for 1900MHz Downconverter (PCS/UMTS Applications)
C6
LOIN
1500MHz
TO
2100MHz
C7
L3
17 16
RFIN
1230MHz
1
T1
2
6
3
TL1
2
C4
3
4
1
5
N/C
TL2
4
NC
LO
+
14
LO–
13
NC
NC
RF
GND
+
IF
LT5512
T2
L1
+ 11
GND
NC
5
12
C9
C5
IFOUT
270MHz
TO
870MHz
6
1
2
10
IF –
RF –
EN
EN
15
C10
3
9
4
L2
VCC1 VCC2 NC
6
7
8
R1
VCC
C1
C3
C2
GND
5512 F03
REF DES
VALUE
SIZE
PART NUMBER
C1, C5, C6,
REF DES
VALUE
SIZE
PART NUMBER
L1, L2
12nH
0402
Toko LL1005-FH12N
L3
8.2nH
0402
Toko LL1005-FH8N2
0402
C7, C9, C10
100pF
0402
Murata GRP1555C1H101J
C2
0.01µF
0402
Murata GRP155R71C103K
R1
10
C3
1.0µF
0603
Taiyo Yuden LMK107F105ZA
T1
1:1
Murata LDB311G2705C-428
C4
2.7pF
0402
Murata GRP1555C1H2R7C
T2
4:1
M/A-COM ETC1.6-4-2-3
TL1, TL2
ZO = 72Ω
θ = 5.4°
(W = 0.4mm, L = 2.0mm)
Figure 3. Test Schematic for 1230MHz Downconverter (Cable Infrastructure Downlink Transmitter Applications)
5512f
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LT5512
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APPLICATIO S I FOR ATIO
The LT5512 consists of a double-balanced mixer, RF
buffer amplifier, high-speed limiting LO buffer, and bias/
enable circuits. The RF, LO and IF ports are differential. All
three ports can be matched from 1kHz to 3GHz, although
the IC has been optimized for downconverter applications
where the RF and LO input signals are high frequency and
the IF output frequency ranges from 1kHz up to 2GHz. Low
side or high side LO injection can be used.
RF Input Port
The RF input buffer has been designed to simplify impedance matching while improving LO-RF isolation and noise
figure. A simplified schematic is shown in Figure 4 with the
associated external impedance matching elements for a
1.9GHz application. Each RF input requires a low resistance DC return to ground capable of sinking 15mA. This
can be accomplished with the center-tap of a balun as
shown in Figure 4, or bias chokes connected from Pins 2
and 3 to ground.
differential input impedance up to the desired value for the
balun input. The following example shows how to design
the low-pass impedance transformation network for the
RF input.
From Table 1, the differential input impedance at 1900MHz
is 20.6 + j22.8. As shown in Figure 5, the 22.8Ω reactance
is split, with one half on each side of the 20.6Ω load
resistor. The matching network will consist of additional
inductance in series with the internal inductance and a
capacitor in parallel with the desired 100Ω source impedance. The capacitance (C4) and inductance are calculated
as follows.
n = RS/RL = 100/20.6 = 4.85
Q = √n – 1 = 1.963
XC = RS/Q = 100/1.963 = 50.9Ω
C4 = 1/(ωXc) = 1.6pF (use 1.5pF)
XL = (RL • Q) = (20.6 • 1.963) = 40.4Ω
XEXT = XL – XINT = 40.4 – 22.8 = 17.6Ω
LT5512
VBIAS
VCC
15mA
15mA
2
3
TL1
ZO = 72Ω
θ = 8.1° AT 1.9GHz
TL2
ZO = 72Ω
θ = 8.1° AT 1.9GHz
C4
1.5pF
1
2
The external inductance is split in half (0.74nH), with each
half connected between the pin and the shunt capacitor, as
shown in Figure 5. The inductance is implemented with
short (2mm) high-impedance printed transmission lines,
which yield a compact board layout. Finally, the 2:1balun
transforms the 100Ω differential impedance down to a
50Ω single-ended input for the RF signal.
Table 1. RF Input Differential Impedance
100Ω
4
LEXT = (XEXT/ω) = 1.47nH
3
5
T1
1:2
RFIN LDB211G9010C-001
50Ω
5512 F04
Figure 4. RF Input with External
Matching for a 1.9GHz Application
Table 1 lists the differential input impedance and differential reflection coefficient between Pins 2 and 3 for several
common RF frequencies. As shown in Figures 4 and 5,
low-pass impedance matching is used to transform the
Frequency
Differential Input
(MHz)
Impedance
Mag
Differential S11
Angle
10
18.2 + j0.14
0.467
179.6
44
18.0 + j0.26
0.470
178.6
240
18.1 + j2.8
0.471
172.6
450
18.1 + j5.2
0.473
166.3
950
18.7 + j11.3
0.479
150.8
1900
20.6 + j22.8
0.503
124.3
2150
21.4 + j26.5
0.512
116.9
2450
22.5 + j30.5
0.522
109.2
2700
24.1 + j34.7
0.530
101.7
5512f
8
LT5512
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APPLICATIO S I FOR ATIO
1/2 XEXT
2
RS
100Ω
C4
Table 2. LO Input Differential Impedance
1/2 XINT
1/2 XEXT
j11.4
RL
20.6Ω
1/2 XINT
3
j11.4
LT5512
Frequency
Differential Input
Differential S11
(MHz)
Impedance
Mag
Angle
750
263 – j172
0.766
–10.2
1000
213 – j178
0.760
–13.4
1250
175 – j173
0.752
–16.6
1500
146 – j164
0.743
–19.8
1750
125 – j153
0.733
–22.8
2000
108 – j142
0.722
–25.8
2250
95 – j131
0.709
–28.9
2500
86 – j122
0.695
–31.8
2750
78 – j113
0.68
–34.6
5512 F05
Figure 5. 1.9GHz RF Input Matching
It is also possible to eliminate the RF balun and drive the
RF inputs differentially. In this case, inductors from Pins
2 and 3 to ground would be required to bias the input
stage. The value of the inductors should be high enough to
avoid reducing the input impedance at the frequency of
interest.
LO Input Port
The LO buffer amplifier consists of high-speed limiting
differential amplifiers, designed to drive the mixer quad for
high linearity. The LO+ and LO– pins are designed for
differential or single-ended drive. An external balun is
optional. Both LO pins are internally biased to 2VDC.
The LO input has been designed for simple impedance
matching for frequencies up to 3GHz. A simplified schematic is shown in Figure 6 with the associated external
impedance matching. The matching technique is similar
to that described earlier for the RF port, except the match
is not nearly as critical. Table 2 lists the differential input
impedance and differential reflection coefficient between
the LO+ and LO– pins (Pin 15 to Pin 14). As shown, the real
part of the series impedance is close to 100Ω. Series
inductors (L3, L4) are used to tune out the capacitive
portion of the differential impedance.
T3
1:2
LDB211G9010C-001
LOIN
50Ω
1
4
LO +
15
Single-ended LO drive can be used if a differential LO
source is not available, or the added expense of a LO balun
is undesirable. In this case, one LO input is AC-coupled to
ground through a 100pf DC blocking capacitor as shown
in Figure 7. The other input is matched to 50Ω using a
series inductor and a second DC blocking capacitor. The
LT5512 is characterized and production tested with singleended LO drive.
L3
LOIN
50Ω
2V
LO +
15
C6
100pF
VCC
C7
100pF
14
LO –
LT5512
5512 F07
Figure 7. Single-Ended LO Input Matching
The differential port impedance listed in Table 2 can be
used to compute the value of the series matching inductor,
L3. Alternatively, Figure 8 shows measured LO input
return loss for various values of L3.
2V
L3
C11
VCC
2
5
3
L4
14
LO –
LT5512
5512 F06
Figure 6. LO Input with External Matching Elements
5512f
9
LT5512
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APPLICATIO S I FOR ATIO
An alternative matching network for a broadband CATV IF
(270MHz to 870MHz) is shown in Figure 3. Here, a lowpass impedance transformer consisting of the internal
capacitance, with L1 and L2, transforms the 371Ω output
resistance at 870MHz to 200Ω. A 4:1 balun then completes the match down to 50Ω. Supply voltage is applied
through the center-tap of the transformer.
0
RETURN LOSS (dB)
–5
–10
4.7nH
5.6nH
6.8nH
–15
–20
8.2nH
–25
Table 3. IF Output Differential Impedance (Parallel Equivalent)
10nH
–30
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (MHz)
1573 F08
Figure 8. Single-Ended LO Port Return Loss
vs Frequency for Various Values of L3
IF Output Port
The IF outputs, IF + and IF –, are internally connected to the
collectors of the mixer switching transistors as shown in
Figure 9. These differential outputs should be combined
externally through an RF balun or 180° hybrid to achieve
optimum performance. Both pins must be biased at the
supply voltage, which can be applied through matching
inductors (see Figure 2), or through the center-tap of an
output transformer (see Figure 3). These pins are protected with ESD diodes; the diodes allow peak AC signal
swing up to 1.3V above VCC.
As shown in Table 3, the IF output differential impedance
is approximately 390Ω in parallel with 0.44pF. A simple
band-pass IF matching network suitable for wireless applications is shown in Figure 9. Here, L1, L2 and C8 set the
desired IF output frequency. The 390Ω differential output
can then be applied directly to a differential filter, or an 8:1
balun for impedance transformation down to 50Ω. To
achieve maximum linearity, C8 should be located as close
as possible to the IF+/IF– pins. Even small amounts of
inductance in series with C8 (such as through a via) can
significantly degrade IIP3. For high IF frequencies, the
value of C8 should be reduced by the value of internal
capacitance (see Table␣ 3).This matching network is simple
and offers good selectivity for narrow band IF applications.
Frequency
Differential Output
(MHz)
Impedance
Mag
Differential S11
10
396 || – j10k
0.766
0
70
394 || – j5445
0.775
–1.1
170
393 || – j2112
0.774
–2.8
240
392 || – j1507
0.773
–3.9
450
387 || – j798
0.772
–7.3
750
377 || – j478
0.768
–12.2
Angle
860
371 || – j416
0.766
–14.0
1000
363 || – j359
0.762
–16.2
1250
363 || – j295
0.764
–19.6
1500
346 || – j244
0.756
–23.6
1900
317 || – j192
0.743
–29.9
LT5512
11
IF+
L1
400Ω
TO
VCC DIFFERENTIAL
FILTER OR
BALUN
C8
L2
10
IF–
5512 F09
Figure 9. IF Output Equivalent Circuit
with Band-Pass Matching Elements
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LT5512
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PACKAGE DESCRIPTIO
UF16 Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.15 ± 0.05
2.90 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BCS
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
4.00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.55 ± 0.20
15
16
PIN 1
1
2.15 ± 0.10
(4-SIDES)
2
(UF) QFN 0102
0.200 REF
0.00 – 0.05
0.30 ± 0.05
0.65 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5512f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LT5512
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APPLICATIO S I FOR ATIO
5512 F10b
5512 F10a
Figure 10. 1900MHz Evaluation Board Layout
5512 F11
Figure 11. 1230MHz Cable Infrastructure Evaluation Board Layout
(Wide Output Range Down-Converting Mixer for Downlink Transmitter)
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Precision VOUT Offset Control, Adjustable Gain and Offset Voltage
5512f
12
Linear Technology Corporation
LT/TP 1103 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002