LTC1773 Synchronous Step-Down DC/DC Controller U FEATURES DESCRIPTIO ■ The LTC®1773 is a current mode synchronous buck regulator controller that drives external complementary power MOSFETs using a fixed frequency architecture. The operating supply range is from 2.65V to 8.5V, making it suitable for 1- or 2-cell lithium-ion battery powered applications. Burst Mode® operation provides high efficiency at low load currents. 100% duty cycle provides low dropout operation which extends operating time in battery-operated systems. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Efficiency: Up to 95% Constant Frequency 550kHz Operation VIN from 2.65V to 8.5V VOUT from 0.8V to VIN OPTI-LOOP® Compensation Minimizes COUT Synchronizable up to 750kHz Selectable Burst Mode Operation µA Low Quiescent Current: 80µ Low Dropout Operation: 100% Duty Cycle Secondary Winding Regulation Soft-Start Current Mode Operation for Excellent Line and Load Transient Response Low Shutdown IQ = 10µA ±1.5% Reference Accuracy Precision 2.5V Undervoltage Lockout Available in 10-Lead MSOP The operating frequency is internally set at 550kHz, allowing the use of small surface mount inductors. For switching-noise sensitive applications, it can be synchronized up to 750kHz. Peak current limit is user programmable with an external high side sense resistor. A SYNC/FCB control pin guarantees regulation of secondary windings regardless of load on the main output by forcing continuous operation. Burst Mode operation is inhibited during synchronization or when the SYNC/FCB pin is pulled low to reduce noise and RF interference. Soft-start is provided by an external capacitor. U APPLICATIO S ■ ■ ■ ■ ■ ■ Cellular Telephones RF PA Supplies Portable Instruments Wireless MODEMS Distributed Power Systems Notebook and Palm Top Computers, PDAs Single and Dual Cell Lithium-Ion Powered Devices Synchronous rectification increases efficiency and eliminates the need for a Schottky diode, saving components and board space. The LTC1773 comes in a 10-lead MSOP package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815. U ■ TYPICAL APPLICATIO VIN 2.65V TO 8.5V High Efficiency 100 + VIN SYNC/FCB 90 ITH 47pF 220pF L1 3µH TG LTC1773 30k SW VFB GND VOUT 2.5V BG Si9801DY + COUT 180µF 80.6k VIN = 5V 85 VIN = 8V 80 75 70 65 60 L = SUMIDA CDRH6D28-3R0 55 169k 1773 F01 Figure 1. Step-Down Converter EFFICIENCY (%) RUN/SS SENSE– 0.1µF VIN = 3.3V 95 CIN 68µF RSENSE 0.025Ω 1 100 1000 10 OUTPUT CURRENT (mA) 5000 1773 F1b 1773fb 1 LTC1773 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage .............................. –0.3V to 10.0V ITH Voltage ................................................ –0.3V to 2.5V RUN/SS, VFB, SENSE– Voltages .................. –0.3V to VIN SYNC/FCB Voltage ...................................... –0.3V to VIN BG, TG Voltages...........................................–0.3V to VIN SW Voltage ...................................................– 5V to 11V Operating Ambient Temperature Range (Note 2) ...............................................–40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec.)................. 300°C ORDER PART NUMBER TOP VIEW ITH RUN/SS SYNC/FCB VFB GND 1 2 3 4 5 10 9 8 7 6 SW SENSE– VIN TG BG LTC1773EMS MS PART MARKING MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 120°C/W LTMV Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, TA = 25°C. VIN = 5V unless otherwise specified. SYMBOL PARAMETER IVFB Feedback Current (Note 4) VFB Regulated Feedback Voltage (Note 4) ∆VOVL ∆Output Overvoltage Lockout ∆VOVL = VOVL – VFB ∆VFB Reference Voltage Line Regulation VIN = 2.7V to 8.5V (Note 4) VLOADREG Output Voltage Load Regulation ITH at 1.0V (Note 4) IS CONDITIONS MIN TYP 20 60 nA 0.788 0.80 0.812 V 40 60 80 mV 0.002 0.02 %/V 0.2 0.8 % ITH at 0.6V (Note 4) –0.2 –0.8 % Input DC Bias Current Normal Mode (Note 5) VIN = 5V, VITH = OPEN, VSYNC/MODE = OPEN 400 600 Burst Mode Operation VITH = 0V, VIN = 5V, VSYNC/MODE = OPEN 80 Shutdown VRUN/SS = 0V, 2.7V < VIN < 8.5V 10 Shutdown VRUN/SS = 0V, VIN < 2.4V ● MAX UNITS µA µA 30 µA 2 5 µA 0.4 0.7 1.0 V VRUN/SS = 0V 0.75 1.5 2.5 µA Auxiliary Feedback Threshold VSYNC/FCB Ramping Negative 0.76 0.8 0.84 V SYNC/FCB Pull-Up Current VSYNC/FCB = 0V 0.1 0.4 1.0 µA fOSC Oscillator Frequency VFB = 0.8V 500 550 600 kHz VUVLO Undervoltage Lockout 2.35 2.5 2.65 V 2.65 2.8 V VRUN/SS RUN/SS Threshold IRUN/SS Soft-Start Current Source VSYNC/FCB ISYNC/FCB VFB = 0V ∆VSENSE(MAX) 55 VIN Ramping Down from 3V ● VIN Ramping Up from 0V ● Maximum Current Sense Voltage ● 85 kHz 100 115 mV TG tr Top Gate Drive Rise Time CLOAD = 3000pF (Note 6) 45 160 ns TG tf Top Gate Drive Fall Time CLOAD = 3000pF (Note 6) 48 150 ns BG tr Bottom Gate Drive Rise Time CLOAD = 3000pF (Note 6) 80 180 ns BG tf Bottom Gate Drive Fall Time CLOAD = 3000pF (Note 6) 45 150 ns 1773fb 2 LTC1773 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC1773 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC1773: TJ = TA + (PD • 120°C/W) Note 4: The LTC1773 is tested in a feedback loop which servos VFB to the balance point for the error amplifier (VITH = 0.8V) Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: Rise and fall times are measured using 10% and 90% levels. U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Load Current Efficiency vs Load Current VIN = 5V 100 VOUT = 2.5V SEE FIGURE 1 VIN = 3.3V Burst Mode OPERATION 70 SYNC(750kHz) EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) 95 90 80 VIN = 5V 80 VIN = 8V 70 FORCED CONTINUOUS 50 10 100 1000 OUTPUT CURRENT (mA) 1 75 50 1 5000 10 100 1000 OUTPUT CURRENT (mA) 2 10,000 500 RSENSE = 0.025Ω 350 VOUT = 1.8V Si9801DY RSENSE = 0.025Ω SEE FIGURE 1 – 0.05 450 INPUT CURRENT (µA) VIN-VOUT (mV) 250 200 150 100 – 0.25 2.5 1.0 1.5 2.0 LOAD CURRENT (A) 3.0 3.5 1773 G16 SYNC TO 750kHz 400 300 – 0.20 10 Input and Shutdown Currents vs Input Voltage 400 0 – 0.15 6 8 INPUT VOLTAGE (V) 1773 G03 VIN-VOUT Dropout Voltage vs Load Current – 0.10 4 1773 G02 Load Regulation 0.5 85 IOUT = 100mA 1773 G01 0 IOUT = 1A 90 80 60 60 – 0.30 VOUT = 2.5V SEE FIGURE 1 VOUT = 2.5V SEE FIGURE 1 100 90 NORMALIZED VOUT (%) Efficiency vs Input Voltage 100 350 VOUT = 1.8V Si9801DY RSENSE = 0.025Ω L = CDRH6D28-3RO 300 250 200 Burst Mode OPERATION 150 100 50 50 0 0 0 500 1500 2000 1000 LOAD CURRENT (mA) 2500 1773 G05 SHUTDOWN 2 4 8 6 INPUT VOLTAGE (V) 10 1773 G06 1773fb 3 LTC1773 U W TYPICAL PERFOR A CE CHARACTERISTICS 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 VRUN/SS (V) 3.5 4.0 105 100 95 85 – 60 – 40 – 20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 1773 G07 100 80 60 Burst Mode OPERATION 40 20 0 560 2.5 550 2.0 540 530 520 – 60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FORCED CONTINUOUS 0 0.2 0.4 0.6 0.8 1.0 VITH (V) 1.2 1.4 1.6 1773 G09 RUN/SS Pin Current vs Temperature RUN/SS CURRENT (µA) FREQUENCY (kHz) 120 1773 G08 Oscillator Frequency vs Temperature Burst Mode Operation ILOAD = 100mA SEE FIGURE 9 VOUT 20mV/DIV 1.5 IL 500mA/DIV 1.0 0.5 – 60 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) VIN = 5V VOUT = 2.5V 20µs/DIV 1773 G12 1773 G11 1773 G10 Load Step (Burst Mode Operation) Start-Up VOUT 2V/DIV Maximum Current Sense Threshold vs VITH MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs VRUN/SS Load Step (Continuous Mode) SEE FIGURE 9 SEE FIGURE 9 SEE FIGURE 9 VOUT 100mV/DIV VOUT 100mV/DIV IL 2A/DIV IL 2A/DIV VRUN/SS 1V/DIV IL 2A/DIV VIN = 5V VOUT = 2.5V 40ms/DIV 1773 G13 VIN = 5V 100µs/DIV VOUT = 2.5V 100mA TO 5A LOAD STEP 1773 G14 100µs/DIV VIN = 5V VOUT = 2.5V 100mA TO 5A LOAD STEP 1773 G15 1773fb 4 LTC1773 U U U PIN FUNCTIONS ITH (Pin 1): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.2V. Under high duty cycle and nearing current limit, ITH can swing up to 2.4V. RUN/SS (Pin 2): Combination of Soft-Start and Run Control Inputs. A capacitor to ground at this pin sets the ramp time to full current output. The time is approximately 0.8s/µF. Forcing this pin below 0.4V shuts down all the circuitry. SYNC/FCB (Pin 3): Multifunction Pin. This pin performs three functions: 1) secondary winding feedback input, 2) external clock synchronization and 3) Burst Mode operation or forced continuous mode select. For secondary winding applications, connect to a resistive divider from the secondary output. To synchronize with an external clock, apply a TTL/CMOS compatible clock with a frequency between 585kHz and 750kHz. To select Burst Mode operation, tie SYNC/FCB to VIN. Grounding this pin forces continuous operation. VFB (Pin 4): Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. Do not use more than 0.01µF of feedforward capacitance from FB to the output. GND (Pin 5): Ground Pin. BG (Pin 6): Bottom Gate Driver of External N-Channel Power MOSFET. This pin swings from 0V to VIN. TG (Pin 7): Top Gate Driver of External P-Channel Power MOSFET. This pin swings from 0V to VIN. VIN (Pin 8) : Main Supply Pin. Must be closely decoupled to GND (pin 5). SENSE–(Pin 9): The Negative Input to the Current Comparator. A sense resistor between this pin and VIN sets the peak current in the top switch. Connect this pin to the source of the external P-Channel power MOSFET. SW (Pin 10): Switch Node Connection to Inductor. This pin connects to the drains of the external main and synchronous power MOSFET switches. W FUNCTIONAL DIAGRA U BURST DEFEAT X 0.4µA Y = “0” ONLY WHEN X IS A CONSTANT “1” Y SLOPE COMP SYNC/FCB 3 8 VIN OSC – SYNC DEFEAT EN + 0.8V FREQ SHIFT 1.5µA + UVLO TRIP = 2.5V ICOMP BURST COMP ITH 1 RUN/ RUN/SOFT SOFT-START START – OVDET 0.86V + 0.22V – 0.8V REF 2 RUN/SS SLEEP 50mV EA + – – S Q R Q SWITCHING LOGIC AND BLANKING CIRCUIT 7 TG ANTI SHOOT-THRU + 6 BG SHUTDOWN 5 GND IRCMP – FCB + 10 SW – 0.8V + 4 + VFB 9 SENSE – – 0.6V 0.4V Figure 2. 1773 FD 1773fb 5 U LTC1773 U OPERATIO (Refer to Functional Diagram) Main Control Loop The LTC1773 uses a constant frequency, current mode step- down architecture to drive an external pair of complementary power MOSFETs. During normal operation, the external top P-channel power MOSFET turns on each cycle when the oscillator sets the RS latch, and turns off when the current comparator ICOMP resets the RS latch. The peak inductor current at which ICOMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of error amplifier EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.8V reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom N-channel MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next cycle. The main control loop is shut down by pulling the RUN/SS pin low. Releasing RUN/SS allows an internal 1.5µA current source to charge the external soft-start capacitor CSS. When CSS reaches 0.7V, the main control loop is enabled with the internal buffered ITH voltage clamped at approximately 5% of its maximum value. As CSS continues to charge, the internal buffered ITH is gradually released allowing normal operation to resume. An overvoltage comparator, 0V, guards against transient overshoots (>7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Burst Mode Operation The LTC1773 is capable of Burst Mode operation in which the external power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply allow the SYNC/FCB pin to float or connect it to a logic high. To disable Burst Mode operation and force continuous mode, connect the SYNC/FCB pin to GND. The threshold voltage between Burst Mode operation and forced continuous mode is 0.8V. This can be used to assist in secondary winding regulation as described in Auxiliary Winding Control Using SYNC/FCB Pin in the Applications Information section. When the converter operates in Burst Mode operation the peak current of the inductor is set to approximately a third of the maximum peak current value during normal operation even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the ITH voltage drops below 0.22V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. The circuit enters sleep mode with both power MOSFETs turned off. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 80µA. The load current is now being supplied from the output capacitor. When the output voltage drops, causing ITH to rise above 0.27V, the internal sleep line goes low, and the LTC1773 resumes normal operation. The next oscillator cycle will turn on the external top MOSFET and the switching cycle repeats. Short-Circuit Protection When the output is shorted to ground, the frequency of the oscillator is reduced to about 55kHz, 1/10 the nominal frequency. This frequency foldback ensures that the inductor current has more time to decay, thereby preventing runaway. The oscillator’s frequency will gradually increase to 550kHz after VFB rises above 0.4V. Frequency Synchronization The LTC1773 can be synchronized with an external TTL/ CMOS compatible clock signal. The frequency range of this signal must be from 585kHz to 750kHz. Do not synchronize the LTC1773 below 585kHz as this may cause abnormal operation and an undesired frequency spectrum. The top MOSFET turn-on follows the rising edge of the external source. When the LTC1773 is clocked by an external source, Burst Mode operation is disabled; the LTC1773 then operates in PWM pulse skipping mode preventing current reversal. In this mode, when the output load is very low, current comparator ICOMP remains tripped for more than one cycle 1773fb 6 LTC1773 U OPERATIO (Refer to Functional Diagram) and forces the main switch to stay off for the same number of cycles. Increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency PWM. Frequency synchronization is inhibited when the feedback voltage, VFB, is below 0.6V. This prevents the external clock from interfering with the frequency foldback for short-circuit protection. Low Supply Operation The LTC1773 is designed to operate down to a 2.65V supply voltage. For proper operation at this low input voltage, sub-logic level MOSFETs are required. When the value of the output voltage is very close to the input voltage, the converter is running at high duty cycles or in dropout where the main switch is on continuously. See Efficiency Considerations in the Applications Information section. Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the IR voltage drop across the external P-channel MOSFET, sense resistor, and the inductor. Undervoltage Lockout A precision undervoltage lockout shuts down the LTC1773 when VIN drops below 2.5V, making it ideal for single lithium-ion battery applications. In shutdown, the LTC1773 draws only several microamperes, which is low enough to prevent deep discharge and possible damage to the lithiumion battery that’s nearing its end of charge. A 150mV hysteresis ensures reliable operation with noisy supplies. Slope Compensation and Inductor Peak Current Slope compensation provides stability by preventing subharmonic oscillations. It works by internally adding a ramp to the inductor current signal at duty cycles in excess of 30%. This causes the internal current comparator to trip earlier. The ITH clamp level is also reached earlier than conditions in which the duty cycle is below 30%. As a result, the maximum inductor peak current is lower for VOUT/VIN > 0.3 than when VOUT/VIN < 0.3. To compensate for this loss in maximum inductor peak current during high duty cycles, the LTC1773 uses a patent pending scheme that raises the ITH clamp level (proportional to the amount of slope compensation) when duty cycle is above 30%. U W U U APPLICATIONS INFORMATION The basic LTC1773 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, L can be chosen, followed by the external power MOSFETs. Finally, CIN and COUT are selected. average output current IMAX equal to the peak value less half the peak-to-peak ripple current ∆IL. RSENSE Selection for Output Current Inductor Value Calculation RSENSE is chosen based on the required output current. The LTC1773 current comparator has a maximum threshold of 100mV/RSENSE. The current comparator threshold sets the peak of the inductor current, yielding a maximum The inductor selection will depend on the operating frequency of the LTC1773. The internal preset frequency is 550kHz, but can be externally synchronized up to 750kHz. Allowing a margin for variations in the LTC1773 and external component values yields: RSENSE = 70mV/IMAX 1773fb 7 LTC1773 U W U U APPLICATIONS INFORMATION The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. However, operating at a higher frequency generally results in lower efficiency because of external MOSFET gate charge losses. The inductor value has a direct effect on ripple current. The ripple current, ∆IL, decreases with higher inductance or frequency and increases with higher VIN or VOUT. ∆IL = ⎛ V ⎞ VOUT ⎜ 1– OUT ⎟ VIN ⎠ ⎝ f L 1 ( )( ) inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available which do not increase the height significantly. (1) Accepting larger values of ∆IL allows the use of lower inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is 30% to 40% of IMAX. Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 1/3 its original value. Lower inductor values (higher ∆IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in Power MOSFET and Schottky Diode Selection Two external power MOSFETs must be selected for use with the LTC1773: a P-channel MOSFET for the top (main) switch, and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the VIN voltage. Therefore, for VIN > 5V, logic-level threshold MOSFETs should be used. But, for VIN < 5V, sub-logic level threshold MOSFETs (VGS(TH) < 3V) should be used. In these applications, make sure that the VIN to the LTC1773 is less than 8V because the absolute maximum VGS rating of the majority of these sub-logic threshold MOSFETs is 8V. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage, maximum output current, and total gate charge. When the LTC1773 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT/VIN Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN The MOSFET power dissipations at maximum output current are given by: PMAIN = VOUT 2 IMAX ) (1 + δ )RDSON + ( VIN K(VIN ) (IMAX )(C RSS )( f) 2 1773fb 8 LTC1773 U W U U APPLICATIONS INFORMATION PSYNC = VIN – VOUT 2 IMAX ) (1 + δ )RDS(ON) ( VIN where δ is the temperature dependency of RDS(ON) and K is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside P-channel equation includes an additional term for transition losses, which are highest at high input voltages. The synchronous MOSFET losses are greatest at high input voltage or during a short-circuit when the duty cycle in this switch is nearly 100%. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant K = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. Typical gate charge for the selected P-channel MOSFET should be less than 30nC (at 4.5VGS) while the turn-off delay should be less than 150ns. However, due to differences in test and specification methods of various MOSFET manufacturers, the P-channel MOSFET ultimately should be evaluated in the actual LTC1773 application circuit to ensure proper operation. A Schottky diode can be placed in parallel with the synchronous MOSFET to improve efficiency. It conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 1A Schottky is generally a good size for 5A to 8A regulators due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. CIN Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: 12 VOUT (VIN – VOUT )] [ CIN required IRMS ≅ IMAX VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. COUT Selection The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement is satisfied the capacitance is adequate for filtering. The output ripple (∆VOUT) is determined by: ⎛ 1 ⎞ ∆VOUT ≅ ∆IL ⎜ ESR + ⎟ 8fC OUT ⎠ ⎝ where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. With ∆IL = 0.4IOUT(MAX) and allowing for 2/3 of the ripple due to ESR, the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2 RSENSE COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output voltage does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. 1773fb 9 LTC1773 U W U U APPLICATIONS INFORMATION The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR/size ratio of any aluminum electrolytic at a somewhat higher price. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. In surface mount applications multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo OS-CON and POSCAP, Nichicon PL series, Panisonic SP series and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Output Voltage Programming The output voltage is set by a resistive divider according to the following formula: ⎛ R2⎞ VOUT = 0.8V⎜ 1 + ⎟ ⎝ R1⎠ Run/Soft-Start Function The RUN/SS pin is a dual purpose pin that provides the soft-start function and a means to shut down the LTC1773. Soft-start reduces surge currents from VIN by gradually increasing the internal current limit. Power supply sequencing can also be accomplished using this pin. An internal 1.5µA current source charges up an external capacitor CSS. When the voltage on RUN/SS reaches 0.7V the LTC1773 begins operating. As the voltage on RUN/SS continues to ramp from 0.7V to 1.8V, the ITH clamp is also ramped at a proportionally linear rate. Depending on the external RSENSE used, the peak inductor current, and thus the internal current limit, rises with the RUN/SS voltage. The output current thus ramps up slowly, charging the output capacitor. If RUN/SS has been pulled all the way to ground, there will be a delay before the current starts increasing and is given by: t DELAY = ( ) 0.7 C SS = 0.47s / µF C SS 1.5µA Pulling the RUN/SS pin below 0.4V puts the LTC1773 into a low quiescent current shutdown mode (IQ < 10µA). This pin can be driven directly from logic as shown in Figure 4. Diode D1 in Figure 4 reduces the start delay but allows CSS to ramp up slowly providing the soft-start function. This diode can be deleted if soft-start is not needed. 3.3V OR 5V RUN/SS RUN/SS D1 (2) CSS CSS The external resistive divider is connected to the output as shown in Figure 3, allowing remote voltage sensing. 1773 F04 Figure 4. RUN/SS Pin Interfacing 0.8V ≤ VOUT ≤ 8.5V Auxiliary Winding Control Using SYNC/FCB Pin R2 VFB R1 LTC1773 GND 1773 F03 Figure 3. Setting the LTC1773 Output Voltage The SYNC/FCB pin can be used as a secondary feedback to provide a means of regulating a flyback winding output. When this pin drops below its ground referenced 0.8V threshold, continuous mode operation is forced. In continuous mode, the P-channel main and N-channel synchronous switches are switched continuously regardless of the load on the main output. 1773fb 10 LTC1773 U W U U APPLICATIONS INFORMATION Synchronous switching removes the normal limitation that power must be drawn from the inductor primary winding in order to extract power from auxiliary windings. With continuous synchronous operation, power can be drawn from the auxiliary windings without regard to the primary output load. The secondary output voltage is set by the turns ratio of the transformer in conjunction with a pair of external resistors returned to the SYNC/FCB pin as shown in Figure 5. The secondary regulated voltage, VSEC, in Figure 5 is given by: ⎛ R4 ⎞ VSEC ≅ (N + 1)VOUT − VDIODE > 0.8V⎜ 1 + ⎟ ⎝ R3 ⎠ where N is the turns ratio of the transformer and VOUT is the main output voltage sensed by VFB. VIN LTC1773 R4 TG VSEC + L1 1:N 1µF VOUT SYNC/FCB R3 SW + BG COUT 1773 F05 Figure 5. Secondary Output Loop Connection Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1773 circuits: VIN quiescent current, external power MOSFET gate charge current, I2R losses, and topside MOSFET transition losses. 1. The VIN quiescent current is due to the DC bias current as given in the electrical characteristics, it excludes MOSFET driver and control currents. VIN current results in a small loss which increases with VIN. 2. The external MOSFET gate charge current results from switching the gate capacitance of the external power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is the current out of VIN; it is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the external main and synchronous switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 3. I2R losses are calculated from the resistances of the external RSENSE, the external power MOSFETs (RSW) and the external inductor (RL). In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin from L is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC), as follows: RSW = (RDS(ON)TOP +RSENSE) • DC + RDS(ON)BOT • (1 – DC) Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. The RDS(ON) for both the top and bottom MOSFETs can be obtained from the MOSFET manufactures’s datasheets. Thus, to obtain I2R losses, simply add RSW and RL together and multiply their sum by the square of the average output current. 4. Transition losses apply to the topside MOSFET and increase when operating at high input voltages and higher operating frequencies. Transition losses can be estimated from: Transition Loss = 2(VIN)2IO(MAX)CRSS(f) 1773fb 11 LTC1773 U W U U APPLICATIONS INFORMATION Other losses including CIN and COUT ESR dissipative losses, and inductor core losses, generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD)(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then returns VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and an AC filtered closed-loop response test point. The DC step, rise time and settling at this test point reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/ DC ratio cannot be used to determine phase margin. The gain of the loop will be increased by increasing RC, and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time that the LTC1773 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. The minimum on-time for the LTC1773 is about 250ns. Low duty cycle and high frequency synchronous applications may approach this minimum on-time limit and care should be taken to ensure that: t ON(MIN)< VOUT f • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1773 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. If an application can operate close to the minimum ontime limit, an inductor must be chosen that has low enough inductance to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current equal or greater than 30% of the IOUT(MAX) at VIN(MAX). 1773fb 12 LTC1773 U U W U APPLICATIONS INFORMATION PC Board Layout Checklist Design Example When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1773. These items are also illustrated graphically in the layout diagram of Figure 6. Check the following in your layout: As a design example, assume the LTC1773 is used in a single lithium-ion battery powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 2A but most of the time it will be on standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 2.5V. With this information we can calculate RSENSE to be around 33mΩ. For the inductor L, using equation (1), 1) Are the signal and power grounds segregated? The LTC1773 signal ground consists of the resistive divider, the compensation network and CSS. The power ground consists of the (–) plate of CIN, the (–) plate of COUT, the source of the external synchronous NMOS, and Pin 5 of the LTC1773. The power ground traces should be kept short, direct and wide. Connect the synchronous MOSFETs source directly to the input capacitor ground. 2) Does the VFB pin connect directly to the feedback resistors? The resistive divider of R1 and R2 must be connected between the (+) plate of COUT and signal ground. Be careful locating the feedback resistors too far away from the LTC1773. The VFB line should not be routed close to any other nodes with high slew rates. 3) Does the (+) terminal of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the external power MOSFETs. 4) Keep the switching nodes SW, TG and BG away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. L= ⎛ V ⎞ VOUT ⎜ 1 – OUT ⎟ VIN ⎠ ⎝ f ∆IL 1 ( )( ) (3) Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL = 800mA and f = 550kHz in equation (3) gives: L= ⎛ 2.5V ⎞ 2.5V ⎟ = 2.3µH ⎜1– 550kHz (800mA) ⎝ 4.2V ⎠ A 2.5µH inductor works well for this application. For good efficiency choose a 4A inductor with less than 0.1Ω series resistance. CIN will require an RMS current rating of at least 1A at temperature and COUT will require an ESR of less than 0.066Ω. In most applications, the requirements for these capacitors are fairly similar. CC2 + CC1 RC 1 ITH SW 10 RSENSE 9 RUN/SS SENSE– LTC1773 8 3 VIN SYNC/FCB + 2 CSS R1 4 5 VFB GND TG BG D1 CIN VIN Q1 7 Q2 6 – R2 – + COUT L1 VOUT + BOLD LINES INDICATE HIGH CURRENT PATHS 1773 F06 Figure 6. LTC1773 Layout Diagram 1773fb 13 LTC1773 U W U U APPLICATIONS INFORMATION For the selection of the external MOSFETs, the RDS(ON) must be guaranteed at 2.5V since the LTC1773 has to operate down to 2.7V. This requirement can be met by the Si9801DY. For the feedback resistors, choose R1 = 80.6k. R2 can then be calculated from equation (2) to be: ⎞ ⎛V R2 = ⎜ OUT – 1⎟ R1 = 171k; use 169k ⎠ ⎝ 0.8 Figure 7 shows the complete circuit along with its efficiency curve. 33pF 2.7V ≤ VIN ≤ 4.2V 30k 200pF 1 ITH SW 2 0.1µF – 10 9 RSENSE 0.033Ω RUN/SS SENSE LTC1773 3 8 VIN VIN SYNC/FCB 4 5 TG VFB BG GND L1 2.5µH 7 VOUT 2.5V 2A + 6 + Si9801DY 169k 1% 80.6k 1% CIN: SANYO POSCAP 6TPA150M COUT: AVX TPSD227M006R0100 L1: CDRH5D28 RSENSE: IRC LR1206-01-R033-F CIN 150µF 6.3V COUT 220µF 6.3V 1773 F07a Figure 7. Single Lithium-Ion to 2.5V/2A Regulator Efficiency Curve for Figure 7 100 VOUT = 2.5V EFFICIENCY (%) 95 VIN = 3.3V 90 85 80 75 70 1 10 100 1000 OUTPUT CURRENT (mA) 5000 1773 F1b 1773fb 14 LTC1773 U TYPICAL APPLICATIONS 33pF 2.7V ≤ VIN ≤ 8.4V 200pF 1 30k 2 0.1µF 10 SW SYNC/FCB VIN VFB TG 5 + L1 5µH 1:1 8 VOUT2 5V 100mA 22µF 6.2V 422k VOUT1 2.5V 2A 7 6 BG GND RSENSE 0.033Ω 9 RUN/SS SENSE– 3 4 MBR0530LT1 LTC1773 ITH 169k 1% + Si9801DY 80.6k 1% + 80.6k COUT 220µF 6.3V L1: COILTRONICS CTX5-4/BH ELECTRONICS 511-0033 RSENSE: IRC LR1206-01-R033-F CIN: SANYO POSCAP 10TPA100M COUT: AVX TPSD227M006R0100 CIN 100µF 10V 1773 TA01 Figure 8. Dual Output 2.5V/2A and 5V/100mA Application 33pF 2.7V ≤ VIN ≤ 5.5V 30k 200pF 1 2 0.1µF VIN 3 4 5 LTC1773 ITH SW RUN/SS SENSE– SYNC/FCB VIN VFB TG GND BG 10 RSENSE 0.015Ω 9 Si9803DY 8 VOUT 2.5V 5A L1 2.8µH 7 + Si9804DY 6 + 169k 1% 80.6k 1% CIN: SANYO POSCAP 6TPA150M COUT: AVX TPSD227M006R0100 CIN 150µF 6.3V COUT 220µF 6.3V ×3 L1: TOKO D104C 919AS-2R8M RSENSE: DALE WSL-2010 1773 TA02 Figure 9. Single Lithium-Ion to 2.5V/5A Regulator Efficiency Curve for Figure 9 100 95 VIN = 3.3V EFFICIENCY (%) 90 VIN = 5V 85 80 75 70 65 60 1 10 100 IOUT (mA) 1000 10000 1773 • G17 1773fb 15 LTC1773 U TYPICAL APPLICATIONS 33pF 2.7V ≤ VIN ≤ 4.2V 30k 200pF 1 2 0.1µF VIN 3 4 5 LTC1773 ITH SW RUN/SS SENSE – SYNC/FCB VIN VFB TG BG GND 10 RSENSE 0.025Ω 9 Si9803DY 8 L1 2µH 47µF 7 VOUT 3.3V 1A + + 6 Si9804DY + 249k 1% 80.6k 1% CIN 150µF 6.3V COUT 220µF 6.3V L1 2µH CIN: SANYO POSCAP 6TPA150M COUT: AVX TPSD227M006R0100 L1: COILTRONICS CTX2-4/BH ELECTRONICS 511-1010 RSENSE: IRC LR1206-01-R033-F 1773 TA03 Figure 10. Single Lithium-Ion to 3.3V/1A Synchronous Zeta Converter Efficiency Curve for Figure 10 100 VOUT = 3.3V 90 VIN = 5V VIN = 4V EFFICIENCY (%) 80 VIN = 3.3V 70 VIN = 2.7V 60 50 40 30 20 0.001 0.01 0.1 OUTPUT CURRENT (A) 1.0 1773 G18 1773fb 16 LTC1773 U TYPICAL APPLICATIONS 2.7V ≤ VIN ≤ 4.2V 47pF 30k 1 220pF LTC1773 ITH 2 RUN/SS SENSE 4 SYNC/FCB 8 VIN VFB TG GND BG 5 100pF RSENSE 0.05Ω 9 – 0.1µF 3 750kHz CLK 10 SW VOUT 2.5V 1A L1 3µH 7 CIN 47µF 6.3V 6 169k 1% 4.7µF 6.3V Si6803DQ + 100pF 80.6k 1% + COUT 47µF 6.3V 0.1µF CIN, COUT: SANYO POSCAP 6TPA47M L1: SUMIDA CDRH5D28 3R0 RSENSE: IRC LR1206-01-R050-J 1773 TA06 Figure 11. 750kHz Single Lithium-Ion to 2.5V/1A Regulator VOUT3 2.5V 150mA 8 LT1762-2.5 IN 1 OUT 2 1µF 10µF SENSE 0.01µF 5 3 SHDN VOUT1 1.8V 6A BYP GND VOUT2 3.3V 1A 47pF 3.3V ≤ VIN ≤ 6V 220pF 30k 1 2 0.1µF 3 4 100pF 5 LTC1773 ITH SW RUN/SS SENSE– SYNC/FCB VIN VFB TG GND BG 100k 1% 100pF 80.6k 1% CIN: PANASONIC SPECIAL POLYMER COUT: KEMET T510687K004AS T1: BH ELECTRONICS 510-1007 RSENSE: IRC LR2512-01-R010-J CSEC: TAIYO YUDEN LMK432F476ZM 10 RSENSE 0.01Ω 9 MBRM120T3 + 8 CSEC 47µF 6.3V + 7 0.1µF 249k 1% T1 2.44µH 1:1 6 CIN 150µF 6.3V 80.6k 1% Si7540DP D2* MBRS340T3 + COUT 680µF 4V ×2 1773 TA07 *NOTE: D2 NOT NECESSARY. IF REMOVED, EFFICIENCY DROPS BY 1% Figure 12. Triple Output 1.8V/6A, 2.5V/150mA,and 3.3V/1A Application 1773fb 17 LTC1773 U TYPICAL APPLICATIONS 2.7V ≤ VIN ≤ 6V 47pF 30k 1 220pF 2 0.1µF 3 4 5 100pF LTC1773 ITH 10 SW RUN/SS SENSE– VFB TG GND BG D1 MMSD914T1 8 VIN SYNC/FCB RSENSE 0.068Ω 9 VOUT 2V 800mA L1 4.2µH 7 CIN 47µF 6.3V 6 118k 1% 4.7µF 6.3V Si9801DY 100pF 80.6k 1% + D2* MBR0530LT1 0.1µF + COUT 47µF 6.3V *NOTE: D2 NOT NECESSARY. IF REMOVED, EFFICIENCY DROPS BY 1% CIN, COUT: SANYO POSCAP 6TPA47M L1: SUMIDA CDRH5D28 4R2 RSENSE: IRC LR1206-01-R068-F 1773 TA05 Figure 13. Single Lithium-Ion to 2V/800mA Regulator with Current Foldback 2.7V ≤ VIN ≤ 6V 47pF 30k 220pF 0.1µF 1 2 3 4 100pF 5 LTC1773 ITH SW RUN/SS SENSE– SYNC/FCB VIN VFB TG GND BG 100k 1% 10 RSENSE 0.01Ω 9 8 VOUT 1.8V 7A L1 1µH 7 4.7µF 6.3V Si7540DP + 100pF D2* MBRS340T3 CIN: PANASONIC SPECIAL POLYMER COUT: KEMET T510687K004AS L1: TOKO TYPE D104C 919AS-1RON RSENSE: IRC LR2512-01-R010-J CIN 150µF 6.3V 6 0.1µF 80.6k 1% + COUT 680µF 4V ×2 *NOTE: D2 NOT NECESSARY. IF REMOVED, EFFICIENCY DROPS BY 1% 1773 TA08 Figure 14. 3.3V to 1.8V/7A Regulator 1773fb 18 LTC1773 U TYPICAL APPLICATIONS 33pF 4.5V ≤ VIN ≤ 5.5V 200pF 1 30k 2 0.1µF VIN 3 4 5 LTC1773 ITH SW – RUN/SS SENSE SYNC/FCB VIN VFB TG BG GND 10 9 RSENSE 0.04Ω 8 L1 2.5µH 7 VOUT 1.8V 2A CIN 47µF 10V 6 COUT 47µF 10V Si9942DY 100k 1% 80.6k 1% CIN, COUT: TAIYO YUDEN LMK550BJ476MM L1: CDRH5D28 RSENSE: IRC LR1206-01-R040-F 1773 TA09 Figure 15. 5V to 1.8V/2A Regulator with Ceramic Capacitors U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 10 9 8 7 6 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.497 ± 0.076 (.0196 ± .003) REF 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 1 2 3 4 5 0° – 6° TYP GAUGE PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.53 ± 0.152 (.021 ± .006) DETAIL “A” SEATING PLANE 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS) 0603 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 1773fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1773 U TYPICAL APPLICATIO 33pF 30k 4.5V ≤ VIN ≤ 5.5V 200pF 1 2 0.1µF VIN 3 4 5 LTC1773 ITH SW RUN/SS SENSE– SYNC/FCB VIN VFB TG GND BG 10 9 L1 10µH 3:1 8 + Si2302DS 6 COUT2 150µF 6.3V D1 + 169k 1% CIN 150µF 6.3V VOUT1 2.5V 1A 7 Si6801DY 40.2k 1% + VOUT2 3.3V 500mA RSENSE 0.050Ω 249k 1% 47k COUT1 150µF 6.3V 0.1µF CIN, COUT1, COUT2: SANYO POSCAP 6TPA150M RSENSE: IRC LR1206-01-R050-F D1: BAS16 1773 TA04 Figure 16. Dual Output Synchronous Buck Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1622 Low Voltage Current Mode Step-Down DC/DC Controller VIN: 2V to 10V, 550kHz, Burst Mode Operation, Synchronizable LTC1627/LTC1707 Low Voltage, Monolithic Synchronous Step-Down Regulator Low Supply Voltage Range: 2.65V to 8V, IOUT to 0.5A LTC1735 High Efficiency Synchronous Step-Down Switching Controller Burst Mode Operation, 16-Pin Narrow SO, Fault Protection LTC1735-1 High Efficiency Synchronous Step-Down Switching Controller Output Fault Protection 16-Pin GN, Burst Mode Operation, Power Good LTC1771 Low Quiescent Current Step-Down DC/DC Controller VIN: 2.8V to 18V, 10µA IQ, MS8 Package LTC1772/B SOT-23 Low Voltage Step-Down Controller 6-Pin SOT-23, 2V ≤ VIN ≤ 10V, 550kHz LTC1778 Wide Operating Range/Step-Down Controller, No RSENSE VIN up to 36V, Current Mode, Power Good LTC1779 SOT-23 Current Mode Step-Down Converter 250mA Output Current, 2.5V ≤ VIN ≤ 9.8V, Up to 94% Efficiency LTC1877 High Efficiency Monolithic Synchronous Step-Down Regulator VIN from 2.65V to 10V, 10µA IQ, 550kHz, IOUT to 600mA,MS8 LTC1878 High Efficiency Monolithic Synchronous Step-Down Regulator VIN from 2.65V to 7V, 10µA IQ, 550kHz, IOUT to 600mA,MS8 LTC3404 1.4MHz Monolithic Synchronous Step-Down Regulator Up to 95% Efficiency, IOUT = 600mA at VIN = 3.3V No Schottky Diode Required, 8-Lead MSOP 1773fb 20 Linear Technology Corporation LT 1106 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006