LINER LTC3412AEFE-PBF

LTC3412A
3A, 4MHz, Monolithic
Synchronous Step-Down Regulator
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DESCRIPTIO
FEATURES
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High Efficiency: Up to 95%
3A Output Current
Low Quiescent Current: 64μA
Low RDS(ON) Internal Switch: 77mΩ
2.25V to 5.5V Input Voltage Range
Programmable Frequency: 300KHz to 4MHz
±2% Output Voltage Accuracy
0.8V Reference Allows Low Output Voltage
Selectable Forced Continuous/Burst Mode® Operation
with Adjustable Burst Clamp
Synchronizable Switching Frequency
Low Dropout Operation: 100% Duty Cycle
Power Good Output Voltage Monitor
Overtemperature Protected
Available in 16-Lead Exposed Pad TSSOP and
QFN Packages
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APPLICATIO S
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Point-of-Load Regulation
Notebook Computers
Portable Instruments
Distributed Power Systems
The LTC®3412A is a high efficiency monolithic synchronous, step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from
an input voltage range of 2.25V to 5.5V and provides a
regulated output voltage from 0.8V to 5V while delivering up to 3A of output current. The internal synchronous
power switch with 77mΩ on-resistance increases efficiency
and eliminates the need for an external Schottky diode.
Switching frequency is set by an external resistor or can
be synchronized to an external clock. 100% duty cycle
provides low dropout operation extending battery life in
portable systems. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
The LTC3412A can be configured for either Burst Mode
operation or forced continuous operation. Forced continuous operation reduces noise and RF interference while
Burst Mode operation provides high efficiency by reducing
gate charge losses at light loads. In Burst Mode operation,
external control of the burst clamp level allows the output
voltage ripple to be adjusted according to the application
requirements.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131, 6724174.
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TYPICAL APPLICATIO
22μF
Efficiency and Power Loss
VIN
3.3V
100
PVIN SVIN
RT
PGOOD
COUT
100μF
×2
PGND
ITH
SYNC/MODE
SGND
VFB
80
1000
75
70
100
65
820pF
60
69.8k
10000
85
392k
POWER LOSS
POWER LOSS (mW)
12.1k
1000pF
VOUT
2.5V AT 3A
SW
RUN/SS
100000
EFFICIENCY
90
0.47μH
LTC3412A
294k
EFFICIENCY (%)
2.2M
95
10
55
115k
3412A F01a
Figure 1. 2.5V/3A Step-Down Regulator
50
0.01
0.1
1
LOAD CURRENT (A)
1
10
3412A F01b
3412afc
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LTC3412A
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ABSOLUTE
AXI U RATI GS
(Note 1)
Input Supply Voltage .................................... –0.3V to 6V
ITH, RUN/SS, VFB, PGOOD,
SYNC/MODE Voltages ....................................–0.3 to VIN
SW Voltages ..................................–0.3V to (VIN + 0.3V)
Operating Ambient Temperature Range
(Note 2) ...............................................– 40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
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PI CO FIGURATIO
1
16 PVIN
2
15 SW
ITH
3
14 SW
VFB
4
13 PGND
SGND 2
RT
5
12 PGND
PVIN 3
SYNC/MODE
6
11 SW
RUN/SS
7
10 SW
SGND
8
9
16 15 14 13
12 PGOOD
RUN/SS 1
11 SVIN
17
10 PVIN
SW 4
FE PACKAGE
16-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 17) IS SGND MUST BE SOLDERED TO PCB
6
7
8
SW
PGND
SW
PVIN
9
5
PGND
17
ITH
SVIN
PGOOD
VFB
TOP VIEW
RT
SYNC/MODE
TOP VIEW
SW
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, JC = 1°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE CONNECTED TO PCB
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ORDER I FOR ATIO
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3412AEFE#PBF
LTC3412AEFE#TRPBF
3412AEFE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3412AIFE#PBF
LTC3412AIFE#TRPBF
3412AIFE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3412AEUF#PBF
LTC3412AEUF#TRPBF
3412A
16-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC3412AIUF#PBF
LTC3412AIUF#TRPBF
3412A
16-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3412AEFE
LTC3412AEFE#TR
3412AEFE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3412AIFE
LTC3412AIFE#TR
3412AIFE
16-Lead Plastic TSSOP
–40°C to 85°C
LTC3412AEUF
LTC3412AEUF#TR
3412A
16-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
LTC3412AIUF
LTC3412AIUF#TR
3412A
16-Lead (4mm × 4mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC3412A
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
SVIN
Signal Input Voltage Range
VFB
Regulated Feedback Voltage
IFB
Voltage Feedback Leakage Current
ΔVFB
CONDITIONS
MIN
TYP
2.25
(Note 3)
●
Reference Voltage Line Regulation
VIN = 2.7V to 5.5V (Note 3)
VLOADREG
Output Voltage Load Regulation
Measured in Servo Loop, VITH = 0.36V
Measured in Servo Loop, VITH = 0.84V
0.784
0.800
MAX
UNITS
5.5
V
0.816
V
0.1
0.2
μA
●
0.04
0.2
%V
●
●
0.02
–0.02
0.2
–0.2
%
%
ΔVPGOOD
Power Good Range
±7.5
±9
%
RPGOOD
Power Good Pull-Down Resistance
120
200
Ω
IQ
Input DC Bias Current
Active Current
Sleep
Shutdown
(Note 4)
VFB = 0.78V, VITH = 1V
VFB = 1V, VITH = 0V
VRUN = 0V, VMODE = 0V
250
64
0.02
330
80
1
μA
μA
μA
fOSC
Switching Frequency
Switching Frequency Range
ROSC = 294kΩ
(Note 6)
0.88
0.3
1
1.1
4
MHz
MHz
fSYNC
SYNC Capture Range
(Note 6)
0.3
4
MHz
RPFET
RDS(ON) of P-Channel FET
ISW = 1A (Note 7)
77
110
mΩ
RNFET
RDS(ON) of N-Channel FET
ISW = –1A (Note 7)
65
90
mΩ
ILIMIT
Peak Current Limit
VUVLO
Undervoltage Lockout Threshold
ILSW
SW Leakage Current
VRUN
RUN Threshold
IRUN
RUN/SS Leakage Current
4.5
1.75
VRUN = 0V, VIN = 5.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3412AE is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3412AI is guaranteed to
meet performance specifications over the full –40°C to 85°C operating
temperature range.
0.5
6
A
2
2.25
V
0.1
1
μA
0.65
0.8
V
1
μA
Note 3: The LTC3412A is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation as follows: LTC3412AFE: TJ = TA + PD (38°C/W)
LTC3412AUF: TJ = TA + PD (34°C/W)
Note 6: 4MHz operation is guaranteed by design and not production tested.
Note 7: Switch on resistance is guaranteed by design and test condition in
the UF package and by final test correlation in the FE package.
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LTC3412A
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current, Burst
Mode Operation
Efficiency vs Load Current
100
100
Burst Mode
80 OPERATION
95
70
85
50
40
30
80
VIN = 5V
80
75
70
65
60
VIN = 3.3V
VOUT = 2.5V
FIGURE 4 CIRCUIT
10
0
0.01
0.1
1
LOAD CURRENT (A)
50
0.01
0.1
1
LOAD CURRENT (A)
3412A GO1
40
FIGURE 4 CIRCUIT
95
1A
0
0.01
10
EFFICIENCY (%)
86
84
3A
Load Regulation
93
0.47μH
92
91
90
89
82
10
0
FIGURE 4 CIRCUIT
VIN = 3.3V
–0.1
0.22μH
90
0.1A
0.1
1
LOAD CURRENT (A)
3412A GO3
FIGURE 4 CIRCUIT
VIN = 3.3V
1μH
94
88
VOUT = 2.5V
FIGURE 4 CIRCUIT
10
Efficiency vs Frequency
96
92
80
2.5
50
3412A GO2
Efficiency vs Input Voltage
94
60
20
VOUT = 2.5V
FIGURE 4 CIRCUIT
55
10
VIN = 5V
70
30
ΔVOUT/VOUT (%)
20
VIN = 3.3V
90
EFFICIENCY (%)
FORCED
CONTINUOUS
60
100
VIN = 3.3V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
EFFICIENCY (%)
Efficiency vs Load Current,
Forced Continuous Operation
–0.2
–0.3
–0.4
–0.5
88
3.0
3.5
4.0
INPUT VOLTAGE (V)
4.5
5.0
–0.6
87
0
0.5 1.0
1.5 2.0 2.5 3.0
FREQUENCY (MHz)
3412A GO4
3.5
4.0
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
2.5
3.0
3412A GO6
3412A GO5
Load Step Transient Burst Mode
Operation
Output Voltage Ripple
Burst Mode Operation
BURST
MODE
20mV/DIV
VOUT
20mV/DIV
0
VOUT
100mV/DIV
PULSE
SKIPPING
20mV/DIV
INDUCTOR
CURRENT
1A/DIV
FORCED
CONTINUOUS
20mV/DIV
INDUCTOR
CURRENT
2A/DIV
VIN = 3.3V
5μs/DIV
VOUT = 2.5V
FIGURE 4 CIRCUIT
FIGURE 4 CIRCUIT 5μs/DIV
3412A GO7
3412A GO8
VIN = 3.3V
40μs/DIV
VOUT = 2.5V
F = 1MHz
LOAD STEP = 50mA TO 2A
FIGURE 4 CIRCUIT
3412A GO9
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LTC3412A
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TYPICAL PERFOR A CE CHARACTERISTICS
Load Step Transient Forced
Continuous
Start-Up Transient
VREF vs Temperature
0.7975
0.7970
VOUT
2V/DIV
VIN = 3.3V
0.7965
VOUT
100mV/DIV
VREF (V)
0.7960
RUN/SS
2V/DIV
INDUCTOR
CURRENT
2A/DIV
0.7955
0.7950
0.7945
INDUCTOR
CURRENT
2A/DIV
0.7940
0.7935
40μs/DIV
VIN = 3.3V
VOUT =2.5V
F = 1MHz
LOAD STEP = 0A TO 3A
FIGURE 4 CIRCUIT
3412A G10
100
50
45
SWITCH LEAKAGE CURRENT (nA)
95
100
ON-RESISTANCE (mΩ)
PFET
80
75
70
NFET
65
60
80
PFET
60
NFET
40
20
3.0
4.0
4.5
3.5
INPUT VOLTAGE (V)
0
–40 –20
4500
5.0
0
20 40 60 80
TEMPERATURE (°C)
25
PFET
20
15
10
NFET
2.5
3.0
4.0
4.5
3.5
INPUT VOLTAGE (V)
Frequency vs Input Voltage
Frequency vs ROSC
5.5
Frequency vs Temperature
1020
1060
VIN = 3.3V
5.0
3412A G15
3412A G14
VIN = 3.3V
1015 ROSC = 294k
ROSC = 294k
1050
1010
3000
2500
2000
1500
1000
1040
FREQUENCY (kHz)
3500
FREQUENCY (kHz)
FREQUENCY (kHz)
30
100 120
4000
1030
1020
1010
40 140 240 340 440 540 640 740 840 940
ROSC (kΩ)
3412A G16
990
2.5
1005
1000
995
990
985
980
1000
500
0
35
0
3412A G13
5000
40
5
55
50
2.5
115
95
Switch Leakage Current vs
Input Voltage
VIN = 3.3V
85
15 35 55 75
TEMPERATURE (°C)
3412A G12
120
90
–5
3412A G11
Switch On-Resistance vs
Temperature
Switch On-Resistance vs
Input Voltage
ON-RESISTANCE (mΩ)
0.7930
–45 –25
1ms/DIV
VIN = 3.3V
VOUT =2.5V
LOAD STEP = 2A
FIGURE 4 CIRCUIT
975
3.0
4.0
4.5
3.5
INPUT VOLTAGE (V)
5.0
5.5
3412A G17
970
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
3412A G18
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LTC3412A
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TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs
Temperature
Quiescent Current vs
Input Voltage
350
MAXIMUM PEAK INDUCTOR CURRENT (mA)
350
Minimum Peak Inductor Current vs
Burst Clamp Voltage
VIN = 3.3V
300
ACTIVE
QUIESCENT CURRENT (μA)
QUIESCENT CURRENT (μA)
300
250
200
150
100
SLEEP
50
0
2.5
ACTIVE
250
200
150
100
SLEEP
50
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
0
–40 –20
5.5
0
20
40
60
80
100 120
TEMPERATURE (°C)
3412A G20
3412A G19
4000
3500
3000
2500
2000
1500
1000
500
0
0.1
0.2
0.3
0.4
0.5
VBURST (V)
0.6
0.7
3412A G21
Peak Current vs Input Voltage
8.0
PEAK INDUCTOR CURRENT (A)
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
2.25
2.75
3.25
3.75
4.25
INPUT VOLTAGE (V)
4.75
3412A G22
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LTC3412A
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PI FU CTIO S
(FE Package/UHF Package)
SVIN (Pin 1/Pin 11): Signal Input Supply. Decouple this
pin to SGND with a capacitor.
PGOOD (Pin 2/Pin 12): Power Good Output. Open-drain
logic output that is pulled to ground when the output voltage is not within ±7.5% of regulation point.
ITH (Pin 3/Pin 13): Error Amplifier Compensation Point.
The current comparator threshold increases with this
control voltage. Nominal voltage range for this pin is from
0.2V to 1.4V with 0.4V corresponding to the zero-sense
voltage (zero current).
VFB (Pin 4/Pin 14): Feedback Pin. Receives the feedback
voltage from a resistive divider connected across the
output.
RT (Pin 5/Pin 15): Oscillator Resistor Input. Connecting
a resistor to ground from this pin sets the switching
frequency.
SYNC/MODE (Pin 6/Pin 16): Mode Select and External
Clock Synchronization Input. To select forced continuous,
tie to SVIN. Connecting this pin to a voltage between 0V
and 1V selects Burst Mode operation with the burst clamp
set to the pin voltage.
RUN/SS (Pin 7/Pin 1): Run Control and Soft-Start Input.
Forcing this pin below 0.5V shuts down the LTC3412A.
In shutdown all functions are disabled drawing < 1μA of
supply current. A capacitor to ground from this pin sets
the ramp time to full output current.
SGND (Pin 8/Pin 2): Signal Ground. All small-signal components, compensation components and the exposed pad
on the bottom side of the IC should connect to this ground,
which in turn connects to PGND at one point.
PVIN (Pins 9, 16/Pins 3, 10): Power Input Supply. Decouple
this pin to PGND with a capacitor.
SW (Pins 10, 11, 14, 15/Pins 4, 5, 8, 9): Switch Node
Connection to the Inductor. This pin connects to the drains
of the internal main and synchronous power MOSFET
switches.
PGND (Pins 12, 13/Pins 6, 7): Power Ground. Connect
this pin close to the (–) terminal of CIN and COUT.
Exposed Pad (Pin 17/Pin 17): Signal Ground. Must be
soldered to PCB for electrical connection and rated thermal
performance.
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LTC3412A
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FUNCTIONAL BLOCK DIAGRA
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SVIN
SGND
ITH
1
8
3
PVIN
9
SLOPE
COMPENSATION
RECOVERY
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VOLTAGE
REFERENCE
0.8V
16
PMOS CURRENT
COMPARATOR
+
BCLAMP
+
–
–
VFB 4
ERROR
AMPLIFIER
SYNC/MODE
0.74V
+
–
+
–
+
–
P-CH
BURST
COMPARATOR
10
SLOPE
COMPENSATION
OSCILLATOR
11
SW
14
15
+
RUN/SS 7
N-CH
RUN
0.86V
LOGIC
–
+
PGOOD 2
NMOS
CURRENT
COMPARATOR
–
–
REVERSE
CURRENT
COMPARATOR
5
6
RT
SYNC/MODE
+
12
PGND
13
3412 FBD
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OPERATIO
Main Control Loop
The LTC3412A is a monolithic, constant-frequency, currentmode step-down DC/DC converter. During normal operation, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal from a resistor divider on
the VFB pin with an internal 0.8V reference. When the load
current increases, it causes a reduction in the feedback
voltage relative to the reference. The error amplifier raises
the ITH voltage until the average inductor current matches
the new load current. When the top power MOSFET shuts
off, the synchronous power switch (N-channel MOSFET)
turns on until either the bottom current limit is reached or
the beginning of the next clock cycle. The bottom current
limit is set at –1.3A for forced continuous mode and 0A
for Burst Mode operation.
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LTC3412A
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OPERATIO
The operating frequency is externally set by an external
resistor connected between the RT pin and ground. The
practical switching frequency can range from 300kHz to
4MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ± 7.5%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Forced Continuous Mode
Connecting the SYNC/MODE pin to SVIN will disable Burst
Mode operation and force continuous current operation.
At light loads, forced continuous mode operation is less
efficient than Burst Mode operation, but may be desirable in
some applications where it is necessary to keep switching
harmonics out of a signal band. The output voltage ripple
is minimized in this mode.
Burst Mode Operation
Connecting the SYNC/MODE pin to a voltage in the range
of 0V to 1V enables Burst Mode operation. In Burst Mode
operation, the internal power MOSFETs operate intermittently at light loads. This increases efficiency by minimizing switching losses. During Burst Mode operation, the
minimum peak inductor current is externally set by the
voltage on the SYNC/MODE pin and the voltage on the ITH
pin is monitored by the burst comparator to determine
when sleep mode is enabled and disabled. When the
average inductor current is greater than the load current,
the voltage on the ITH pin drops. As the ITH voltage falls
below 150mV, the burst comparator trips and enables
sleep mode. During sleep mode, the top power MOSFET
is held off and the ITH pin is disconnected from the output
of the error amplifier. The majority of the internal circuitry
is also turned off to reduce the quiescent current to 64μA
while the load current is solely supplied by the output
capacitor. When the output voltage drops, the ITH pin is
reconnected to the output of the error amplifier and the
top power MOSFET along with all the internal circuitry is
switched back on. This process repeats at a rate that is
dependent on the load demand.
Pulse Skipping operation is implemented by connecting
the SYNC/MODE pin to ground. This forces the burst
clamp level to be at 0V. As the load current decreases, the
peak inductor current will be determined by the voltage
on the ITH pin until the ITH voltage drops below 400mV. At
this point, the peak inductor current is determined by the
minimum on-time of the current comparator. If the load
demand is less than the average of the minimum on-time
inductor current, switching cycles will be skipped to keep
the output voltage in regulation.
Frequency Synchronization
The internal oscillator of the LTC3412A can be synchronized to an external clock connected to the SYNC/MODE
pin. The frequency of the external clock can be in the
range of 300kHz to 4MHz. For this application, the oscillator timing resistor should be chosen to correspond to
a frequency that is 25% lower than the synchronization
frequency. During synchronization, the burst clamp is set
to 0V, and each switching cycle begins at the falling edge
of the clock signal.
Dropout Operation
When the input supply voltage decreases toward the output
voltage, the duty cycle increases toward the maximum
on-time. Further reduction of the supply voltage forces
the main switch to remain on for more than one cycle
eventually reaching 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Low Supply Operation
The LTC3412A is designed to operate down to an input
supply voltage of 2.25V. One important consideration
at low input supply voltages is that the RDS(ON) of the
P-channel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3412A is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded.
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LTC3412A
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APPLICATIO S I FOR ATIO
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when
slope compensation is added. In the LTC3412A, however,
slope compensation recovery is implemented to keep the
maximum inductor peak current constant throughout the
range of duty cycles. This keeps the maximum output
current relatively constant regardless of duty cycle.
Short-Circuit Protection
When the output is shorted to ground, the inductor current decays very slowly during a single switching cycle.
To prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases larger than 4.4A, the top
power MOSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
The basic LTC3412A application circuit is shown in Figure 1. External component selection is determined by the
maximum load current and begins with the selection of
the operating frequency and inductor value followed by
CIN and COUT.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3412A is determined
by an external resistor that is connected between pin RT
and ground. The value of the resistor sets the ramp current
that is used to charge and discharge an internal timing
capacitor within the oscillator and can be calculated by
using the following equation:
ROSC =
3.08 • 1011
(Ω) – 10kΩ
f
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3412A imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 110ns; therefore, the minimum duty cycle is
equal to 100 • 110ns • f(Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN or VOUT and
decreases with higher inductance.
V V IL = OUT 1– OUT VIN fL Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors, and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
A reasonable starting point for selecting the ripple current
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should
be chosen according to the following equation:
V
VOUT OUT
L=
1–
fIL(MAX) VIN(MAX) The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
when the peak inductor current falls below a level set by
the burst clamp. Lower inductor values result in higher
ripple current which causes this to occur at lower load
currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
3412afc
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Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price verus size requirements and
any radiated field/EMI requirements. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Toko, and Sumida.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal
wave current at the source of the top MOSFET. To prevent
large voltage transients from occurring, a low ESR input
capacitor sized for the maximum RMS current should be
used. The maximum RMS current is given by:
IRMS =IOUT(MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
derate the capacitor, or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be paralleled to meet size or height requirements in the
design. For low input voltage applications, sufficient bulk
input capacitance is needed to minimize transient effects
during output load changes.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response as described in a later section.
The output ripple, ΔVOUT, is determined by:
1 VOUT IL ESR +
8fCOUT The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic, and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
3412afc
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Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
R2 VOUT = 0.8V 1+ R1
The resistive divider allows pin VFB to sense a fraction of
the output voltage as shown in Figure 2.
VOUT
R2
VFB
LTC3412A
R1
The value for IBURST is determined by the desired amount
of output voltage ripple. As the value of IBURST increases,
the sleep period between pulses and the output voltage
ripple increase. The burst clamp voltage, VBURST, can be
set by a resistor divider from the VFB pin to the SGND pin
as shown in Figure 1.
Pulse skipping, which is a compromise between low output voltage ripple and efficiency, can be implemented by
connecting pin SYNC/MODEto ground. This sets IBURST to
0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operating discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
SGND
3412A F02
Figure 2. Setting the Output Voltage
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than VIN by
1V, Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, IBURST. To select the burst clamp level,
use the graph of Minimum Peak Inductor Current vs Burst
Clamp Voltage in the Typical Performance Characteristics
section.
VBURST is the voltage on the SYNC/MODE pin. IBURST
can only be programmed in the range of 0A to 6A. For
values of VBURST greater than 1V, IBURST is set at 6A. For
values of VBURST less than 0.4V, IBURST is set at 0A. As
the output load current drops, the peak inductor currents
decrease to keep the output voltage in regulation. When
the output load current demands a peak inductor current
that is less than IBURST, the burst clamp will force the peak
inductor current to remain equal to IBURST regardless of
further reductions in the load current. Since the average
inductor current is greater than the output load current,
the voltage on the ITH pin will decrease. When the ITH
voltage drops to 150mV, sleep mode is enabled in which
both power MOSFETs are shut off along with most of the
circuitry to minimize power consumption. All circuitry is
turned back on and the power MOSFETs begin switching
again when the output voltage drops out of regulation.
Frequency Synchronization
The LTC3412A’s internal oscillator can be synchronized
to an external clock signal. During synchronization, the
top MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation
is generated by the oscillator’s RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3412A as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412A in a low
quiescent current shutdown state (IQ < 1μA).
The LTC3412A contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
VIN
t SS = RSS CSS ln (SECONDS)
VIN – 1.8V 3412afc
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Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
The VIN quiescent current loss dominates the efficiency loss
at very low load currents whereas the I2R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
from switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and
QB are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN; thus, their effects will be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. To obtain I2R losses, simply add RSW to RL and
multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative losses
and inductor core losses generally account for less than
2% of the total loss.
Thermal Considerations
In most applications, the LTC3412A does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3412A is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3412A from exceeding the maximum junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
tr = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature. For the 16-lead exposed TSSOP
package, the θJA is 38°C/W. For the 16-lead QFN package
the θJA is 34°C/W.
The junction temperature, TJ, is given by:
TJ = TA + tr
where TA is the ambient temperature.
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)).
To maximize the thermal performance of the LTC3412A,
the exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current.
3412afc
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When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD(ESR), where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value. During
this recovery time, VOUT can be monitored for overshoot
or ringing that would indicate a stability problem. The ITH
pin external components and output capacitor shown in
Figure 1 will provide adequate compensation for most
applications.
Decoupling the PVIN and SVIN pins with two 22μF capacitors is adequate for most applications.
The burst clamp and output voltage can now be programmed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.50V by the resistor
divider consisting of R2 and R3. According to the graph
of Minimum Peak Inductor Current vs Burst Clamp Voltage in the Typical Performance Characteristics section, a
burst clamp voltage of 0.5V will set the minimum inductor
current, IBURST, to approximately 1.1A.
Design Example
If we set the sum of R2 and R3 to 185k, then the following
equations can be solved:
R2 + R3 = 185k
R2 0.8V
1+
=
R3 0.50V
As a design example, consider using the LTC3412A in an
application with the following specifications:
VIN = 3.3V, VOUT = 2.5V, IOUT(MAX) = 3A,
IOUT(MIN) = 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
3.08 • 1011
– 10k = 298k
ROSC =
1• 106
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
2.5V 2.5V
L=
1–
= 0.51μH
(1MHz)(1.2A) 3.3V Using a 0.47μH inductor results in a maximum ripple
current of:
2.5V 2.5V
IL = 1–
= 1.29A
(1MHz)(0.47μH) 3.3V COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
2.5V IRMS = (3A) 3.3V 3.3V
– 1= 1.29ARMS
2.5V
The two equations shown above result in the following
values for R2 and R3: R2 = 69.8k , R3 = 115k. The value
of R1 can now be determined by solving the following
equation.
2.5V
R1
1+
=
185k 0.8V
R1 = 392k
A value of 392k will be selected for R1. Figure 4 shows
the complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3412A. Check the following in your layout:
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small signal components returning
to the SGND pin at one point which is then connected to
the PGND pin close to the LTC3412A.
2. Connect the (+) terminal of the input capacitor(s), CIN, as
close as possible to the PVIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
3412afc
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3. Keep the switching node, SW, away from all sensitive
small signal nodes.
5. Connect the VFB pin directly to the feedback resistors.
The resistor divider must be connected between VOUT
and SGND.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail
in your system).
Bottom
Top
Figure 3. LTC3412A Layout Diagram
VIN
3.3V
CFF 22pF X5R
CIN3**
100μF
R1 392k
1
RPG
100k
PGOOD
CITH 330pF X7R RITH
17.4k
2
3
CC
47pF
4
R3
115k
RSS
2.2M
SVIN
PVIN
PGOOD
SW
ITH
SW
CIN1
22μF
14
L1*
0.47μH
VFB
5
ROSC
294k
6 SYNC/MODE
CSS
1000pF X7R 8
15
LTC3412A
13
EFE
PGND
R2
69.8k
7
16
PGND
12
RT
SW
RUN
SW
SGND
PVIN
11
COUT**
100μF
×2
10
9
CIN2
22μF
X5R 6.3V
*VISHAY IHLP-2525CZ-01
**TDK 4532X5R0J107M
VOUT
2.5V
3A
GND
3412 F04
Figure 4. 3.3V to 2.5V, 3A Regulator at 1MHz, Burst Mode Operation
3412afc
15
LTC3412A
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TYPICAL APPLICATIO S
1.2V, 3A, 1.5MHz 1mm Height Regulator Using All Ceramic Capacitors
VIN
3.3V
C1 22pF X5R
R1 95.3k
11
RPG
100k
PGOOD
CITH 1000pF X7R RITH
6.34k
12
13
CC
22pF
14
RSS
2.2M
R2
187k
15
ROSC
196k
16
1
CSS
1000pF X7R 2
SVIN
PVIN
PGOOD
SW
ITH
SW
10
CIN1
10μF
X5R 6.3V
9
8
LTC3412A
7
EUF
PGND
L1*
0.47μH
VFB
PGND
VOUT
1.2V
3A
6
RT
SW
5
COUT**
22μF
X3
SYNC/MODE
RUN
SW
SGND
PVIN
4
3
CIN2
10μF
X5R 6.3V
GND
3412 TA01
*COOPER SD10-R47
**TAIYO YUDEN AMK212BJ226MD-B
1.8V, 3A Step-Down Regulator at 1MHz, Burst Mode Operation
VIN
2.5V
C1 47pF X5R
CIN3**
100μF
R1 232k
1
RPG
100k
PGOOD
CITH 820pF X7R RITH
15k
2
3
C2
47pF
4
R3
115k
RSS
2.2M
R2
69.8k
5
ROSC
294k
6
7
CSS
1000pF X7R 8
SVIN
PVIN
PGOOD
ITH
SW
16
15
14
SW
LTC3412A
13
EFE
PGND
VFB
PGND
CIN1
22μF
X5R 6.3V
L1
0.47μH*
VOUT
1.8V
3A
12
RT
SW
11
COUT**
100μF
×3
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF
X5R 6.3V
3412 TA02
GND
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
3412afc
16
LTC3412A
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TYPICAL APPLICATIO S
3.3V, 3A Step-Down Regulator at 2MHz, Forced Continuous Mode Operation
CIN3**
100μF
C1 22pF X5R
VIN
5V
R1 634k
1
RPG
100k
PGOOD
CITH 820pF X7R RITH
7.5k
2
3
CC
47pF
PVIN
PGOOD
SW
ITH
SW
16
15
CIN1
22μF
X5R 6.3V
14
LTC3412A
13
EFE
PGND
4
L1*
0.47μH
VFB
R2
200k
5
ROSC
137k
6
7
CSS
1000pF X7R 8
RSS
2.2M
SVIN
PGND
VOUT
3.3V
3A
12
RT
SW
11
COUT**
100μF
×2
SYNC/MODE
RUN
SW
SGND
PVIN
10
9
CIN2
22μF
X5R 6.3V
GND
3412 TA03
*VISHAY IHLP-2525CZ-01
**TDK C4532X5R0J107M
2.5V, 3A Step-Down Regulator Synchronized to 1.8MHz
VIN
3.3V
C1 22pF X5R
R1 392k
1
RPG
100k
PGOOD
CITH 220pF X7R
RITH
6.49k
2
3
SVIN
PGOOD
ITH
CC 22pF
4
PVIN
SW
CIN1
22μF
X5R 6.3V
L1*
0.47μH
VFB
PGND
1.8MHz 6 SYNC/MODE
EXT CLOCK 7
RUN
CSS
1000pF X7R 8
SGND
SW
SW
PVIN
11
+
10
COUT**
150μF
9
CIN2
22μF
X5R 6.3V
*COOPER SD20-R47
**SANYO POSCAP 4TPE150MAZB
VOUT
1.5V
3A
12
RT
ROSC 182k
RSS
2.2M
15
14
SW
LTC3412A
13
EFE
PGND
R2 162k
5
16
GND
3412 TA04
3412afc
17
LTC3412A
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PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BA
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 ±0.10
9
2.74
(.108)
4.50 ±0.10
2.74 6.40
(.108) (.252)
BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.25
REF
1.10
(.0433)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0204
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3412afc
18
LTC3412A
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PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.15 ± 0.05
2.90 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
4.00 ± 0.10
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
15
PIN 1 NOTCH R = 0.20 TYP
OR 0.35 × 45° CHAMFER
16
0.55 ± 0.20
PIN 1
TOP MARK
(NOTE 6)
1
2.15 ± 0.10
(4-SIDES)
2
(UF16) QFN 10-04
0.200 REF
0.00 – 0.05
0.30 ± 0.05
0.65 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3412afc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3412A
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTC1879
1.20A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN) = 0.8V, IQ = 15μA,
ISD <1μA, TSSOP16 Package
LT1934/LT1934-1
300mA (IOUT), Constant Off-Time, High Efficiency Step-Down
DC/DC Converter
90% Efficiency, VIN: 3.2V to 34V, VOUT(MIN) = 1.25V, IQ = 14μA,
ISD <1μA, ThinSOT ™ Package
LTC3404
600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10μA,
ISD <1μA, MS8 Package
LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA,
ISD <1μA, ThinSOT Package
LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA,
ISD <1μA, ThinSOT Package
LTC3407
Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,
ISD <1μA, MS10E and 3mm × 3mm DFN Packages
LTC3411
1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, MS10 and 3mm × 3mm DFN Packages
LTC3412
2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, TSSOP16E Package
LTC3413
3A (IOUT Sink/Source), 2MHz, Monolithic Synchronous Regulator
for DDR/QDR Memory Termination
90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2,
IQ = 280μA, ISD <1μA, TSSOP16E Package
LTC3414
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD <1μA, TSSOP20E Package
LTC3416
4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD <1μA, TSSOP20E Package
LTC3418
8A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 380μA,
ISD <1μA, QFN Package
LT3430
60V, 2.75A (IOUT), 200kHz, High Efficiency Step-Down
DC/DC Converter
90% Efficiency, VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,
ISD 25μA, TSSOP16E Package
LTC3440
600mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT: 2.5V to 5.5V, IQ = 25μA,
ISD <1μA, DFN Package
LTC3441
1.2A (IOUT), 1MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN: 2.4V to 5.5V, VOUT: 2.4V to 5.25V, IQ = 25μA,
ISD <1μA, DFN Package
LTC3548
400mA/800mA Dual Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ <40μA,
ISD <1μA, MS8E and DFN Packages
ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
LT 0708 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005