LTC3709 Fast 2-Phase, No RSENSETM, Synchronous DC/DC Controller with Tracking/Sequencing DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PolyPhaseTM Valley Current Mode Controller Synchronizable to an External Clock with PLL Coincident or Ratiometric Tracking Sense Resistor Optional 2% to 90% Duty Cycle at 200kHz tON(MIN) < 100ns True Remote Sensing Differential Amplifier High Efficiency at Both Light and Heavy Loads Power Good Output Voltage Monitor 0.6V ±1% Reference Adjustable Current Limit Programmable Soft-Start and Operating Frequency Output Overvoltage Protection Optional Short-Circuit Shutdown Timer 32-Lead (5mm × 5mm) QFN Package The LTC®3709 is a single output, dual phase, synchronous step-down switching regulator. The controller uses a constant on-time, valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. An internal phase-locked loop allows the LTC3709 to be synchronized to an external clock. A TRACK pin is provided for tracking or sequencing the output voltage among several LTC3709 chips or an LTC3709 and other DC/DC regulators. Soft-start is accomplished using an external timing capacitor. Fault protection is provided by an output overvoltage comparator and an optional short-circuit shutdown timer. The current limit level is user programmable. A wide supply range allows voltages as high as 31V to step down to 0.6V. U APPLICATIO S ■ , LTC and LT are registered trademarks of Linear Technology Corporation. No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6476589, 6144194, 5847554, 6177678, 6304066, 6580258, 6674274, 6462525, 6593724. Notebook Computers Power Supply for DSP, ASIC, Graphic Processors U ■ TYPICAL APPLICATIO High Efficiency Dual Phase 1.5V/30A Step-Down Converter 1µF 1µF 4.7µF 324k 10Ω PGND1 PGND2 VCC DRVCC ION TRACK TG1 VRNG FCB BOOST1 47.5k 10k 100k 0.1µF BG1 100 1.22µH 100nF 10k VFB DIFFOUT 15k VIN VOS VOS+ SENSE2– PGND2 8 0.22µF 6 75 5 70 4 3 POWER LOSS 60 1.22µH HAT2165H 7 80 65 HAT2168H VOUT 1.5V 30A SW2 SENSE2+ BG2 – 9 EFFICIENCY 85 HAT2165H TG2 BOOST2 10 VIN = 12V 90 20k SGND 95 + 330µF 2.5V ×4 2 1 55 50 0.01 POWER LOSS (W) RUN/SS Efficiency and Power Loss HAT2168H 0.22µF EXTLPF SENSE1– INTLPF PGND1 ITH LTC3709 3.32k 680pF PGOOD SW1 SENSE1+ VIN 4.5V TO 28V 10µF 35V ×3 1µF EFFICIENCY (%) 5V 0.1 1 10 LOAD CURRENT (A) 0 100 3709 TA01b 3709 TA01a 3709f 1 LTC3709 W W W AXI U U U W PACKAGE/ORDER I FOR ATIO U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VCC, DRVCC) ............ 7V to – 0.3V Boosted Topside Driver Supply Voltage (BOOST1, BOOST2) .................................. 37V to – 0.3V Switch Voltage (SW1, 2) ............................. 31V to – 1V SENSE1+, SENSE2+ Voltages ....................... 31V to – 1V SENSE1–, SENSE2– Voltages .................... 10V to – 0.3V ION Voltage ............................................... 31V to –0.3V (BOOST – SW) Voltages ..............................7V to – 0.3V RUN/SS, PGOOD Voltages .......................... 7V to – 0.3V TRACK Voltage ............................................7V to – 0.3V VRNG Voltage ................................. VCC + 0.3V to – 0.3V ITH Voltage ............................................... 2.7V to – 0.3V VFB Voltage .............................................. 2.7V to – 0.3V INTLPF, EXTLPF Voltages ........................ 2.7V to – 0.3V VOS+, VOS– Voltages ................................... 7V to – 0.3V FCB Voltage ................................................ 7V to – 0.3V Operating Temperature Range ................ – 40°C to 85°C Junction Temperature (Note 2) ............................ 125°C Storage Temperature Range ................ – 65°C to 125°C SENSE1+ SW1 TG1 BOOST1 PGOOD ION FCB VRNG TOP VIEW 32 31 30 29 28 27 26 25 24 SENSE1– RUN/SS 1 ITH 2 23 PGND1 VFB 3 22 BG1 TRACK 4 21 DRVCC 33 SGND 5 20 BG2 19 PGND2 SGND 6 18 SENSE2– VOS– 7 DIFFOUT 8 17 VCC SENSE2+ SW2 TG2 BOOST2 NC INTLPF EXTLPF VOS+ 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN EXPOSED PAD IS SGND (PIN 33) MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 34°C/ W ORDER PART NUMBER UH PART MARKING LTC3709EUH 3709 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 2.4 25 3 65 mA µA – 35 – 60 nA 0.600 0.606 Main Control Loop IQ Input DC Supply Current Normal Shutdown IFB FB Pin Input Current ITH = 1.2V (Note 3) VFB Feedback Voltage ITH = 1.2V (Note 3) ∆VFB(LINEREG) Feedback Voltage Line Regulation VIN = 4V to 6.5V (Note 3) ∆VFB(LOADREG) Feedback Voltage Load Regulation ITH = 0.5V to 2V (Note 3) – 0.12 – 0.2 % gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 3) 1.3 1.45 1.6 mS tON On-Time VIN = 20V, ION = 180µA VIN = 20V, ION = 90µA 90 180 116 233 140 280 ns ns tON(MIN) Minimum On-Time VIN = 20V, ION = 540µA 45 100 ns tOFF(MIN) Minimum Off-Time VIN = 20V, ION = 90µA 250 350 ns ● 0.594 0.02 V %/V 3709f 2 LTC3709 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VSENSE(MAX) Maximum Current Sense Threshold VRNG = 1V VRNG = 0V VRNG = VCC 124 86 177 144 101 202 166 119 234 mV mV mV VSENSE(MIN) Minimum Current Sense Threshold VRNG = 1V VRNG = 0V VRNG = VCC ∆VFB(OV) Overvoltage Fault Threshold 8.5 10 12.5 % ∆VFB(UV) Undervoltage Fault Threshold – 8.5 – 10 – 12.5 % VRUN/SS(ON) RUN Pin Start Threshold 0.8 1.4 2 V VRUN/SS(LE) RUN Pin Latchoff Enable Threshold RUN/SS Pin Rising VRUN/SS(LT) RUN Pin Latchoff Threshold RUN/SS Pin Falling IRUN/SS(C) Soft-Start Charge Current IRUN/SS(D) Soft-Start Discharge Current UVLO Undervoltage Lockout Measured at VCC Pin TG RUP TG Driver Pull-Up On-Resistance TG High 2 Ω TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.5 Ω BG RUP BG Driver Pull-Up On-Resistance BG High 3 Ω BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.5 Ω ITRACK TRACK Pin Input Current ITH = 1.2V, VTRACK = 0.2V (Note 3) –100 –150 nA VFB(TRACK) Feedback Voltage at Tracking VTRACK = 0.1V, ITH = 1.2V (Note 3) VTRACK = 0.3V, ITH = 1.2V (Note 3) VTRACK = 0.5V, ITH = 1.2V (Note 3) 90 290 490 100 300 500 110 310 510 mV mV mV ∆VFBH PGOOD Upper Threshold VFB Rising 8.5 10 12.5 % ∆VFBL PGOOD Lower Threshold VFB Falling – 8.5 – 10 – 12.5 % PG Delay PGOOD Delay VFB Falling 100 ∆VFB(HYS) PGOOD Hysteresis VFB Returning IPGOOD PGOOD Leakage Current VPGOOD = 7V VPGL PGOOD Low Voltage IPGOOD = 5mA – 60 – 40 – 80 ● mV mV mV 3 V 2.3 – 0.5 0.8 – 1.2 V –3 µA 2 4 µA 3.9 4.2 V Tracking PGOOD Output µs 3.5 0.2 % ±1 µA 0.4 V Phase-Lock Loop IINTPLL_SOURCE Internal PLL Sourcing Current 20 µA IINTPLL_SINK Internal PLL Sinking Current – 20 µA IEXTPLL_SOURCE External PLL Sourcing Current 20 µA IEXTPLL_SINK External PLL Sinking Current – 20 µA VFCB(DC) Forced Continuous Threshold Measured with a DC Voltage at FCB Pin VFCB(AC) Clock Input Threshold Measured with a AC Pulse at FCB Pin tON(PLL)1 tON1 Modulation Range by External PLL Up Modulation Down Modulation tON2 Modulation Range by Internal PLL Up Modulation Down Modulation tON(PLL)2 1.9 2.1 2.3 V 1 1.5 2 V ION1 = 180µA, VEXTPLL = 1.8V ION1 = 180µA, VEXTPLL = 0.6V 186 233 58 80 ns ns ION2 = 180µA, VINTPLL = 1.8V ION2 = 180µA, VINTPLL = 0.6V 186 233 58 80 ns ns 3709f 3 LTC3709 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = DRVCC = 5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.995 1.000 0.5 1.005 7 V/V mV 5 V dB Differential Amplifier AV VOS Differential Gain Input Offset Voltage CM CMRR Common Mode Input Voltage Range Common Mode Rejection Ratio ICL GBP SR VO(MAX) RIN Output Current Gain Bandwidth Product Slew Rate Maximum High Output Voltage Input Resistance IN+ = IN– = 1.2V, IOUT = 1mA, Input Referred; Gain = 1 IOUT = 1mA 0V < IN+ = IN– < 5V, IOUT = 1mA, Input Referred 0 45 10 IOUT = 1mA RL = 2k IOUT = 1mA Measured at IN+ Pin Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3709EUH: TJ = TA + (PD • 34°C/W) Note 3: The LTC3709 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). 70 40 2 5 VCC – 1.2 VCC – 0.8 80 mA MHz V/µs V kΩ Note 4: The LTC3709E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 5: RDS(ON) limit is guaranteed by design and/or correlation to static test. 3709f 4 LTC3709 U W TYPICAL PERFOR A CE CHARACTERISTICS Start-Up Continuous Current Mode (CCM) Discontinuous Current Mode (DCM) VRUN/SS 5V/DIV VOUT 1V/DIV SW1 5V/DIV SW1 5V/DIV IL1 10A/DIV SW2 1V/DIV SW2 5V/DIV IL2 10A/DIV 1ms/DIV 3709 G01 3709 G02 2µs/DIV Transient Response (CCM) 3709 G03 10µs/DIV Transient Response (DCM) Efficiency vs Load Current 100 ILOAD 3A-18A VOUT 50mV/DIV VOUT 50mV/DIV VSW1 20V/DIV VSW1 20V/DIV VSW2 20V/DIV VSW2 20V/DIV 20µs/DIV VIN = 12V 95 VOUT = 1.5V f = 220kHz 90 85 EFFICIENCY (%) ILOAD 3A-18A 80 75 70 65 3709 G04 3709 G05 20µs/DIV 60 55 50 10 100 1000 LOAD (mA) 10000 100000 3709 G06 Efficiency vs VIN VIN = 12V VOUT = 1.5V f = 220kHz VOUT = 1.5V ILOAD = 10A f = 220kHz 95 EFFICIENCY (%) POWER LOSS (W) 1 Quiescent Current at VCC = 5V 3.0 100 QUIESCENT CURRENT (mA) Power Loss vs Load Current 10 0.1 0.01 90 85 0.001 10 1000 10000 100 LOAD CURRENT (mA) 100000 3709 G07 80 4 8 12 16 VIN (V) 20 24 3709 G08 2.8 2.6 2.4 2.2 2.0 –40 –20 40 20 0 TEMPERATURE (°C) 60 80 3709 G09 3709f 5 LTC3709 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Current at VCC = 5V Error Amplifier gm 45 EA Load Regulation 1.6 0.4 EA LOAD REGULATION (%) 1.5 35 EA gm (mS) SHUTDOWN CURRENT (µA) 40 30 1.4 25 1.3 0.3 0.2 0.1 20 15 –40 –20 40 20 0 TEMPERATURE (°C) 60 1.2 –40 80 –20 40 20 0 TEMPERATURE (°C) 60 3709 G10 VFB Pin Input Current RUN/SS Threshold 1.4 1.2 1.0 –45 –50 –40 –20 40 20 0 TEMPERATURE (°C) 60 0.8 –40 80 –20 40 20 0 TEMPERATURE (°C) 3709 G13 60 100 3.7 80 3709 G16 10 100 ION CURRENT (µA) 80 1000 VRNG = 2V 250 VRNG = VCC 200 VRNG = 1V 150 VRNG = 0V 100 50 VRNG = 0.5V 0 –50 –100 –150 10 60 60 3709 G15 CURRENT SENSE THRESHOLD (mV) ON-TIME (ns) 3.9 40 20 0 TEMPERATURE (°C) 300 1000 4.1 –20 Current Sense Threshold vs ITH Voltage 4.3 40 20 0 TEMPERATURE (°C) 2.5 2.0 –40 80 10000 –20 3.0 On-Time vs ION Current 4.5 3.5 –40 3.5 3709 G14 UVLO Threshold 80 Armed Threshold ARMED THRESHOLD (V) –40 60 4.0 1.6 RUN/SS THRESHOLD (V) VFB PIN INPUT CURRENT (nA) –25 –35 40 20 0 TEMPERATURE (°C) 3709 G12 1.8 –30 –20 3709 G11 –20 UVLO THRESHOLD (V) 0 –40 80 0 0.6 1.2 1.8 2.4 ITH VOLTAGE (V) 3709 G17 3709 G18 3709f 6 LTC3709 U W TYPICAL PERFOR A CE CHARACTERISTICS Minimum Current Sense Threshold Voltage vs VRNG 350 0 300 –20 MINIMUM CURRENT SENSE THRESHOLD VOLTAGE (mV) MAXIMUM CURRENT SENSE THRESHOLD VOLTAGE (mV) Maximum Current Sense Threshold Voltage vs VRNG 250 200 150 100 50 –40 –60 –80 –100 –120 0 0.5 0.8 1.1 1.4 1.7 2.0 –140 0.5 0.8 1.1 1.4 1.7 2.0 VRNG (V) VRNG (V) 3709 G19 3709 G20 U U U PI FU CTIO S RUN/SS (Pin 1): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 0.5s/µF) and the time delay for overcurrent latch-off (see Applications Information). Forcing this pin below 1.4V shuts down the device. SGND (Pins 5, 6, 33): Signal Ground. All small-signal components such as CSS and compensation components should connect to this ground and eventually connect to PGND at one point. The Exposed Pad of the QFN package must be soldered to PCB ground. ITH (Pin 2): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). VOS– (Pin 7): The (–) Input to the Differential Amplifer. VFB (Pin 3): Error Amplifier Feedback Input. This pin connects to the error amplifier input. It can be used to attach additional compensation components if desired. EXTLPF (Pin 10): Filter Connection for the PLL. This PLL is used to synchronize the LTC3709 with an external clock. TRACK (Pin 4): Tie the TRACK pin to a resistive divider connected to the output of another LTC3709 for either coincident or ratiometric output tracking (see Applications Information). To disable this feature, tie the pin to VCC. Do Not Float this pin. DIFFOUT (Pin 8): The Output of the Differential Amplifier. VOS+ (Pin 9): The (+) Input to the Differential Amplifier. INTLPF (Pin 11): Filter Connection for the PLL. This PLL is use to phase shift the second channel to the first channel by 180°. NC (Pin 12): No Connect. 3709f 7 LTC3709 U U U PI FU CTIO S VCC (Pin 17): Main Input Supply. Decouple this pin to SGND with an RC filter (1Ω, 0.1µF). DRVCC (Pin 21): Driver Supply. Provides supply to the driver for the bottom gate. Also used for charging the bootstrap capacitor. BOOST1, BOOST2 (Pins 28, 13): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below DRVCC up to VIN + DRVCC. BG1, BG2 (Pins 22, 20): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and DRVCC. PGOOD (Pin 29): Power Good Output. Open-drain logic output that is pulled to ground when output voltage is not within ±10% of the regulation point. The output voltage must be out of regulation for at least 100µs before the power good output is pulled to ground. PGND1, PGND2 (Pins 23, 19): Power Ground. Connect this pin closely to the source of the bottom N-channel MOSFET, the (–) terminal of CDRVCC and the (–) terminal of CIN. ION (Pin 30): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. SENSE1–, SENSE2 – (Pins 24, 18): Current Sense Comparator Input. The (–) input to the current comparator is used to accurately Kelvin sense the bottom side of the sense resistor or MOSFET. SENSE1+, SENSE2+ (Pins 25, 16): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information). SW1, SW2 (Pins 26, 15): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a Schottky diode voltage drop below ground up to VIN. FCB (Pin 31): Forced Continuous and External Clock Input. Tie this pin to ground to force continuous synchronous operation or to VCC to enable discontinuous mode operation at light load. Feeding an external clock signal into this pin will synchronize the LTC3709 to the external clock and enable forced continuous mode. VRNG (Pin 32): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maximum output current and can be programmed from 0.5V to 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to VCC. TG1, TG2 (Pins 27, 14): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to DRVCC superimposed on the switch node voltage SW. 3709f 8 LTC3709 W FU CTIO AL DIAGRA U U ION INTLPF RON VIN + FCB CIN CLOCK DETECTOR 0.6V REF FROM CHANNEL 2 TG EXTLPF VCC + CVCC PLL2 PLL1 BOOST TO CHANNEL 2 OST OST tON = 0.7 (30pF) IION R M1 ON Q SW S L1 20k + CB TG FCNT + ICMP DRVCC IREV – – SHDN DUPLICATE FOR SECOND CHANNEL + 5V COUT CDRVCC BG OV VOUT DB SENSE+ SWITCH LOGIC M2 PGND 1.4V SENSE– SHDN TO CHANNEL 2 SWITCH LOGIC VRNG × 0.7V – 3.3µA 0.66V OV – EA R2 + 1 240k VFB SGND Q4 R1 + – ITH UV CC PGOOD 0.54V + RC 100µs BLANKING SHED 40k RUN SHDN ITHB VOS 1.2µA 6V TRACK Q1 Q2 0.6V VREF Q3 –+ RUN/SS 1.4V + – 1.4V CSS + VOS– 40k 40k + DISABLE DIFFOUT – 40k 3709 FD 3709f 9 LTC3709 U OPERATIO (Refer to Functional Diagram) MAIN CONTROL LOOP The LTC3709 is a constant on-time, current mode stepdown controller with two channels operating 180 degrees out of phase. In normal operation, each top MOSFET is turned on for a fixed interval determined by its own oneshot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and repeating the cycle. The trip level of the current comparator is set by the ITH voltage, which is the output of error amplifier EA. Inductor current is determined by sensing the voltage between the SENSE – and SENSE+ pins using either the bottom MOSFET on-resistance or a separate sense resistor. At light load, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV, which then shuts off the bottom MOSFET, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Discontinuous mode operation is disabled when the FCB pin is tied to ground, forcing continuous synchronous operation. The main control loop is shut down by pulling the RUN/SS pin low, turning off both top MOSFET and bottom MOSFET. Releasing the pin allows an internal 1.2µA current source to charge an external soft-start capacitor CSS. When this voltage reaches 1.4V, the LTC3709 turns on and begins operating with a clamp on the noninverting input of the error amplifier. This input is also the reference input of the error amplifier. As the voltage on RUN/SS continues to rise, the voltage on the reference input also rises at the same rate, effectively controlling output voltage slew rate. Operating Frequency The operating frequency is determined implicitly by the top MOSFET on time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding the frequency approximately constant with changes in VIN. The nominal frequency can be adjusted with an external resistor RON. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious conditions that may overvoltage the output. In this condition, the top MOSFET is turned off and the bottom MOSFET is turned on and held on until the condition is cleared. Power Good (PGOOD) Pin Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. In addition, the output feedback voltage must be out of this window for a continuous duration of at least 100µs before the PGOOD is pulled low. This is to prevent any glitch on the feedback voltage from creating a false power bad signal. The PGOOD will indicate a good power immediately when the feedback voltage is in regulation. Short-Circuit Detection and Protection After the controller has been started and been given adequate time to charge the output capacitor, the RUN/SS capacitor is used in a short-circuit time-out circuit. If the output voltage falls to less than 67% of its nominal output voltage, the RUN/SS capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the RUN/SS capacitor, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latch off can be overridden by providing a >5µA pull-up at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during an overcurrent and/or shortcircuit condition. 3709f 10 LTC3709 U OPERATIO (Refer to Functional Diagram) DRVCC Dual Phase Operation Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the DRVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is normally recharged from DRVCC through an external Schottky diode DB when the top MOSFET is turned off. An internal phase-lock loop (PLL1) ensures that channel 2 operates exactly at the same frequency as channel 1 and is also phase shifted by 180°, enabling the LTC3709 to operate optimally as a dual phase controller. The loop filter connected to the INTLPF pin provides stability to the PLL. For external clock synchronization, a second PLL (PLL2) is incorporated into the LTC3709. PLL2 will adjust the ontime of channel 1 until its frequency is the same as the external clock. When locked, the PLL2 aligns the turn on of the top MOSFET of channel 1 to the rising edge of the external clock. Compensation for PLL2 is through the EXTLPF pin. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT+ and VOUT– benefits regulation in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground, preventing the possibility of troublesome “ground loops” on the PC layout and preventing voltage errors caused by board-to-board interconnects. Second Channel Shutdown During Light Loads When FCB is tied to VCC, discontinuous mode is selected. In this mode, no reverse current is allowed. The second channel is off when ITH is less than 0.8V for better efficiency. When FCB is tied to ground, forced continuous mode is selected, both channels are on and reversed current is allowed. 3709f 11 LTC3709 U W U U APPLICATIO S I FOR ATIO The basic LTC3709 application circuit is shown on the first page of this data sheet. External component selection is primarily determined by the maximum load current and begins with the selection of the power MOSFET switches and/or sense resistor. The inductor current is determined by the RDS(ON) of the synchronous MOSFET while the user has the option to use a sense resistor for a more accurate current limiting. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple specification. this resistor, connect the SENSE+ pin to the source end of the resistor and the SENSE– pin to the other end of the resistor. The SENSE+ and SENSE– pin connections provide the Kelvin connections, ensuring accurate voltage measurement across the resistor. Using a sense resistor provides a well-defined current limit, but adds cost and reduces efficiency. Alternatively, one can use the synchronous MOSFET as the current sense element by simply connecting the SENSE+ pin to the switch node SW and the SENSE– pin to the source of the synchronous MOSFET, eliminating the sense resistor. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed in the Power MOSFET Selection section. Maximum Sense Voltage and VRNG Pin Power MOSFET Selection Inductor current is determined by measuring the voltage across the RDS(ON) of the synchronous MOSFET or through a sense resistance that appears between the SENSE – and the SENSE+ pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately VRNG/7.5. The current mode control loop will not allow the inductor current valleys to exceed VRNG/(7.5 • RSENSE). In practice, one should allow some margin for variations in the LTC3709 and external component values. A good guide for selecting the sense resistance for each channel is: The LTC3709 requires four external N-channel power MOSFETs, two for the top (main) switches and two for the bottom (synchronous) switches. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). RSENSE = 2 • VRNG 10 • IOUT(MAX) The voltage of the VRNG pin can be set using an external resistive divider from VCC between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to ground or VCC, in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.3 times this nominal value. Connecting the SENSE + and SENSE – Pins The LTC3709 provides the user with an optional method to sense current through a sense resistor instead of using the RDS(ON) of the synchronous MOSFET. When using a sense resistor, it is placed between the source of the synchronous MOSFET and ground. To measure the voltage across The gate drive voltage is set by the 5V DRVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3709 applications. If the driver’s voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be used. When the bottom MOSFETs are used as the current sense elements, particular attention must be paid to their onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE ρT The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C. Junction-tocase temperature is about 20°C in most applications. For a maximum junction temperature of 100°C, using a value ρ100°C = 1.3 is reasonable (Figure 1). 3709f 12 LTC3709 U W U U APPLICATIO S I FOR ATIO ρT NORMALIZED ON-RESISTANCE 2.0 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3709 F01 Figure 1. RDS(ON) vs Temperature The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3709 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V –V = IN OUT VIN DTOP = DBOT bottom MOSFET losses are the greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low “on” resistance with significantly reduced input capacitance for the main switch application in switching regulators. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. The operating frequency of LTC3709 applications is determined implicitly by the one-shot timer that controls the on time, tON, of the top MOSFET switch. The on-time is set by the current into the ION pin according to: The maximum power dissipation in the MOSFETs per channel is: 2 ⎛ IOUT(MAX) ⎞ PTOP = DTOP • ⎜ ⎟ • ρT(TOP) • RDS(ON)(MAX) + 2 ⎝ ⎠ ⎛I ⎞ (0.5) • VIN2 • ⎜ OUT ⎟ • CRSS • f • ⎝ 2 ⎠ ⎛ 1 1 ⎞ + RDS(ON)_ DRV ⎜ ⎟ VGS(TH) ⎠ ⎝ DRVCC – VGS(TH) ( ) 2 ⎛ IOUT(MAX) ⎞ PBOT = DBOT • ⎜ ⎟ • ρT(BOT) • RDS(ON)(MAX) 2 ⎝ ⎠ Both top and bottom MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are the largest at maximum input voltages. The tON = 0.7 (30pF ) IION Tying a resistor from VIN to the ION pin yields an on-time inversely proportional to VIN. For a down converter, this results in approximately constant frequency operation as the input supply varies: f= VOUT 0.7 • RON (30pF ) PLL and Frequency Synchronization In the LTC3709, there are two on-chip phase-lock loops (PLLs). One of the PLLs is used to achieve frequency locking and phase separation between the two channels while the second PLL is for locking onto an external clock. Since the LTC3709 is a constant on-time architecture, the error signal generated by the phase detector of the PLL is 3709f 13 LTC3709 U W U U APPLICATIO S I FOR ATIO used to vary the on-time to achieve frequency locking and 180° phase separation. The synchronization is set up in a “daisy chain” manner whereby channel 2’s on-time will be varied with respect to channel 1. If an external clock is present, then channel 1’s on-time will be varied and channel 2 will follow suit. Both PLLs are set up with the same capture range and the frequency range that the LTC3709 can be externally synchronized to is between 2 • fC and 0.5 • fC, where fC is the initial frequency setting of the two channels. It is advisable to set initial frequency as close to external frequency as possible. A limitation of both PLLs is when the on-time is close to the minimum (100ns). In this situation, the PLL will not be able to synchronize up in frequency. To ensure proper operation of the internal phase-lock loop when no external clock is applied to the FCB pin, the INTLPF pin may need to be pulled down while the output voltage is ramping up. One way to do this is to connect the anode of a silicon diode to the INTLPF pin and its cathode to the PGOOD pin and connect a pull-up resistor between the PGOOD pin and VCC. Refer to Figure 9 for an example. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ⎛ V ⎞⎛ V ⎞ ∆IL = ⎜ OUT ⎟ ⎜ 1 – OUT ⎟ ⎝ f •L ⎠⎝ VIN ⎠ Lower ripple current reduces core losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX)/2. Note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: ⎛ VOUT ⎞ ⎛ VOUT ⎞ L=⎜ 1 – ⎟⎜ ⎟ ⎝ f • ∆IL(MAX) ⎠ ⎝ VIN(MAX) ⎠ Once the value for L is known, the inductors must be selected (based on the RMS saturation current ratings). A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida, Toko and Panasonic. Schottky Diode Selection The Schottky diodes conduct during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, which causes a modest (about 1%) efficiency loss. The diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between the diode and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. CIN and COUT Selection In continuous mode, the current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 2 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the input voltage is twice the output voltage. 3709f 14 LTC3709 U W U U APPLICATIO S I FOR ATIO In the Figure 2 graph, the local maximum input RMS capacitor currents are reached when: VOUT 2k – 1 = where k = 1, 2 VIN 4 These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a 2-phase system. The required amount of input capacitance is further reduced by the factor 2 due to the effective increase in the frequency of the current pulses. 0.5 DC LOAD CURRENT RMS INPUT RIPPLE CURRNET 0.6 0.4 1-PHASE 2-PHASE The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: ⎛ 1 ⎞ ∆VOUT ≤ ∆IL ⎜ ESR + ⎟ ⎝ 8 fCOUT ⎠ Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and longterm reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. High performance through-hole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. 0.3 Top MOSFET Driver Supply (CB, DB) 0.2 An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from DRVCC when the switch node is low. Note that the average voltage across CB is approximately DRVCC. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + DRVCC. The boost capacitor 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3709 F02 Figure 2. RMS Input Current Comparison 3709f 15 LTC3709 U W U U APPLICATIO S I FOR ATIO needs to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1µF to 0.47µF is adequate. Discontinuous Mode Operation and FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin to VCC enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which inductor current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current. The ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. Tying the FCB pin to ground forces continuous synchronous operation, allowing current to reverse at light loads and maintaining high frequency operation. Besides providing a logic input to force continuous operation, the FCB pin acts as the input for external clock synchronization. Upon detecting a TTL level clock and the frequency is higher than the minimum allowable, channel 1 will lock on to this external clock. This will be followed by channel 2 (see PLL and Frequency Synchronization). The LTC3709 will be forced to operate in forced continuous mode in this situation. Fault Conditions: Current Limit The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3709, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ⎛ VSNS(MAX) ⎞ 1 ILIMIT = ⎜ + • ∆IL ⎟ • 2 ⎝ RDS(ON) • ρT 2 ⎠ generally occurs with the largest VIN at the highest ambient temperature, conditions which cause the largest power loss in the converter. Note that it is important to check for self-consistency between the assumed junction temperature and the resulting value of ILIMIT, which heats the junction. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET on-resistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. For a more accurate current limiting, a sense resistor can be used. Sense resistors in the 1W power range are easily available with 5%, 2% or 1% tolerance. The temperature coefficient of these resistors are very low, ranging from ±250ppm/°C to ±75ppm/°C. In this case, the denominator in the above equation can simply be replaced by the RSENSE value. Minimum Off-Time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3709 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation in order to maintain the duty cycle at its limit. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT 1 1 – tOFF(MIN) • f A plot of maximum duty cycle vs frequency is shown in Figure 3. The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit 3709f 16 LTC3709 U W U U APPLICATIO S I FOR ATIO SWITCHING FREQUENCY (MHz) 2.0 RUN/SS 1.5 ∆V = 0.6V DROPOUT REGION ON THRESHOLD TIME 1.0 VOUT1 0.5 0 0 1.0 0.25 0.50 0.75 DUTY CYCLE (VOUT/VIN) TIME 3709 F04 3709 F03 Figure 3. Maximum Switching Frequency vs Duty Cycle Soft-Start and Latchoff with the RUN/SS Pin The RUN/SS pin provides a means to shut down the LTC3709 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 1.4V puts the LTC3709 into a low quiescent current shutdown (IQ < 30µA). Releasing the pin allows an internal 1.2µA internal current source to charge the external capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: tDELAY = 1.4V • CSS = ( 1.2 s / µF )CSS 1.2µA When the RUN/SS voltage reaches the ON threshold (typically 1.4V), the LTC3709 begins operating with a clamp on EA’s reference voltage. The clamp level is one ON threshold voltage below RUN/SS. As the voltage on RUN/SS continues to rise, EA’s reference is raised at the same rate, achieving monotonic output voltage soft-start (Figure 4). When RUN/SS rises 0.6V above the ON threshold, the reference clamp is invalidated and the internal precision reference takes over. After the controller has been started and given adequate time to charge the output capacitor, CSS is used as a shortcircuit timer. After the RUN/SS pin charges above 3V, and Figure 4. Monotonic Soft-Start Waveforms if the output voltage falls below 67% of its regulated value, then a short-circuit fault is assumed. A 2µA current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 2.5V, then the controller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 3V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: CSS > COUT VOUT RSENSE (10 –4 [F/VS]) Overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current of >5µA to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to VIN as shown in Figure 5 is simple, but slightly increases shutdown current. Any pull-up network must be able to pull RUN/SS above the 3V threshold that arms the latchoff circuit and overcome the 2µA maximum discharge current. 3709f 17 LTC3709 U W U U APPLICATIO S I FOR ATIO VCC RSS* VIN 3.3V OR 5V RUN/SS RSS* D1 D2* RUN/SS 2N7002 CSS CSS 3709 F05 *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (5a) (5b) Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated Output Voltage Tracking The feedback voltage, VFB, will follow the TRACK pin voltage when the TRACK pin voltage is less than the reference voltage, VREF (0.6V). When the TRACK pin voltage is greater than VREF, the feedback voltage will servo to VREF. When selecting components for the TRACK pin, ensure the final steady-state voltage on the TRACK pin is greater than VREF at the end of the tracking interval. The LTC3709 allows the user to set up start-up sequencing among different supplies in either coincident tracking or ratiometric tracking as shown in Figure 6. To implement the coincident tracking, connect an extra resistor divider to the output of supply 1. This resistor divider is selected to be the same as the divider across supply 2’s output. The TRACK pin of supply 2 is connected to this extra resistor divider. For the ratiometric tracking, simply connect the TRACK pin of supply 2 to the VFB pin of supply 1. Figure 7 shows this implementation. Note that in the coincident tracking, output voltage of supply 1 has to be set higher than output voltage of supply 2. Note that since the shutdown trip point varies from part to part, the “slave” part’s RUN/SS pin will need to be connected to VCC. This eliminates the possibility that different LTC3709s may shut down at different times. If output sequencing is not needed, connect the TRACK pins to VCC. Do Not Float these pins. SUPPLY 1 SUPPLY 2 VOUT1 R1 VFB TRACK VFB R2 R6 R4 3709 F07 R3 = R5 V COINCIDENTLY TRACKS VOUT1 R4 R6 OUT2 R3 = R1 RATIOMETRIC POWER UP R4 R2 BETWEEN VOUT1 AND VOUT2 Figure 7. Setup for Coincident and Ratiometric Tracking VOUT1 OUTPUT VOLTAGE OUTPUT VOLTAGE R5 R3 VOUT1 VOUT2 VOUT2 LTC3709 VOUT2 3709 F06 TIME TIME (6a) Coincident Tracking (6b) Ratiometric Tracking Figure 6. Two Different Forms of Output Voltage Sequencing 3709f 18 LTC3709 U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3709 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 0.1% up to 10% as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problems. The ITH pin external components shown in Figure 9 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Application Note 76. Design Example Transition Loss ≈ (0.5) • VIN2 • IOUT • CRSS • f • ⎛ 1 1 ⎞ RDS(ON)_ DRV ⎜ + ⎟ ⎝ DRVCC − VGS(TH) VGS(TH) ⎠ 3. Gate driver supply current. The driver current supplies the gate charge QG required to switch the power MOSFETs. This current is typically much larger than the control circuit current. In continuous mode operation: IGATECHG = f (Qg(TOP) + Qg(BOT)) 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from As a design example, take a supply with the following specifications: VIN = 7V to 28V (15V nominal), VOUT = 2.5V, IOUT(MAX) = 20A, f = 250kHz. First, calculate the timing resistor: RON = 2.5V = 476k (0.7V)(250kHz)(30pF ) and choose the inductor for about 40% ripple current at the maximum VIN. Maximum output current for each channel is 10A: L= 2.5V ⎛ 2.5V ⎞ ⎜ 1− ⎟ = 2.3µH (250kHz)(0.4)(10A) ⎝ 28V ⎠ 3709f 19 LTC3709 U W U U APPLICATIO S I FOR ATIO Selecting a standard value of 1.8µH results in a maximum ripple current of: 2.5V ⎛ 2.5V ⎞ ∆IL = ⎜ 1– ⎟ = 5.1A (250kHz)(1.8µH) ⎝ 28V ⎠ Next, choose the synchronous MOSFET switch. Choosing a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX), qJA = 40°C/W) yields a nominal sense voltage of: VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV Tying VRNG to 1.1V will set the current sense voltage range for a nominal value of 110mV with current limit occurring at 146mV. To check if the current limit is acceptable, assume a junction temperature of about 80°C above a 70°C ambient with ρ150°C = 1.5: ⎛ ⎞ 146mV 1 ILIMIT ≥ ⎜ + (5.1A)⎟ • 2 = 24A ⎝ (1.5)(0.010Ω) 2 ⎠ and double check the assumed TJ in the MOSFET: 2 PBOT 28 V – 2 .5V ⎛ 24A ⎞ = ⎜ ⎟ (1.5 )(0.010 Ω) = 1.97 W ⎝ 2 ⎠ 28 V TJ = 70°C + (1.97W)(40°C/W) = 149°C Because the top MOSFET is on for such a short time, an Si4884 RDS(ON)(MAX) = 0.0165Ω, CRSS = 100pF, θJA = 40°C/W will be sufficient. Checking its power dissipation at current limit with ρ100°C = 1.4: 2 PTOP 2.5V ⎛ 24A ⎞ = ⎜ ⎟ (1.4)(0.0165Ω) + 28 V ⎝ 2 ⎠ (1.7)(28V)2 (12A)(100pF )(250kHz) = 0.30W + 0.40W = 0.7W TJ = 70°C + (0.7W)(40°C/W) = 98°C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 10A at 85°C. The output capacitors are chosen for a low ESR of 0.013Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (5.1A) (0.013Ω) = 66mV However, a 0A to 10A load step will cause an output change of up to: ∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV An optional 22µF ceramic output capacitor is included to minimize the effect of ESL in the output ripple. The complete circuit is shown in Figure 9. PC Board Layout Checklist When laying out a PC board follow one of the two suggested approaches. The simple PC board layout requires a dedicated ground plane layer. Also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. • The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. • Place CIN, COUT, MOSFETs, D1, D2 and inductors all in one compact area. It may help to have some components on the bottom side of the board. • Use an immediate via to connect the components to ground plane including SGND and PGND of LTC3709. Use several larger vias for power components. • Use a compact plane for switch node (SW) to keep EMI down. • Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. • Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power component. You can connect the copper areas to any DC net (VIN, VOUT, GND or to any other DC rail in your system). When laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in Figure 9. 3709f 20 LTC3709 U W U U APPLICATIO S I FOR ATIO • Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point, which is then tied to a “clean” point in the power ground such as the “–” node of CIN. • Keep the high dV/dt SW, BOOST and TG nodes away from sensitive small-signal nodes. • Minimize impedance between input ground and output ground. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect PGND1 to the source of M2 or RS1 (QFN) directly. This also applies to channel 2. • Connect the VIN pin decoupling capacitor CF closely to the VCC and PGND pins. • Place M2 as close to the controller as possible, keeping the PGND1, BG1 and SW1 traces short. The same for the other channel. SW2 trace should connect to the drain of M2 directly. • Are the SENSE– and SENSE+ leads routed together with minimum PC trace spacing? The filter capacitor between SENSE– and SENSE+ (CSENSE) should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the sense resistor as shown in Figure 8. • Connect the input capacitor(s) CIN close to the power MOSFETs: (+) node to drain of M1, (–) node to source of M2. This capacitor carries the MOSFET AC current. D G D S D S D S • Connect the DRVCC decoupling capacitor CVCC closely to the DRVCC and PGND pins. RSENSE MOSFET SENSE + SENSE – SENSE + SENSE – (8a) Sensing the Bottom MOSFET 3709 F08 (8b) Sensing a Resistor Figure 8. Kelvin Sensing 3709f 21 LTC3709 U W U U APPLICATIO S I FOR ATIO MMSD4148 (OPTIONAL) 10nF CSS 0.1µF 1 RC 20k CC 470pF 2 100pF 3 4 TRACK 100pF RF2 10k RF1 31.6k 100nF 5 RUN/SS VRNG FCB ITH VFB ION TRACK PGOOD 31 30 29 28 SGND BOOST1 SGND TG1 7 VOS– SW1 8 DIFFOUT SENSE1+ 25 9 VOS+ 24 6 SENSE1 – 10k 32 27 35.7k fIN RON 476k VIN 7V TO 28V RPGOOD 100k PGOOD DRVCC 5V D1 B340A DB1 CMDSH-3 CB1 0.22µF M1 M2 L1 1.8µH 26 100pF 475Ω LTC3709EUH 1nF 10 3.32k 11 470pF 12 13 CB2 0.22µF 14 15 16 EXTLPF PGND1 INTLPF BG1 NC DRVCC BOOST2 BG2 TG2 PGND2 SW2 SENSE2 – SENSE2 + VCC 100pF 23 + 100nF COUT 180µF 4V ×4 CIN 10µF 35V ×3 22 1µF VOUT 2.5V 20A 21 20 1µF 19 18 17 L2 1.8µH 10Ω M3 1µF M4 DB2 CMDSH-3 L1, L2: PANASONIC ETQP6FIR8BFA COUT: PANASONIC EEFUEOG181R M1, M3: SILICONIX Si4884DY M2, M4: SILICONIX Si4874DY D2 B340A 3709 F09 Figure 9. 2-Phase 2.5V/20A Supply at 250kHz with Tracking and External Synch 3709f 22 LTC3709 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.23 TYP (4 SIDES) R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH) QFN 0603 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 3709f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC3709 U TYPICAL APPLICATIO Low Output Ripple, 2-Phase 12V/30A Supply CSS 0.1µF 1 RC 20k CC 1nF 2 3 220pF 4 5V 5 RUN/SS VRNG ITH FCB VFB ION TRACK PGOOD SGND BOOST1 32 10nF 31 RON 2.86M 30 29 RPGOOD 100k 3.32k 470pF CB2 0.22µF 27 SGND TG1 LTC3709 7 26 VOS– SW1 8 25 DIFFOUT SENSE1+ 9 24 SENSE1 – VOS+ 10 23 EXTLPF PGND1 11 22 INTLPF BG1 12 21 NC DRVCC 13 20 BG2 BOOST2 14 19 PGND2 TG2 15 18 SENSE2 – SW2 16 17 VCC SENSE2 + VIN 24V D1 B340A DRVCC 5V L1 4.7µH TOKO FDA1254 CB1 0.22µF M1 M2 COUT 150µF 16V ×3 100pF 100pF + 100nF RF1 190k DB1 CMDSH-3 28 6 RF2 10k 10k 21.5k 1µF VOUT CIN 10µF 35V ×3 1µF L2 4.7µH 10Ω 1µF DB2 CMDSH-3 M3 M4 D2 B340A M1-M4: RENESAS HAT2167 COUT: OS-CON 16SVP150M 3709 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1708 Fast 2-Phase Dual Output Step-Down Controller PLL, VIN up to 36V, Tracking LTC1778 Wide Operating Range, No RSENSE Step-Down Controller Single Channel, GN16 Package LTC3413 DDR, QDR Memory Termination Regulator ±3A Output Current, 90% Efficiency LTC3708 Fast, Dual No RSENSE, 2-Phase Synchronous Step-Down Controller Very Fast Transient Response; Very Low Duty Factor Tracking; Minimum CIN, COUT LTC3728 Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator Fixed Frequency, Dual Output LTC3729 ® 550kHz, PolyPhase , High Efficiency, Synchronous Step-Down Switching Regulator Fixed Frequency, Single Output, Up to 12-Phase Operation LTC3730/LTC3731 3-Phase to 12-Phase Synchronous Step-Down Controllers LTC3732 40A to 240A, 4.5V ≤ VIN ≤ 32V, 0.6V ≤ VOUT ≤ 5V LTC3778 Single Channel, Separate VON Programming Wide Operating Range, No RSENSE Step-Down Controller PolyPhase is a registered trademark of Linear Technology Corporation. 3709f 24 Linear Technology Corporation LT/TP 1104 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004