LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit Datasheet The Intel® LXT3108 is an octal 3.3V Long Haul/Short Haul (LH/SH) T1/E1/J1 Line interface unit (LIU). This flexible LIU allows the design of T1/E1/J1 LH/SH multi-service cards with a single design and one bill-of-material. The LXT3108 LIU can be configured on a per-port basis through software. Intel’s proven design robustness makes the LXT3108 LIU the perfect device for high-density T1/E1/J1 applications. To increase network reliability, Intel’s LXT3108 incorporates a DSP-based architecture with features such as Intel® Hitless Protection Switching (Intel® HPS) and Intel® Pulse Template Matching (Intel® PTM). The DSP-based architecture is less sensitive to power supply and temperature variations and allows the LIU to adapt to varying line conditions. Intel® HPS allows the design of 1+1 redundant cards without the use of relays as well as the ability to switch from one card to another without a loss of frame synchronization. Intel® PTM software allows the transmitter to shape the output pulse to meet various board conditions, without the need to change any external components. Applications ■ ■ ■ ■ Voice over packet gateways Integrated Multi-service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse multiplexing for ATM (IMA) ■ ■ ■ ■ Wireless base stations Routers Frame relay access devices CSU/DSU equipment Product Features ■ ■ ■ ■ ■ ■ Intel® HPS for 1+1 protection without relays Intel® PTM software for pulse output adjustment through software without component or board change Interfaces with IXF3208, Octal T1/E1/J1 Framer with Intel® On-Chip Performance Report Messaging (Intel® On-Chip PRM) T1 (100 Ohm), E1 (75 and 120 Ohm), J1 (110 Ohm) termination and LH/SH selectable per port through software without component change Receiver sensitivity exceeds 36 dB @ 772 KHz and 43 dB @ 1024 KHz of cable attenuation providing margin for board and cable variations 3.3V power supply with 5V tolerant inputs ■ ■ ■ ■ ■ ■ On chip Clock Adaptor (CLAD) that allows one master clock for T1/E1/J1 applications (1X, 2X, 4X or 8X T1 or E1 clock) 16 bit BPV/Excess Zero counters per port B8ZS/HDB3 encoders and decoders, and unipolar/bipolar I/O modes selectable per port Digital Jitter Attenuator (DJA) in either receive or transmit path Meets or exceeds specifications in ANSI T1.102, T1.403 and T1.408; ITU I.431, CTR12/13, G.703, G.736, G.775 and G.823; ETSI 300-166 and 300-233; and AT&T Pub 62411 Available in a 17x17mm 256 PBGA (LXT3108 BE) or 28x28mm 208 QFP (LXT3108 HE) package LXT3108 — Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit Order Number: 249543-003 January 2002 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT3108 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Octal T1/E1/J1 LH/SH LIU — LXT3108 Contents 1.0 Pin Assignments and Signal Descriptions .................................................... 10 2.0 Signal Descriptions ................................................................................................. 12 3.0 T1/E1 Nomenclature ................................................................................................ 22 4.0 LXT3108 Nomenclature.......................................................................................... 23 5.0 Functional Description........................................................................................... 23 6.0 Software Support ..................................................................................................... 26 7.0 LIU Functional Description .................................................................................. 26 8.0 Initialization ................................................................................................................ 28 8.1 8.2 8.3 8.4 9.0 Transmitter.................................................................................................................. 30 9.1 9.2 10.0 10.3 10.4 Digital Jitter Attenuator (DJA) Status................................................................... 40 Network Control and Maintenance Functions .............................................. 40 12.1 Datasheet Master Reference Clock...................................................................................... 36 Receiver Digital Interface .................................................................................... 36 10.2.1 Receiver Idle Conditions ........................................................................ 37 Receiver Line Interface ....................................................................................... 37 10.3.1 Receive Termination Impedance............................................................ 37 10.3.2 Receiver Sensitivity Programming ......................................................... 38 Receiver Status Information ................................................................................ 39 Jitter Attenuation (JA) ............................................................................................ 39 11.1 12.0 Transmit Line Interface........................................................................................ 31 9.1.1 Transmit Impedance Termination........................................................... 32 9.1.2 Transmit Return Loss Performance ....................................................... 33 Transmit Digital Interface .................................................................................... 34 9.2.1 Transmit Idle Operation and Three Stating Drivers................................ 35 Receiver ....................................................................................................................... 36 10.1 10.2 11.0 CLAD Initialization ............................................................................................... 28 Reset Operation .................................................................................................. 28 5V Tolerant I/O Pins ............................................................................................ 28 Power Supply Requirements............................................................................... 29 8.4.1 Ground Plane ......................................................................................... 29 8.4.2 Analog Power Supply ............................................................................. 29 8.4.3 Digital Power Supply .............................................................................. 30 Diagnostic Modes................................................................................................ 40 12.1.1 In-Band Network Loop Up or Down Code Generator/Detector .............. 40 12.1.2 Analog Loopback.................................................................................... 41 12.1.3 Digital Loopback..................................................................................... 41 12.1.4 Remote Loopback .................................................................................. 42 12.1.5 Transmit All Ones (TAOS)...................................................................... 42 3 LXT3108 — Octal T1/E1/J1 LH/SH LIU 12.2 12.3 13.0 Host Interface ............................................................................................................ 49 13.1 13.2 14.0 Global Registers.................................................................................................. 54 Port Page Register Bank (PPRB) ....................................................................... 56 JTAG Boundary Scan ............................................................................................. 64 15.1 15.2 15.3 16.0 Supported Processors and Connections............................................................. 49 13.1.1 MPC860/M68360 ................................................................................... 49 13.1.2 M68302 .................................................................................................. 50 13.1.3 i960/i486................................................................................................. 50 Interrupts ............................................................................................................. 51 13.2.1 Interrupt Enable...................................................................................... 51 13.2.2 Interrupt Clearing ................................................................................... 52 Register Definitions ................................................................................................ 54 14.1 14.2 15.0 Line Coding ......................................................................................................... 43 12.2.1 Alternate Mark Inversion (AMI)............................................................... 44 Network Maintenance Functions......................................................................... 45 12.3.1 Loss Of Signal (LOS) ............................................................................. 45 12.3.2 Alarm Indication Signal (AIS) ................................................................. 47 12.3.3 NLOOP Status ....................................................................................... 47 12.3.4 Monitoring BPV and EXZ Line Coding Violations................................... 49 Architecture ......................................................................................................... 64 TAP Controller..................................................................................................... 64 JTAG Register Description.................................................................................. 66 15.3.1 Boundary Scan Register (BSR).............................................................. 67 15.3.2 Device Identification Register (IDR) ....................................................... 67 15.3.3 Bypass Register (BYR) .......................................................................... 67 15.3.4 Instruction Register (IR) ......................................................................... 67 Test Specifications .................................................................................................. 68 16.1 16.2 Microprocessor Interface Timing Diagrams ........................................................ 79 Referenced Standards ........................................................................................ 86 17.0 Mechanical Specification ...................................................................................... 87 18.0 Glossary ....................................................................................................................... 89 4 Datasheet Octal T1/E1/J1 LH/SH LIU — LXT3108 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Datasheet LXT3108 Block Diagram ....................................................................................... 9 LXT3108 HE 208 Pin Assignment....................................................................... 10 LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments .......................... 11 LXT3108 Port Block ............................................................................................ 23 LXT3108 Port Circuit ........................................................................................... 24 Transmitter Circuit for Twisted Pair and Coaxial Cable....................................... 25 T1/E1/J1 LIU Block Diagram ............................................................................... 27 Diode Protection Network When Inputs Power Up Before Supplies ................... 29 50% AMI Encoding.............................................................................................. 31 Typical Transmitter Interface Connections.......................................................... 31 T1, T1.102 Mask Templates................................................................................ 33 Transmit Interface Timing.................................................................................... 35 TCLK Power Down Timing .................................................................................. 36 Typical Receiver Interface................................................................................... 37 Jitter Attenuation Loop ....................................................................................... 39 Analog Loopback................................................................................................. 41 Digital Loopback.................................................................................................. 42 Remote Loopback ............................................................................................... 42 TAOS Data Path.................................................................................................. 43 TAOS with Digital Loopback................................................................................ 43 TAOS with Analog Loopback .............................................................................. 43 Interrupt Processing FlowChart........................................................................... 53 LXT3108 JTAG Architecture ............................................................................... 64 JTAG State Diagram ........................................................................................... 66 Transmit Clock Timing Diagram .......................................................................... 72 Receive Clock Timing Diagram ........................................................................... 74 LXT3108 Output Jitter for CTR12/13 Applications .............................................. 75 JTAG Timing ....................................................................................................... 75 E1, G.703 Mask Templates................................................................................. 76 LXT3108 Jitter Tolerance Performance .............................................................. 77 LXT3108 Jitter Transfer Performance ................................................................. 78 MPC860 Write Timing ......................................................................................... 79 MPC860 Read Timing ......................................................................................... 80 M68302 Write Timing .......................................................................................... 81 M68302 Read Timing .......................................................................................... 82 i486/i960 Nonmuxed Mode Write Timing ............................................................ 83 i960 Muxed Mode Write Timing........................................................................... 83 i486/i960 Nonmuxed Mode Read Timing ............................................................ 84 i960 Muxed Mode Read Timing .......................................................................... 85 LXT3108 256 PBGA Mechanical Specification ................................................... 87 LXT3108 208 Pin QFP Mechanical Specifications ............................................. 88 5 LXT3108 — Octal T1/E1/J1 LH/SH LIU Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 6 LXT3108 Pin Description .................................................................................... 12 CLAD Initialization Options ................................................................................. 28 Transformer Specifications for the LXT3108....................................................... 31 Preset Pulse Shaping Settings and Conditions................................................... 32 Transmit Return Loss Specifications for Frequency Range and Magnitude ....... 33 Powering Down the Transmitter with Static TCLK .............................................. 35 Programming Receiver Sensitivity ...................................................................... 38 Jitter Attenuation Specifications .......................................................................... 40 LOS Criteria for LXT3108.................................................................................... 46 LOS Register Configurations .............................................................................. 46 LOS Selection Defaults ....................................................................................... 46 AIS Service Condition Variations ........................................................................ 47 Excess Zero (EXZ) Definitions ............................................................................ 48 MPC860/M68360 Mode 8-Bit Mode.................................................................... 50 68302 8-bit mode ................................................................................................ 50 i960/i486 Mode.................................................................................................... 51 Port Page Select Register, CPS, 00h ................................................................. 55 ID Register, ID, 01h............................................................................................. 55 Interrupt Port Register, ICR, 02h......................................................................... 55 CLAD Configuration Register1, 11h3 .................................................................................... 56 Port Master Control Page Register, 01h ............................................................. 57 Port Receive Enable Page Register, 02h............................................................ 58 Transmit Control Page Register, 03h.................................................................. 58 Receive Control Page Register, 04h ................................................................... 58 Termination Control Page Register, 05h............................................................. 59 Receiver Equalizer Status Zero Page Register, 06h........................................... 59 Receiver Equalizer Status One Page Register, 07h ........................................... 59 Receiver Equalizer Status Two Page Register, 08h ........................................... 60 LOS Window Page Register, 0Bh ....................................................................... 60 LOS Set Threshold One Page Register, 0Ch ..................................................... 60 LOS Reset Threshold Two Page Register, 0Dh ................................................. 60 Loopback Enable Page Register, 10h................................................................. 61 Interrupt Enable Page Register, 11h................................................................... 61 Alarm Status One Page Register, 12h ................................................................ 61 Interrupt Status Two Page Register, 13h ............................................................ 62 Line Coding Control One Page Register, 1Ch .................................................... 62 JA Control Two Page Register, 1Dh ................................................................... 63 DJA Corner Frequency Selection........................................................................ 63 BPV Counter High Byte Page Register, 1Eh ...................................................... 63 BPV Counter Low Byte Page Register, 1Fh ....................................................... 63 Transmit Coefficient Page Register Range, 40h-6Fh ......................................... 64 TAP State Description......................................................................................... 65 Device Identification Register (IDR) .................................................................... 67 Instruction Register (IR) ...................................................................................... 67 Absolute Maximum Ratings ................................................................................ 68 Recommended Operating Conditions ................................................................. 68 Electrical Characteristics (Over Recommended Operating Conditions) ............. 69 E1 Transmitter Analog Characteristics................................................................ 69 E1 Receiver Analog Characteristics.................................................................... 70 Datasheet Octal T1/E1/J1 LH/SH LIU — LXT3108 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Datasheet T1 Transmitter Analog Characteristics ................................................................ 70 T1 Receiver Analog Characteristics .................................................................... 71 Master and Transmit Clock Timing Characteristics............................................. 72 Jitter Attenuator Characteristics .......................................................................... 73 Receive Timing Characteristics for T1 Operation................................................ 74 Receive Timing Characteristics for E1 Operation ............................................... 74 JTAG Timing Characteristics............................................................................... 75 G.703 2.048 Mbps Pulse Mask Specifications .................................................... 76 T1.102 1.544 Mbps Pulse Mask Specifications................................................... 76 MPC860 Write Timing Characteristics ................................................................ 79 MPC860 Read Timing Characteristics ................................................................ 80 M68302 Write Timing Characteristics ................................................................. 81 M68302 Read Timing Characteristics ................................................................. 82 i486/i960 Write Timing Characteristics................................................................ 84 i486/i960 Read Timing Characteristics................................................................ 85 7 LXT3108 — Octal T1/E1/J1 LH/SH LIU Revision History 8 Revision Date Description -002 07/15/01 Modified Pages: 1, 22 - 28, and 30. Modified Tables: 1, 2, 44 - 53. Modified Figures:1-3, 5-7, 10, 11, 15, 26, 38 & 39. Modified: TOC, LOF and LOT. Added glossary. -003 01/18/02 Modified Figures: 1 - 3, 5 - 7, 10, 14, 15, 32 - 36, and 38. Modified Tables: 1, 5, 9 - 11, 14 - 18, 20, 22, 23, 26, 29 - 31, 33 - 36, 39, 40, 45, 47, 48, 50 - 55, 61 - 63, 65, and 66. Modified Sections: 8.1, 8.2, 9.0, 9.2.1, 10.1, 10.2, 10.2.1, 10.3.1, 10.3.2, 11.0, 12.1.5, 12.3.2, 12.3.3.1, 12.3.3.2, 12.3.4, 13.0, 13.1, 13.2, 13.2.1, and 16.2. Deleted Section: 16.1 and 16.1.1 - 4. Deleted Tables: 58 - 61. Datasheet DB7..0 AD7..0 MCLK SOFTWARE CONTROL LOS LOS Equalizer RTIP PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK LINE DRIVER DIGITAL LOOPBACK TRING ANALOG LOOPBACK RRING TTIP DATA CLOCK CLOCK RECOVERY Figure 1. LXT3108 Block Diagram Datasheet JTAG PORT RPOS RCLK RNEG TPOS TCLK TNEG B8ZS / HDB3 DECODER B8ZS / HDB3 ENCODER 0 1 3 4 5 6 7 9 LXT3108 — Octal T1/E1/J1 LH/SH LIU 2 LXT3108 — Octal T1/E1/J1 LH/SH LIU Pin Assignments and Signal Descriptions LXT3108 HE (Top View) Figure 2. LXT3108 HE 208 Pin Assignment VCCIO ..... 53 DVCC ..... 54 DVSS ..... 55 AVCC ..... 56 RRING0 ..... 57 RTIP0 ..... 58 AVSS ..... 59 TXVSS ..... 60 TXVCC ..... 61 TVSS ..... 62 TRING0 ..... 63 TTIP0 ..... 64 TVSS ..... 65 DVSS ..... 66 DVCC ..... 67 TVSS ..... 68 TTIP1 ..... 69 TRING1 ..... 70 TVSS ..... 71 TXVCC ..... 72 TXVSS ..... 73 AVSS ..... 74 RTIP1 ..... 75 RRING1 ..... 76 AVCC ..... 77 DVSS ..... 78 DVCC ..... 79 AVCC ..... 80 RRING2 ..... 81 RTIP2 ..... 82 AVSS ..... 83 TXVSS ..... 84 TXVCC ..... 85 TVSS ..... 86 TRING2 ..... 87 TTIP2 ..... 88 TVSS ..... 89 DVCC ..... 90 DVSS ..... 91 TVSS ..... 92 TTIP3 ..... 93 TRING3 ..... 94 TVSS ..... 95 TXVCC ..... 96 TXVSS ..... 97 AVSS ..... 98 RTIP3 ..... 99 RRING3 ..... 100 AVCC ..... 101 DVSS ..... 102 DVCC ..... 103 GNDIO ..... 104 Datasheet 208..... GNDI0 207..... DVCC 206..... DVSS 205..... AVCC 204..... RRING7 203..... RTIP7 202..... AVSS 201..... TXVSS 200..... TXVCC 199..... TVSS 198..... TRING7 197..... TTIP7 196..... TVSS 195..... DVSS 194..... DVCC 193..... TVSS 192..... TTIP6 191..... TRING6 190..... TVSS 189..... TXVCC 188..... TXVSS 187..... AVSS 186..... RTIP6 185..... RRING6 184..... AVCC 183..... DVSS 182..... DVCC 181..... AVCC 180..... RRING5 179..... RTIP5 178..... AVSS 177..... TXVSS 176..... TXVCC 175..... TVSS 174..... TRING5 173..... TTIP5 172..... TVSS 171..... DVCC 170..... DVSS 169..... TVSS 168..... TTIP4 167..... TRING4 166..... TVSS 165..... TXVCC 164..... TXVSS 163..... AVSS 162..... RTIP4 161..... RRING4 160..... AVCC 159..... DVSS 158..... DVCC 157..... INTR 52........ GNDIO 51........ TCLK0 50........ TNEG0 49........ TPOS0/ TDATA0 48........ RCLK0 47........ RNEG0 46........ RPOS0/ RDATA0 45........ TCLK1 44........ TNEG1 43........ TPOS1/ TDATA1 42........ RCLK1 41........ RNEG1 40........ RPOS1/ RDATA1 39........ TCLK2 38........ TNEG2 37........ TPOS2/ TDATA2 36........ RCLK2 35........ RNEG2 34........ RPOS2/ RDATA2 33........ TCLK3 32 ....... TNEG3 31........ TPOS3/ TDATA3 30........ RCLK3 29........ RNEG3 28........ RPOS3/ RDATA3 27........ VCCIO 26........ GNDIO 25........ TCLK4 24........ TNEG4 23........ TPOS4/ TDATA4 22........ RCLK4 21........ RNEG4 20........ RPOS4/ RDATA4 19........ TCLK5 18........ TNEG5 17........ TPOS5/ TDATA5 16........ RCLK5 15........ RNEG5 14........ RPOS5/ RDATA5 13........ TCLK6 12........ TNEG6 11........ TPOS6/ TDATA6 10........ RCLK6 9 .......... RNEG6 8 .......... RPOS6/ RDATA6 7 .......... TCLK7 6 .......... TNEG7 5 .......... TPOS7/ TDATA7 4 .......... RCLK7 3 .......... RNEG7 2 .......... RPOS7/ RDATA7 1 .......... VCCIO 1.0 10 VCCIO ..... 105 JRST ..... 106 TMS ..... 107 TDO ..... 108 TDI ..... 109 TClK ..... 110 RSTB ..... 111 LOS0 ..... 112 LOS1 ..... 113 LOS2 ..... 114 LOS3 ..... 115 LOS4 ..... 116 LOS5 ..... 117 LOS6 ..... 118 LOS7 ..... 119 TYPE2 ..... 120 TYPE1 ..... 121 CS ..... 122 MCLK ..... 123 NC ..... 124 NC ..... 125 VMOAT ..... 126 RBIAS ..... 127 QVSS ..... 128 QVCC ..... 129 OE ..... 130 GNDIO ..... 131 VCCIO ..... 132 DB0 ..... 133 DB1 ..... 134 DB2 ..... 135 DB3 ..... 136 GNDIO ..... 137 VCCIO ..... 138 DB4 ..... 139 DB5 ..... 140 DB6 ..... 141 DB7 ..... 142 GNDIO ..... 143 VCCIO ..... 144 A0 ..... 145 A1 ..... 146 A2 ..... 147 A3 ..... 148 A4 ..... 149 A5 ..... 150 A6 ..... 151 A7 ..... 152 RW ..... 153 DS ..... 154 RDY ..... 155 MPI_CLK/ALE ..... 156 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 3. LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments Top View 1 2 3 A VCCIO DVCC B RPOS7 RNEG7 VSS C TPOS7 TNEG7 AVCC D 4 5 6 7 TTIP7 TTIP6 TXVCC RTIP7 TRING7 DVCC VSS VSS VSS RNEG6 RCLK6 RPOS6 TCLK7 RCLK7 E TCLK6 RPOS5 TNEG6 TPOS6 F RCLK5 TNEG5 G 8 10 11 12 13 14 15 16 TRING4 TXVCC RRING4 AVCC DVCC A RRING5 TTIP5 TTIP4 TRING6 RTIP6 AVCC VSS TRING5 VSS VSS RTIP4 INTR RW B RRING6 RTIP5 TXVCC VSS VSS DVCC VSS ALE/ MPI_CLK A7 A4 C VSS VSS VSS DVCC VSS VSS RDY DS A5 A3 A1 D VSS VSS VSS VSS VSS VSS VSS VSS A6 VCCIO A0 DB7 E TPOS5 RNEG5 VSS VSS VSS VSS VSS VSS VSS VSS A2 DB5 DB6 VCCIO F RPOS4 RCLK4 RNEG4 TCLK5 VSS VSS VSS VSS VSS VSS VSS VSS VSS DB3 VSS DB1 G H TNEG4 TCLK4 TPOS4 VSS VSS VSS VSS VSS VSS VSS VSS DB4 DB0 VCCIO OE H J VCCIO RCLK3 RNEG3 RPOS3 VSS VSS VSS VSS VSS VSS VSS VSS DB2 RBIAS VSS GND J K TPOS3 RNEG2 TCLK3 TNEG3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VMOAT GND TYPE1 K L RPOS2 TCLK2 TPOS2 RCLK2 VSS VSS VSS VSS VSS VSS VSS VSS QVCC CS TYPE2 LOS5 L M TNEG2 TPOS1 RNEG1 RPOS1 VSS VSS VSS VSS NC VSS VSS VSS MCLK LOS6 LOS4 LOS2 M N RCLK1 RPOS0 TNEG1 VSS VSS DVCC VSS VSS AVCC LOS7 LOS3 LOS1 LOS0 TCK N P TCLK1 TNEG0 VSS TXVCC RRING1 AVCC VSS VSS TXVCC VSS RSTB TDI TDO P R TPOS0 VCCIO RRING0 TXVCC TRING0 TTIP1 RTIP1 AVCC RTIP2 TRING2 DVCC VSS RTIP3 DVCC TMS JRST R T DVCC DVCC AVCC RTIP0 TTIP0 DVCC TRING1 VSS RRING2 TXVCC TTIP2 TTIP3 TRING3 RRING3 VSS VCCIO T 1 2 3 4 5 6 8 9 10 11 13 14 Datasheet VSS RRING7 TXVCC TCLK0 RNEG0 RCLK0 VSS VSS 7 AVCC 9 12 15 16 11 LXT3108 — Octal T1/E1/J1 LH/SH LIU 2.0 Signal Descriptions Table 1. LXT3108 Pin Description QFP PBGA Symbol I/O 1 A1 VCCIO S Description Power (I/O). Receive Positive Data/Receive Data Output (Port. 7). In bipolar mode this digital framer interface pin acts as the positive side of the bipolar data output pair, RPOS7 and RNEG7, recovered from the line interface. In unipolar mode, RDATA7 digital framer interface pin acts as a single Non-Return-to-Zero (NRZ) output of the data recovered from the line interface. Bipolar Mode: 2 B1 RPOS7/ RDATA7 DO This pin acts as an active high NRZ receive data output. A High signal on RPOS7 corresponds to receipt of a positive pulse on RTIP/RRING. A High signal on RNEG7 corresponds to receipt of a negative pulse on RTIP/RRING. As default this signal along with RNEG7 is valid on the falling edge of RCLK7. The LXT3108 can be programmed to validate the RPOS7 and RNEG7data on the rising edge of the RCLK7. This rule applies to all ports (0 through 7). Unipolar Mode: RDATA7 acts as the receive data output. Receive Negative Data (Port. 7). In bipolar mode this digital framer interface pin acts as the negative side of the bipolar data output pair, RPOS7 and RNEG7, recovered from the line interface. Bipolar Mode: 3 B2 RNEG7/ RBPV7 DO This pin acts as an active high NRZ receive signal output. A High signal on RNEG7 corresponds to receipt of a negative pulse on RTIP/RRING. This signal along with RPOS7 is valid on the falling edge of RCLK7. Unipolar Mode: In unipolar mode, this pin indicates a receive BiPolar Violation (BPV). It goes High on receipt of a bipolar violation at the receiver. This is a NRZ output, valid by default on the falling edge of the RCLK. The clock edge validating this signal can be changed from falling edge to rising edge by software. This description applies to ports 0 through 7. 4 12 D5 RCLK7 DO Receive Clock Output (Port. 7). This digital framer interface pin provides the recovered clock from the signal received at RTIP7 and RRING7. Under LOS conditions there is a transition from RCLK7 signal (derived from the recovered data) to MCLK signal at the RCLK7 output. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. QFP LXT3108 Pin Description (Continued) PBGA Symbol I/O Description Transmit Positive Data/Transmit Data Input (Port. 7. In bipolar mode this digital framer interface pin acts as the positive side of the bipolar data input pair, TPOS7 and TNEG7, which controls the signal transmitted to the line interface. In unipolar mode, TDATA7 acts as a single NRZ data input controlling the signal transmitted to the line interface. Bipolar Mode: TPOS7 is an active high NRZ input that operates together with TNEG7. TPOS7 starts the transmission of a positive pulse on TTIP7/TRING7, whereas TNEG7 starts the transmission of a negative pulse on TTIP7/TRING7. 5 C1 TPOS7/ TDATA7 DI TPOS7 TNEG7 Selection 0 0 Space 1 0 Positive Mark 0 1 Negative Mark 1 1 Space Unipolar Mode: TDATA7 acts as a single NRZ input controlling the signal transmitted to the line interface. 6 C2 TNEG7 DI Transmit Negative Data (Port 7). In bipolar mode this digital framer interface pin acts as the negative side of the bipolar data input pair, TPOS7 and TNEG7, which controls the signal transmitted to the line interface. Unipolar Mode: Tie TNEG7 to ground in unipolar mode. Transmit Clock Input (Port 7). During normal operation TCLK7 toggles at the line rate, which is 1.544 MHz for T1/J1 operation, and 2.048 MHz for E1 operation. TPOS7 and TNEG7, or TDATA7, are sampled on the falling edge of TCLK7. TCLK Clocked 7 D4 TCLK7 DI Operating Mode Normal operation L Driver outputs three stated, but powered on for redundancy. H Driver outputs three stated and powered down for reduced power draw. Note: The Transmit All Ones (TAOS) generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. 8 9 D3 D1 RPOS6/ RDATA6 RNEG6/ RBPV6 DO DO Receive Positive Data/Receive Data Output (Port 6). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS6 and RNEG6, recovered from the line interface. In unipolar mode, RDATA6 acts as a single NRZ output of the data recovered from the line interface. Receive Negative Data (Port 6). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS6 and RNEG6, recovered from the line interface. In Unipolar mode, it indicates receive BPV for port 6. 10 Datasheet D2 RCLK6 DO Receive Clock Output (Port 6). 13 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O Description 11 E4 TPOS6/ TDATA6 DI Transmit Positive Data/Transmit Data Input (Port 6). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS6 and TNEG6, which controls the signal transmitted to the line interface. In unipolar mode, TDATA6 acts as a single NRZ input data controlling the signal transmitted to the line interface. 12 E3 TNEG6 DI Transmit Negative Data (Port 6). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS6 and TNEG6, which controls the signal transmitted to the line interface. Tie TNEG6 to ground in unipolar mode. 13 E1 TCLK6 DI Transmit Clock Input (Port 6). 14 E2 RPOS5/ RDATA5 DO Receive Positive Data/Receive Data Output (Port 5). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS5 and RNEG5, recovered from the line interface. In unipolar mode, RDATA5 acts as a single NRZ output of the data recovered from the line interface. 15 F4 RNEG5/ RBPV5 DO Receive Negative Data (Port 5). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS5 and RNEG5, recovered from the line interface. In Unipolar Mode this pin indicates Receive BPV for port 5. 16 F1 RCLK5 DO Receive Clock Output (Port 5). 17 F3 TPOS5/ TDATA5 DI Transmit Positive Data/Transmit Data Input (Port 5). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS5 and TNEG5, which controls the signal transmitted to the line interface. In unipolar mode, TDATA5 acts as a single NRZ input data controlling the signal transmitted to the line interface. 18 F2 TNEG5 DI Transmit Negative Data (Port 5). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS5 and TNEG5, which controls the signal transmitted to the line interface. Tie TNEG5 to ground in unipolar mode. 19 G4 TCLK5 DI Transmit Clock Input (Port 5). 20 G1 RPOS4/ RDATA4 DO Receive Positive Data/Receive Data Output (Port 4). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS4 and RNEG4, recovered from the line interface. In unipolar mode, RDATA4 acts as a single NRZ output of the data recovered from the line interface. 21 G3 RNEG4/ RBPV4 DO Receive Negative Data (Port 4). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS4 and RNEG4, recovered from the line interface. In Unipolar Mode this pin indicates Receive BPV for port 4. 14 22 G2 RCLK4 DO Receive Clock Output (Port 4). 23 H4 TPOS4/ TDATA4 DI Transmit Positive Data/Transmit Data Input (Port 4). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS4 and TNEG4, which controls the signal transmitted to the line interface. In unipolar mode, TDATA4 acts as a single NRZ input data controlling the signal transmitted to the line interface. 24 H1 TNEG4 DI Transmit Negative Data (Port 4). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS4 and TNEG4, which controls the signal transmitted to the line interface. Tie TNEG4 to ground in unipolar mode. 25 H3 TCLK4 DI Transmit Clock Input (Port 4). 26 H2 GNDIO S Ground (I/O). 27 J1 VCCIO S Power (I/O). 28 J4 RPOS3/ RDATA3 DO Receive Positive Data/Receive Data Output (Port 3). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS3 and RNEG3, recovered from the line interface. In unipolar mode, RDATA3 acts as a single NRZ output of the data recovered from the line interface. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA 29 J3 Symbol RNEG3/ RBPV3 I/O DO Description Receive Negative Data (Port 3). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS3 and RNEG3, recovered from the line interface. In Unipolar Mode this output indicates Receive BPV for port 3. 30 J2 RCLK3 DO Receive Clock Output (Port 3). 31 K1 TPOS3/ TDATA3 DI Transmit Positive Data/Transmit Data Input (Port 3). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS3 and TNEG3, which controls the signal transmitted to the line interface. In unipolar mode, TDATA3 acts as a single NRZ input data controlling the signal transmitted to the line interface. 32 K4 TNEG3 DI Transmit Negative Data (Port 3). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS3 and TNEG3, which controls the signal transmitted to the line interface. Tie TNEG3 to ground in unipolar mode. 33 K3 TCLK3 DI Transmit Clock Input (Port 3). 34 L1 RPOS2/ RDATA2 DO Receive Positive Data/Receive Data Output (Port 2). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS2 and RNEG2, recovered from the line interface. In unipolar mode, RDATA2 acts as a single NRZ output of the data recovered from the line interface. 35 K2 RNEG2/ RBPV2 DO Receive Negative Data (Port 2). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS2 and RNEG2, recovered from the line interface. In Unipolar Mode this output indicates Receive BPV for port 2. 36 L4 RCLK2 DO Receive Clock Output (Port 2). 37 L3 TPOS2/ TDATA2 DI Transmit Positive Data/Transmit Data Input (Port 2). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS2 and TNEG2, which controls the signal transmitted to the line interface. In unipolar mode, TDATA2 acts as a single NRZ input data controlling the signal transmitted to the line interface. 38 M1 TNEG2 DI Transmit Negative Data (Port 2). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS2 and TNEG2, which controls the signal transmitted to the line interface. Tie TNEG2 to ground in unipolar mode. 39 L2 TCLK2 DI Transmit Clock Input (port 2). 40 M4 RPOS1/ RDATA1 DO Receive Positive Data/Receive Data Output (Port 1). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS1 and RNEG1, recovered from the line interface. In unipolar mode, RDATA1 acts as a single NRZ output of the data recovered from the line interface. 41 M3 RNEG1/ RBPV1 DO Receive Negative Data (Port 1). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS1 and RNEG1, recovered from the line interface. In Unipolar mode this output indicates Receive BPV for port 0. 42 N1 RCLK1 DO Receive Clock Output (Port 1). 43 M2 TPOS1/ TDATA1 DI Transmit Positive Data/Transmit Data Input (Port 1). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS1 and TNEG1, which controls the signal transmitted to the line interface. In unipolar mode, TDATA1 acts as a single NRZ input data controlling the signal transmitted to the line interface. 44 N3 TNEG1 DI Transmit Negative Data (Port 1). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS1 and TNEG1, which controls the signal transmitted to the line interface. Tie TNEG1 to ground in unipolar mode. 45 P1 TCLK1 DI Transmit Clock Input (Port 1). Datasheet 15 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O Description 46 N2 RPOS0/ RDATA0 DO Receive Positive Data/Receive Data Output (Port 0). In bipolar mode this pin acts as the positive side of the bipolar data output pair, RPOS0 and RNEG0, recovered from the line interface. In unipolar mode, RDATA0 acts as a single NRZ output of the data recovered from the line interface. RNEG0/ 47 N4 48 N5 RCLK0 DO Receive Clock Output (Port 0). 49 R1 TPOS0/ TDATA0 DI Transmit Positive Data/Transmit Data Input (Port 0). In bipolar mode this pin acts as the positive side of the bipolar data input pair, TPOS0 and TNEG0, which controls the signal transmitted to the line interface. In unipolar mode, TDATA0 acts as a single NRZ input data controlling the signal transmitted to the line interface. 50 P2 TNEG0 DI Transmit Negative Data (Port 0). In bipolar mode this pin acts as the negative side of the bipolar data input pair, TPOS0 and TNEG0, which controls the signal transmitted to the line interface. Tie TNEG0 to ground in unipolar mode. 51 P3 TCLK0 DI Transmit Clock Input (Port 0). 52 P4 GNDIO S Ground (I/O). 53 R2 VCCIO S Power (I/O). 54 T1 DVCC S Digital Power 3.3V. 55 L6 DVSS S Digital Ground. 56 T3 AVCC S Analog Power 3.3V. 57 R3 RRING0 AI Receive Ring Input (Port 0). This pin is one of the pair of inputs, RRING0/RTIP0, to the differential line receiver at the line interface for the port. Data and clock are recovered and output at the digital framer interface output pins. 58 T4 RTIP0 AI Receive Tip Input (Port 0). This pin is one of the pair of inputs, RRING0/RTIP0, to the differential line receiver at the line interface for the port. Data and clock are recovered and output at the digital framer interface output pins. 59 P5 AVSS S Analog Ground. RBPV0 DO Receive Negative Data (Port 0). In bipolar mode this pin acts as the negative side of the bipolar data output pair, RPOS0 and RNEG0, recovered from the line interface. In Unipolar Mode this output indicates Receive BPV for port 0. 16 60 P6 TXVSS S Transmit Ground. Ground pin for transmit logic. 61 P7 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 62 N6 TVSS S Transmit Driver Ground. Ground pin for the output driver. 63 R5 TRING0 AO Transmit Ring Output (Port 0). This is one of the pair of differential line driver outputs to the line interface pins, TTIP0/TRING0. TTIP0/TRING0 will be in a high impedance state if the TCLK pin is static or if the OE pin is Low. TTIP0/TRING0 can be in a the high impedance state on a port-by-port basis by writing a ‘1’ to the TXPD bit in “Port Master Control Page Register, 01h” on page 57, or the OES bit in “Transmit Control Page Register, 03h” on page 58. Please refer to “Transmit Idle Operation and Three Stating Drivers” on page 35 for details. 64 T5 TTIP0 AO Transmit Tip Output (Port 0). This is one of the pair of differential line driver outputs to the line interface pins, TTIP0/TRING0. 65 N7 TVSS S Transmit Driver Ground. Ground pin for the output driver. 66 T8 DVSS S Digital Ground. 67 T6 DVCC S Digital Power 3.3V 68 N9 TVSS S Transmit Driver Ground. Ground pin for the output driver. 69 R6 TTIP1 AO Transmit Tip Output (Port 1). This is one of the pair of differential line driver outputs to the line interface pins, TTIP1/TRING1. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O Description 70 T7 TRING1 AO 71 P10 TVSS S Transmit Driver Ground. Ground pin for the output driver. 72 R4 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 73 P11 TXVSS S Transmit Ground. Ground pin for transmit logic. 74 G13 AVSS S Analog Ground 75 R7 RTIP1 AI Receive Tip Input (Port 1). This pin is one of the pair of inputs, RRING1/RTIP1, to the differential line receiver at the line interface for the port. 76 P8 RRING1 AI Receive Ring Input (port 1). This pin is one of the pair of inputs, RRING1/RTIP1, to the differential line receiver at the line interface for the port. Transmit Ring Output (Port 1). This is one of the pair of differential line driver outputs to the line interface pins, TTIP1/TRING1. 77 P9 AVCC S Analog Power 3.3V. 78 N10 DVSS S Digital Ground. 79 R11 DVCC S Digital Power 3.3V. 80 R8 AVCC S Analog Power 3.3V. 81 T9 RRING2 AI Receive Ring Input (Port 2). This pin is one of the pair of inputs, RRING2/RTIP2, to the differential line receiver at the line interface for the port. 82 R9 RTIP2 AI Receive Tip Input (port 2). This pin is one of the pair of inputs, RRING2/RTIP2, to the differential line receiver at the line interface for the port. 83 L5 AVSS S Analog Ground. 84 R12 TXVSS S Transmit Ground. Ground pin for transmit logic. 85 P12 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 86 P13 TVSS S Transmit Driver Ground. Ground pin for the output driver. 87 R10 TRING2 AO Transmit Ring Output (Port 2). This is one of the pair of differential line driver outputs to the line interface pins, TTIP2/TRING2. 88 T11 TTIP2 AO Transmit Tip Output (Port 2). This is one of the pair of differential line driver outputs to the line interface pins, TTIP2/TRING2. 89 T15 TVSS S Transmit Driver Ground. Ground pin for the output driver. 90 R14 DVCC S Digital Power 3.3V. 91 M11 DVSS S Digital Ground. 92 M12 TVSS S Transmit Driver Ground. Ground pin for the output driver. 93 T12 TTIP3 AO Transmit Tip Output (Port 3). This is one of the pair of differential line driver outputs to the line interface pins, TTIP3/TRING3. 94 T13 TRING3 AO Transmit Ring Output (Port 3). This is one of the pair of differential line driver outputs to the line interface pins, TTIP3/TRING3. 95 M10 TVSS S Transmit Driver Ground. Ground pin for the output driver. 96 T10 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 97 M7 TXVSS S Transmit Ground. Ground pin for transmit logic. 98 M8 AVSS S Analog Ground. 99 R13 RTIP3 AI Receive Tip Input (Port 3). This pin is one of the pair of inputs, RRING3/RTIP3, to the differential line receiver at the line interface for the port. 100 T14 RRING3 AI Receive Ring Input (Port 3). This pin is one of the pair of inputs, RRING3/RTIP3, to the differential line receiver at the line interface for the port. Datasheet 17 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O Description 101 N11 AVCC S Analog Power 3.3V. 102 M6 DVSS S Digital Ground. 103 N8 DVCC S Digital Power 3.3V. 104 M5 GNDIO S Ground (I/O). 105 T16 VCCIO S Power (I/O). 106 R16 JRST DI JTAG Controller Reset Input. Input is used to reset the JTAG controller. This pin should be tied to ground through a 1K resistor. 107 R15 TMS DI JTAG Test Mode Select Input. Used to control the test logic state machine. Sampled on rising edge of TCK. TMS is pulled up internally and may be left disconnected. 108 P16 TDO DO JTAG Data Output. During JTAG operation, this pin is Test Data Output for JTAG. Used for reading all serial configuration and test data from internal test logic. It is updated on falling edge of TCK. 109 P15 TDI DI JTAG Data Input. This pin is Test Data input for JTAG. Used for loading serial instructions and data into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may be left disconnected. 110 N16 TCK DI JTAG Clock Input. This pin is clock input for JTAG. Connect to GND when not used. 111 P14 RSTB DI Reset. This pin is the reset pin for the LXT3108 octal LIU. One microsecond after RSTB goes Low, the internal registers will be restored to their default values. 112 N15 LOS0 DO Loss of Signal Output (Port 0). When the LOS0 output is High, it indicates a loss of signal at the port’s line interface receiver. LOS goes active after the incoming signal has insufficient transitions for a specified time interval, which is determined by the page and global register settings. The LOS condition is cleared and the output pin returns to Low when the incoming signal has a sufficient number of transitions in a specified time interval, as determined by the register settings. 113 N14 LOS1 DO Loss of Signal Output (Port 1). 114 M16 LOS2 DO Loss of Signal Output (Port 2). 115 N13 LOS3 DO Loss of Signal Output (Port 3). 116 M15 LOS4 DO Loss of Signal Output (Port 4). 117 L16 LOS5 DO Loss of Signal Output (Port 5). 118 M14 LOS6 DO Loss of Signal Output (Port 6). 119 N12 LOS7 DO Loss of Signal Output (port 7). 120 L15 TYPE2 DI Microprocessor Type Select Inputs. These pins control which microprocessor interface is active: Type2 121 122 18 K16 L14 TYPE1 CS DI DI Type1 Microprocessor 0 0 MPC860, M68360 0 1 i960, i486 1 0 M68302 1 1 Reserved Chip Select. This active Low input initiates each access to the parallel microprocessor interface. For each read or write operation, CS must transition from High to Low, and remain Low. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. QFP LXT3108 Pin Description (Continued) PBGA Symbol I/O Description Master Clock Input. MCLK is an independent, free-running reference clock. After initialization the frequency can be set to 8, 4, 2 or 1x of the T1/E1/J1 frequency. Refer to CLAD Configuration Register (Address 11h) for MCLK frequency selection. This reference clock is used to generate several internal reference signals: 123 M13 MCLK DI • Timing reference for the integrated clock recovery unit. • Timing reference for the integrated digital jitter attenuator. • Generation of RCLK signal during a loss of signal condition. • Reference clock during a blue alarm transmit all ones (TAOS) condition. • Reference timing for the parallel processor wait state generation logic. 124 K15 GND Ground. 125 J16 GND Ground. 126 K14 VMOAT AI Substrate Ground. 127 J14 RBIAS AI Resistor Bias Input. A 30.1 K Ω, 1% ±100 PPM/°C, resistor must be connected from this pin to analog ground. The Panasonic ERJ-8ENF3012V resistor is recommended. 128 K13 QVSS AI Ground for analog bias circuit. 129 L13 QVCC AI Power for analog bias circuit. 3.3V DI Output Driver Enable Input. If this pin is asserted low every port’s analog driver/ transmitter output immediately enters a high impedance state to support redundancy applications without external mechanical relays. All other internal circuitry stays active. TTIP and TRING for each port can also be placed in the high impedance state individually by writing a ‘1’ to the TXPD bit in “Port Master Control Page Register, 01h” on page 57 or the OES bit in the “Transmit Control Page Register, 03h” on page 58. Please refer to “Transmit Idle Operation and Three Stating Drivers” on page 35 for details. 130 H16 OE 131 L12 GNDIO S Ground (I/O). 132 H15 VCCIO S Power (I/O). 133 H14 DB0 DI/O 134 G16 DB1 DI/O 135 J13 DB2 DI/O 136 G14 DB3 DI/O 137 J15 GNDIO S Ground (I/O). 138 F16 VCCIO S Power (I/O). 139 H13 DB4 DI/O 140 F14 DB5 DI/O 141 F15 DB6 DI/O 142 E16 DB7 DI/O 143 G15 GNDIO S Ground (I/O). 144 E14 VCCIO S Power (I/O). Datasheet Data Bus Input/Output. When a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data bus. When a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs A0 -A7. Data Bus Input/Output. When a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data bus. When a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs A0 -A7. 19 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. QFP LXT3108 Pin Description (Continued) PBGA Symbol I/O 145 E15 AD0 DI 146 D16 AD1 DI 147 F13 AD2 DI 148 D15 AD3 DI 149 C16 AD4 DI 150 D14 AD5 DI 151 E13 AD6 DI 152 C15 AD7 DI 153 B16 RW 154 D13 DS 155 D12 RDY DI DI DI DI Description Address Bus Input. In non-multiplexed mode these inputs function as address input pins for the microprocessor bus. This pin has one of two functions depending on the microprocessor interface selected by the TYPE1 and TYPE2 inputs. • Read/Write Input (Motorola Mode). • Write Enable Active Low Input (Intel mode). This pin has one of two functions depending on the microprocessor interface selected by the TYPE1 and TYPE2 inputs. • Data Strobe Input (Motorola Mode). • Read Enable Active Low Input (Intel mode) DO This pin has one of two functions depending on the microprocessor interface selected by the TYPE1 and TYPE2 inputs. • Data Transfer Acknowledge Output. (Motorola Mode). • Ready Output (Intel mode). DO Motorola Mode: A Low signal on RDY during a read operation indicates that the information on the data bus is valid. A Low signal during a write operation acknowledges that a data transfer into the addressed register has been accepted (acknowledge signal). This pin has one of two functions depending on the microprocessor interface selected by the TYPE1 and TYPE2 inputs. 156 C14 MPI_CLK/ ALE DI Address Latch Enable Input (Intel Mode). • The address on the multiplexed address/data bus is clocked into the device with the falling edge of ALE. Microprocessor Clock (Intel i486 Mode). • This pin is used to input the microprocessor clock in the synchronous i486 mode. 20 Interrupt. This is an active Low output. If the corresponding interrupt enable bit is enabled, INTR goes Low to flag the microprocessor when the LXT3108 changes state (see details in the interrupt handling section). The microprocessor interrupt input should be set to level triggering. 157 B15 INTR DO 158 A16 DVCC S Digital Power 3.3V. 159 E12 DVSS S Digital Ground. 160 A15 AVCC S Analog Power 3.3V. 161 A14 RRING4 AI Receive Ring Input (Port 4). This pin is one of the pair of inputs, RRING4/RTIP4, to the differential line receiver at the line interface for the port. 162 B14 RTIP4 AI Receive Tip Input (Port 4). This pin is one of the pair of inputs, RRING4/RTIP4, to the differential line receiver at the line interface for the port. 163 C13 AVSS S Analog Ground. 164 D11 TXVSS S Transmit Ground. Ground pin for transmit logic. 165 A13 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 166 B13 TVSS S Transmit Driver Ground. Ground pin for the output driver. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O Description 167 A12 TRING4 AO Transmit Ring Output (Port 4). This is one of the pair of differential line driver outputs to the line interface pins, TTIP4/TRING4. 168 A11 TTIP4 AO Transmit Tip Output (Port 4). This is one of the pair of differential line driver outputs to the line interface pins, TTIP4/TRING4. 169 B12 TVSS S Transmit Driver Ground. Ground pin for the output driver. 170 C11 DVSS S Digital Ground. 171 C12 DVCC S Digital Power 3.3V. 172 D10 TVSS S Transmit Driver Ground. Ground pin for the output driver. 173 A10 TTIP5 AO Transmit Tip Output (Port 5). This is one of the pair of differential line driver outputs to the line interface pins, TTIP5/TRING5. 174 B11 TRING5 AO Transmit Ring Output (Port 5). This is one of the pair of differential line driver outputs to the line interface pins, TTIP5/TRING5. 175 E10 TVSS S Transmit Driver Ground. Ground pin for the output driver. 176 A7 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 177 B10 TXVSS S Transmit Ground. Ground pin for transmit logic. 178 C10 AVSS S Analog Ground. 179 C8 RTIP5 AI Receive Tip Input (Port 5). This pin is one of the pair of inputs, RRING5/RTIP5, to the differential line receiver at the line interface for the port. 180 A9 RRING5 AI Receive Ring Input (Port 5). This pin is one of the pair of inputs, RRING5/RTIP5, to the differential line receiver at the line interface for the port. 181 A8 AVCC S Analog Power 3.3V. 182 B6 DVCC S Digital Power 3.3V. 183 D6 DVSS S Digital Ground. 184 B9 AVCC S Analog Power 3.3V. 185 C7 RRING6 AI Receive Ring Input (Port 6). This pin is one of the pair of inputs, RRING6/RTIP6, to the differential line receiver at the line interface for the port. 186 B8 RTIP6 AI Receive Tip Input (port 6). This pin is one of the pair of inputs, RRING6/RTIP6, to the differential line receiver at the line interface for the port. 187 D7 AVSS S Analog Ground. 188 E6 TXVSS S Transmit Ground. Ground pin for transmit logic. 189 C9 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 190 B3 TVSS S Transmit Driver Ground. Ground pin for the output driver. 191 B7 TRING6 AO Transmit Ring Output (Port 6). This is one of the pair of differential line driver outputs to the line interface pins, TTIP6/TRING6. 192 A6 TTIP6 AO Transmit Tip Output (Port 6). This is one of the pair of differential line driver outputs to the line interface pins, TTIP6/TRING6. 193 C4 TVSS S Transmit Driver Ground. Ground pin for the output driver. 194 A2 DVCC S Digital Power 3.3V. 195 C5 DVSS S Digital Ground. 196 C6 TVSS S Transmit Driver Ground. Ground pin for the output driver. 197 A5 TTIP7 AO Datasheet Transmit Tip Output (Port 7). This is one of the pair of differential line driver outputs to the line interface pins, TTIP7/TRING7. 21 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 1. LXT3108 Pin Description (Continued) QFP PBGA Symbol I/O 198 B5 TRING7 AO 199 E5 TVSS S Transmit Driver Ground. Ground pin for the output driver. 200 A4 TXVCC S Transmit Power Supply. Power supply pin for the transmit logic, 3.3V. 201 E8 TXVSS S Transmit Ground. Ground pin for transmit logic. 202 E7 AVSS S Analog Ground. 203 B4 RTIP7 AI Receive Tip Input (Port 7). This pin is one of the pair of inputs, RRING7/RTIP7, to the differential line receiver at the line interface for the port. 204 A3 RRING7 AI Receive Ring Input (Port 7). This pin is one of the pair of inputs, RRING7/RTIP7, to the differential line receiver at the line interface for the port. 205 C3 AVCC S Analog Power 3.3V. 206 E9 DVSS S Digital Ground. 207 D9 DVCC S Digital Power 3.3V. 208 E11 GNDIO S Ground (I/O). T2 DVCC S Digital Power 3.3V. M9 Transmit Ring Output (Port 7). This is one of the pair of differential line driver outputs to the line interface pins, TTIP7/TRING7. This pin must be left floating. D8, F5, F6, F7, F8, F9, F10, F11, F12, G5, G6, G7, G8, G9, G10, G11, G12, H5, H6, H7, H8, H9, H10, H11, H12, J5, J6, J7, J8, J9, J10, J11, J12, K5, K6, K7, K8, K9, K10, K11, K12, L7, L8, L9, L10, L11, M8 3.0 Description VSS S Ground. T1/E1 Nomenclature The nomenclature in this document follows telecommunication industry standard conventions, i.e., bit, channel, and frame numbering increase sequentially with time. In the case of bit ordering, unless otherwise stated, the Most Significant Bit (MSB) is transmitted first and is designated Bit 1. 22 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 4.0 LXT3108 Nomenclature The LXT3108 is an octal device, meaning that it supports up to eight T1/E1/J1 ports. The ports are numbered sequentially, beginning with zero and ending with seven. A port is defined as the standard 4-wire receive/transmit pair T1/E1/J1 interface. Port and channel are used interchangeably in this document and all related documents. 5.0 Functional Description The LXT3108 is a port-by-port programmable, fully integrated eight-port LIU with jitter attenuator as well as network control and maintenance functions. Each LXT3108 port is suitable for mixed LH or SH, T1/E1/J1 telecommunications applications allowing full-duplex transmission of digital data over existing cable installations. Under microprocessor control and with a single MCLK source, each port can individually operate: — at either T1/J1 or E1 line rates — at separate line termination impedance settings — with default or programmable transmit signal — with preset or customized receiver sensitivity — with the jitter attenuator in either the transmit or receive path, or disabled — with or without zero suppression line coding Figure 4. LXT3108 Port Block Transmitter TCLK TPOS TNEG TTIP TRING JA* Network Control and Maintenance RCLK RPOS RNEG RTIP RRING Receiver *Jitter Attenuator in either transmitter or receiver path. Can be disabled. Datasheet 23 LXT3108 — Octal T1/E1/J1 LH/SH LIU An eight-bit wide data bus conveys commands from a microprocessor to each port individually or all ports at the same time by a two-step process. First, writing the port number to the global register described in Table 18, “Port Page Select Register, CPS, 00h” on page 55 chooses the port. The next read or write operation can then reach one of the 32 Port Page Registers (PPRs) adjusting preset port parameters. Besides the PPRs, the designer can also access 48 ATWG registers described in Table 43, “Transmit Coefficient Page Register Range, 40h-6Fh” on page 64. The LXT3108 is fully T1/E1/J1 selectable without the need to change any external components for twisted pair applications, allowing the development of a single board design to support T1 and E1 designs. The J1 line rate and transformer configuration are the same for T1 and J1 cable. T1 will refer to both T1 and J1 operation throughout this document. The line interface to the cables is through standard T1 and E1 telecommunications transformers and resistors. Each LIU front-end interfaces with two twisted pairs: one pair for transmit, and one pair for receive. These two pairs comprise a digital data loop for full duplex transmission. Figure 5. LXT3108 Port Circuit VCC 1 CT:1 TTIP Tx LINE LXT3108 Port 1ΚΩ 100 pF 1 TRING 1 CT:1 RTIP 121 Ω Rx LINE RRING NOTE: 1) Actual value may vary depending on design. Framed or unframed data clocked by TCLK to TPOS/TNEG or TDATA inputs activates the waveshaping and line driver circuits. The port’s transmitter will drive T1 or E1 lines from TTIP and TRING pins out to standard telecommunications T1 or E1 transformers. The line driver can handle both LH and SH lines for T1/E1/J1. Preset and programmable pulse shaping suits both LH and SH environments. Each port provides eight built-in equalization settings for SH applications and six line build outs for LH applications. In addition, the Intel PTM software allows the transmitter performance to be tuned for a wide variety of line conditions or special applications. The PTM software provides eight bits of amplitude resolution and either 15 (T1) or 16 (E1) phases of time resolution for up to three Unit Intervals (UI). The combination of proven preset wave-shaping settings and the PTM software means the designer has increased flexibility in meeting design challenges of copper interfaces. 24 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU A simplified transmitter circuit configuration offers: — Port-by-port programmable line impedance matching. — Reduced port component count. — Current limiting for short-circuits. By programming the internal transmitter termination, matching the line impedance requires no component changes for twisted pair and coaxial cable applications, as shown in Figure 6. Figure 6. Transmitter Circuit for Twisted Pair and Coaxial Cable Tx LINE 75 Ω 1 VCC TTIP TRING 100 pf 1ΚΩ 100/120 Ω 1 CT:1:0.8 NOTE: 1) Actual value may vary depending on design. Trimming each port’s transmitter circuit components to a single transformer and a capacitor increases design flexibility. The transmitter’s current mode driver is self-limiting to provide built in short circuit protection. Efficient and flexible line circuit configuration increases designer options and maintains line protection. A single mandatory clock reference, MCLK, shared between all eight clock recovery circuits, enables each receiver in the LXT3108 to recover the clock and data signals from the line interface. When selected, after smoothing the recovered signals through the jitter attenuator, RCLK clocks out RDATA or RPOS/RNEG at the port’s digital framer interface. Each port’s receiver dynamic range is from 0 to -43 dB for E1 operation and 0 to -36 dB for T1 operation. This translates to cable reach of at least 2.5 kilometers on 0.63 mm cables (E1) and at least 6000 feet on 22 AWG cables (T1). The analog AMI waveform from the E1, T1, or J1 line is transformer coupled into the port’s RTIP and RRING pins through the LXT3108’s internal receive termination. This programmable input termination can select between 100, 110, or 120 Ω applications, eliminating the need to change external components for twisted-pair cable. The designer has the option of selecting by software the internal receive line termination, or bypassing this option with external terminating resistors. See Figure 6 for operating 75 Ω cable. Datasheet 25 LXT3108 — Octal T1/E1/J1 LH/SH LIU 6.0 Software Support The LXT3108 comes with a complete set of software support. The various software modules allow you to: • Configure the device through a Graphical User Interface (GUI). The LXT3108 GUI software allows you to configure the LXT3108 without having to worry about which bits to set in a particular register. Configuration of the LXT3108 can be accomplished by a series of mouse clicks within the GUI. Configurations can be saved as a series of LXT3108 API messages, which can be used by client applications. Additionally, the LXT3108 GUI allows you to monitor the performance of the device as well as poll the interrupts. • Develop customized applications using the LXT3108 Application Programming Interface (API). The LXT3108 API is an open source, ANSI C standard library that allows you to develop custom applications for communicating with the device. Programming with the API improves development time by relieving the programmer of having to know the register specifics of the LXT3108. The LXT3108 API complies with the Intel® IXA architecture for compatibility with other Intel communication building blocks. • Fine-tune the pulse shape of the device using the Intel® Pulse Template Matching (Intel® PTM) software. The Intel PTM software provides a graphical view of the transmitting pulse shape (T1, J1 or E1) that the LXT3108 generates. PTM allows you to adjust the pulse shape to fit its respective template, without having to manually manipulate register settings. The PTM software, through the use of graphical controls, automatically adjusts the register settings of the LXT3108 for you. This simplifies the process of fine-tuning the pulse shape, which leads to faster development time. 7.0 LIU Functional Description Each port consists of a transmitter and a receiver with a jitter attenuator switched between each path. Access to the host device is via a microprocessor parallel interface configured in either Intel or Motorola mode. JTAG built-in test chains enable verification on-board of digital pins and functions. 26 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 7. T1/E1/J1 LIU Block Diagram TCLK Transmit PLL TPOS TNEG Transmit DSP/Control TTIP TRING Transmit DAC Analog Loopback Switchable DJA Remote Loopback RPOS RNEG RCLK MCLK ENABLE LOS Timing/Data Recovery Line Equalizer ADC Analog Noise Filter AGC Internal Line Termination RTIP RRING Clock Generator Activation/ Control Logic LOS Each of the eight transmitters consists of a current mode output driver, a second-order charge pump Phase Lock Loop (PLL), a simple digital Finite Infinite Response (FIR) filter and a switchedcurrent Digital to Analog Converter (DAC). The FIR filter, in combination with the transmitter DAC, provides shaped pulses fitting the pulse shape to the various T1 and E1 pulse templates. A ROM is used to store coefficients and settings for the digital transmit waveform generator. Each of the eight receivers’ Analog Front Ends (AFE) consists of an Automatic Gain Control (AGC) amplifier, anti-aliasing filter, and Analog to Digital Converter (ADC). The digital section consists of a digital noise filter, a root-f equalizer, a decision feedback equalizer, timing recovery, and adaptation control logic, as shown in Figure 7 on page 27. A ROM is used to store coefficients and settings for the receiver digital filters. The programmer controls overall device operation of the LXT3108 through global registers. Each individual LIU is separately controlled by a set of PPRs. There are eight sets of PPRs, one for each port. It is also possible to write to all ports at the same time in the case where all ports need to be set up with the same configuration. The LXT3108 jitter attenuator enhances compatibility with the existing network by complying with jitter control standards The jitter performance of the LXT3108 conforms to the stringent specifications of AT&T Pub. 62411 and ITU TBR12/13. The jitter attenuator is completely digital and does not require an external crystal. The LXT3108 has the capability to insert a Jitter Attenuator (JA) in either the transmit or receive data path individually for each port. Datasheet 27 LXT3108 — Octal T1/E1/J1 LH/SH LIU 8.0 Initialization During power up, the Power-On-Reset (POR) circuit initiates a reset sequence after the power supply reaches threshold of approximately 60% of VCC. On crossing this threshold, the device begins a 32 msec reset cycle to calibrate internal phase lock loops. During power-up, an internal reset places all registers to their default values and resets the status and state machines for LOS and AIS. MCLK is mandatory for chip operation. 8.1 CLAD Initialization It is required to initialize the CLAD register (Addr : 0x11) after power on reset, based on the frequency of the MCLK input signal. The following table can be used for programming the CLAD register (refer to Table 21, “CLAD Configuration Register1, 11h3” on page 56). Table 2. CLAD Initialization Options MCLK Input1 Value to be written to CLAD (Addr : 0x11) after power on reset. 8x E1 clock 80 4x E1 clock 88 2x E1 clock 84 1x E1 clock 8c 8x T1 clock 90 4x T1 clock 98 2x T1 clock 94 1x T1 clock 9c 1. E1 clock is 2.048 MHz and T1 clock is 1.544 MHz. 8.2 Reset Operation The LXT3108 can be reset in two ways: 1) Writing to the reset bit as shown in the “Port Page Select Register, CPS, 00h” on page 55. this soft reset initiates 32 msec reset cycle. The user should not access the internal registers during the reset cycle (register values are undefined). The reset bit does not initialize the “CLAD Configuration Register1, 11h.” 2) Asserting the reset pin RSTB low. The reset pulse width must be a minimum of 1 msec. It is recommended to wait for another 32 msec after the reset pulse is de-asserted before performing any read/write access to the port registers. The operation sets all LXT3108 registers to their default values, including the “CLAD Configuration Register1, 11h.” 8.3 5V Tolerant I/O Pins All digital input pins will tolerate 5.0 volts and are compatible with TTL logic. Please note that it is recommended to keep digital input pins less than 2 volts above the analog and digital supplies. The 5.0 V-tolerance of the LXT3108 is only applicable when the 3.3V (nominal) supplies are present. 28 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Note: External devices such as pull-up resistors, TTL logic, microprocessors, and system-bus peripherals are potential sources of 5V signals to the digital pins. Power-cycling and power-supply failure can potentially cause situations where the LXT3108 is powered down, while external 5V devices are powered up. If the power supply is not guaranteed to prevent this situation, a diode network can be used as shown in Figure 8. The diodes must be capable of handling the entire load capacity of either the 3.3V or 5V supply, whichever is greater. Figure 8. Diode Protection Network When Inputs Power Up Before Supplies 5V Supply 3.3 V Supply If the 5V supply fails, it be will held up to around 2.6 volts by the 3.3V supply. If the 3.3V supply fails, it will be held up to around 2.9 volts by the 5V supply. Each of these conditions is safe for the 5V tolerant pins. 8.4 Power Supply Requirements This section identifies recommended practice for layout and decoupling of power and ground planes. Long-term reliability of this device might be compromised if these guidelines are not followed. 8.4.1 Ground Plane All ground pins should be connected to a solid ground plane with the shortest possible path to minimize inductive effects. All pins with names containing GND, VSS, or SUB are ground pins. The VMOAT pin should also be connected to the ground plane. 8.4.2 Analog Power Supply The analog supply pins listed below require a 3.3V (nominal) supply, which should be filtered separately from the digital supply. — TXVCC — TVCC — AVCC — QVCC The recommended method is to connect all of the analog pins to a wide PCB trace, and connect one end of the PCB trace to the power plane. Bypass capacitors from the ground plane to the analog supply trace should be placed as close as possible to the following pins: — A 0.082 µF capacitor between each TXVCC pin and ground. — A 0.082 µF capacitor between each AVCC pin and ground. — A 0.082 µF capacitor between each DVCC pin and ground. Datasheet 29 LXT3108 — Octal T1/E1/J1 LH/SH LIU It is recommended that analog and digital power comes from the same power supply. To prevent excessive current through the device, due to one of the supplies failing or sequential power-cycling, it is suggested that the supplies be connected back to the same point. 8.4.3 Digital Power Supply Digital power supply pins, I/O power, and DVCC should be connected to a solid power plane with the shortest possible path. Four 0.01 µF bypass capacitors, one per side, should be placed as close as possible to the LXT3108 to filter the ground and power planes of the circuit board. In addition, the circuit board should contain 10 µF tantalum and 0.01 µF ceramic capacitors where power is supplied to the board. As with the analog power supply, it is recommended that analog and digital power come from the same power supply. To prevent excessive current through the device, due to one of the supplies failing or sequential power-cycling, it is suggested that the supplies be connected back to the same point. 9.0 Transmitter Each of the eight ports’ transmitters offers several features when interfacing with the framer device’s port transmitter control signals TCLK and TDATA or TPOS/TNEG. With TCLK clocking at the line rate and TDATA or TPOS/TNEG carrying digital traffic, the line driver will output a T1/ E1/J1 signal through a center tapped 1:1 transformer to the transmit cable pair. The eight low power transmitters of the LXT3108 are identical. Along with fourteen preprogrammed pulse shapes shown in Table 25, “Transmit Control Page Register, 03h” on page 58, the designer may choose the PTM software to tailor pulse shapes to the application. The PTM implements 48 8-bit registers described in Table 43, “Transmit Coefficient Page Register Range, 40h-6Fh” on page 64 that customizes the AMI transmit waveform. The user must assert bit zero, ATWG_EN, of TXCON register, 0x03 page 60, to enable this feature. The analog current driver uses programmable internal resistive feedback to synthesize an output impedance of either 100, 110 or 120 Ω for twisted-pair applications. The impedance is programmable through port page register in Table 27, “Termination Control Page Register, 05h” on page 59. When TCLK is not supplied, the transmitter remains powered down and the TTIP/TRING outputs are held in a high impedance state. All eight transmitters can be simultaneously three stated by setting the OE pin low. Also, the programmer can set the port’s output enable control bit to individually three state port transmitters as shown in “Transmit Control Page Register, 03h” on page 58. Please refer to Section 9.2.1, “Transmit Idle Operation and Three Stating Drivers” on page 35 for details. Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O is selected by setting the appropriate bits as described in Table 38, “Line Coding Control One Page Register, 1Ch” on page 62. The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer to the Test Specifications Section, Table 54, “Master and Transmit Clock Timing Characteristics” on page 72, for MCLK and TCLK timing characteristics. 30 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 9. 50% AMI Encoding TTIP Bit Cell 1 1 0 TRING 9.1 Transmit Line Interface Each of the eight transmitters has pre-programmed and preset pulse shapes suited for driving T1 and E1 twisted-pair cables in LH or SH applications. The signal from TTIP and TRING of each port is coupled to a 1:1 center-tapped transformer as shown in Figure 10. Figure 10. Typical Transmitter Interface Connections VCC 1 CT:1 TTIP Tx LINE 1 100 pF 1ΚΩ TRING 1 Actual value may vary depending on design. The 1:1 center-tapped transformer is readily available in many packages as specified below. Table 3. Transformer Specifications for the LXT3108 Tx/Rx Frequency MHz Tx Rx Turns Ratio Primary Inductance µH (minimum) Leakage Inductance µH (max) Interwinding Capacitance pF (max) DCR Ω (maximum) Dielectric 1 Breakdown V (minimum) 1.544/2.048 1 CT:1 600 0.80 60 0.70 pri 1.20 sec 1500 VRMS2 1.544/2.048 1:1 600 1.10 60 1.10 pri 1.10 sec 1500 VRMS2 1. Some ETSI applications may require a 2.3 kV dielectric breakdown voltage. 2. Some applications require transformers with center tap on the line side of the transformer (LH applications with DC current in the E1/T1 loop). Datasheet 31 LXT3108 — Octal T1/E1/J1 LH/SH LIU The programmer can control from the Port Page Register Bank: — Matching line impedance of the transmitter in “Termination Control Page Register, 05h” on page 59. — LH or SH pulse shape “Transmit Control Page Register, 03h” on page 58. — T1 or E1 port line clock rate “Port Master Control Page Register, 01h” on page 57. 9.1.1 Transmit Impedance Termination The LXT3108’s LIU transmitter will synthesize its output impedance to match either a 100 Ω, a 110 Ω, or a 120 Ω line as set by the TXTERM bits in “Termination Control Page Register, 05h” on page 59. For 75 Ω E1 coax applications, set the termination to 120 Ω and use 1 CT: 0.8 transformer. Refer to Figure 6. Preset pulse shaping controls the transmit pulse equalization to determine the transmitted pulse shape as shown in Table 25, “Transmit Control Page Register, 03h” on page 58. Table 4 provides more detail about the settings. In order for the port to accurately produce the desired pulse, software must: • Set T1 or E1 line clock rate in “Port Master Control Page Register, 01h”. • Set transmit line termination in “Termination Control Page Register, 05h”. • Load preset pulse shape setting in “Transmit Control Page Register, 03h”. Table 4. Preset Pulse Shaping Settings and Conditions T1/E1/J1 TCLK Frequency, MHz Register Bits 3-0 hex Cable Range in Feet1,2 or Line Build Out, LBO Cable Impedance, Ω Cable Attenuation, dB DSX1 1.544 00 • 0 to 133 100 0 to 0.6 DSX1 1.544 01 • 133 to 266 100 0.6 to 1.2 DSX1 1.544 02 • 266 to 399 100 1.2 to 1.8 DSX1 1.544 03 • 399 to 533 100 1.8 to 2.4 DSX1 1.544 04 • 533 to 655 100 2.4 to 3.0 DS1 1.544 05 • 0dB LBO 100 0 to 36 DS1 1.544 06 • -7.5dB LBO 100 0 to 28.5 DS1 1.544 07 • -15dB LBO 100 0 to 21 DS1 1.544 08 • -22.5dB LBO 100 0 to 13.5 E1 2.048 09 • 0 to 655 75 0 to 3.0 E1 2.048 0A • 0 to 655 120 0 to 3.0 E1 2.048 0B • up to 2.5 km 75 0 to 43 E1 2.048 0C • up to 2.5 km 120 0 to 43 J1 1.544 0D • 0 - 655 ft. 110 0 to 3.0 . 32 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 9.1.2 Transmit Return Loss Performance The LXT3108 transmitter will meet the applicable standard for transmit return loss, but there are several requirements. Because transmit return loss depends on the match between transmitter circuit output impedance and the characteristic cable impedance, ITU limits the reflections due to mismatch by specifying minimum transmit return loss. ANSI currently does not specify this parameter. In order to compare T1 performance to E1 performance, the ITU standard is adapted to show a similar T1 minimum return loss. This is a benchmark that might be suitable for some T1 applications. By appropriate software control of the internal transmit impedance in “Termination Control Page Register, 05h”, the transmit return loss will be maximized. There are three standards that can be checked for minimum transmit return loss. For E1 line rate, ITU G.703 recommends ETSI 300166. For T1 line rate, 0 dB is the de facto standard; however, ETSI 300166 can be adapted to 1.544 MHz, as shown in Table 5. Table 5. Transmit Return Loss Specifications for Frequency Range and Magnitude Transmit Return Loss T1/E1 E1 T1 Frequency Band Actual Performance ETS 300 166 51-102 KHz 16 6 dB 102-2048 KHz 12 8 dB 2048 - 3072 KHz 11 8 dB 39-77 KHz TBD Notes ITU G.703 specification 6 dB 77-1544 KHz 8 dB 1544 - 2316 KHz 8 dB Adapted as a benchmark Figure 11. T1, T1.102 Mask Templates 1.40 1.20 1.00 Normalized Amplitude 0.80 0.60 0.40 0.20 -1.00 -0.50 0.00 0.00 0.50 1.00 1.50 -0.20 -0.40 -0.60 Tim e [UI] Datasheet 33 LXT3108 — Octal T1/E1/J1 LH/SH LIU 9.1.2.1 Intel Pulse Template Matching (Intel PTM) Each transmit baud, or UI, is divided into either 16 (E1) or 15 (T1) sub-phases. The pulse amplitude during each phase is described by an 8 bit, 2’s complement, binary word. Thus, each pulse can be described with a timing resolution of Tper/16 and an amplitude resolution of Full Scale/128. Up to 48 transmit words can be used, allowing each shaped pulse to extend up to three baud. Typically SH pulses use only 15 or 16 words, although all 48 bytes are available. LH pulse shaping may extend over three baud. To use the PTM, two operations must take place. • The desired 8-bit words must be loaded into the LXT3108’s LIU local memory. This can be done through a host API. The coding is 2’s complement from +127 to -127 where a code of +127 creates a full scale pulse at the output. Each LSB is approximately 1/127 of FS. Care must be taken by the users, as it is possible to create nonsensical pulse shapes either by miscoding or by saturating the DAC. • After the words are loaded, assert ATWG_EN by loading value “01h”as shown in “Transmit Control Page Register, 03h” on page 58. The transmit DAC will use the codes from the local ROM registers. These settings are maintained as long as power is applied to the device and reset is not asserted. They can be overwritten at anytime and are not lost when the transmitter is powered-down as shown in Figure 13 on page 36. The contents of the local memory are lost when power is removed from the chip and initialized to all zeros when reset is asserted. Note: The user must be careful not to assert ATWG_EN if the contents of the local memory have not been properly initialized. Adjustments to the output signal can be made using the Intel PTM software. The Intel PTM software simplifies the process of modifying the output signal by handling all of the register manipulation for you. 9.2 Transmit Digital Interface Input data for transmission onto the line is clocked serially into the device at the TCLK rate. TPOS and TNEG are the bipolar data inputs, and TDATA accepts unipolar data. Software controls how input data passes through: • The jitter attenuator, according to “JA Control Two Page Register, 1Dh” on page 63. • The B8ZS/HD3 encoder, according to “Line Coding Control One Page Register, 1Ch” on page 62. Data is clocked on the falling edge of TCLK as shown in Figure 12, “Transmit Interface Timing” on page 35. 34 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 12. Transmit Interface Timing V TCLK tsut TPOS TNEG 9.2.1 tht Transmit Idle Operation and Three Stating Drivers When the transmitter is not being used, the designer conserves power by powering down the driver circuit. There are two ways to power down the transmitter: • Set bit five, Transmit Clock Detect Enable in the Transmit Control Register 03h to 0 and hold TCLK input High for 16 clock cycles. • Assert the TXPD bit in “Port Master Control Page Register, 01h” on page 57, in software. In this state, TTIP and TRING are at high impedance, and all of the analog circuitry associated with the transmitter is turned off. After restarting TCLK or clearing the TXPD bit, it may take several milliseconds for the transmitter to achieve steady state performance. For redundancy applications, it is desirable to three state each driver while leaving the transmitter circuitry turned on. In this case, there are three ways to three state the drivers: • Set the OE pin low, which affects all eight ports at the same time. • Set the OES bit high in “Transmit Control Page Register, 03h” on page 58. In this state, TTIP and TRING will enter a high impedance state. However, in this state the transmitter will remain powered up. This will allow two transmitters to be connected in parallel for redundancy applications. Table 6. Powering Down the Transmitter with Static TCLK TXCLK Effect TXCLK = 1 > 16 MCLK cycles OR TXPD = 1 Transmitter enters Powered-down State. TTIP & TRING enter high_impedence state. TXCLK = 0 > 16 MCLK cycles TTIP & TRING enter high-impedance state. Datasheet 35 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 13. TCLK Power Down Timing MCLK TCLK 16 MCLK cycles Tx Power 10.0 Receiver The eight receivers in the LXT3108 are identical and operate independently. The following paragraphs describe the operation of one receiver. The receiver is coupled to the line through a 1:1 transformer. The input common mode level is set on-chip. Recovered data is presented at the port’s RPOS/RNEG or RDATA pins. The recovered clock is present at the port’s RCLK pin. Upon loss of signal, RCLK is derived from MCLK. Refer to the test specification section for receiver timing. 10.1 Master Reference Clock The MCLK input to the LXT3108 requires Master Clock (MCLK) for operation. This clock is used by the on-chip Clock Adapter (CLAD). The MCLK can be one of the following: 1x, 2x, 4x, 8x (T1 or E1). The LXT3108 requires only one clock (e.g., 2.408 MHz) for all modes (T1/E1/J1). The onchip CLAD configuration is specified in CLAD_CONFIG1register in table 19. The data and timing recovery circuits provide input jitter tolerance significantly better than required by AT&T Pub 62411 and ITU G.823. See the Test Specifications section Table 47 to Table 57 and Figure 25 to 31 for more information. 10.2 Receiver Digital Interface The recovered data goes to the Loss of Signal (LOS) Monitor, and through the Alarm Indication Signal (AIS, Blue Alarm) Monitor. Received data may go through either the B8ZS or HDB3 decoder or neither. Finally, the data is sent to the framer either as unipolar or bipolar data on the RDATA or RPOS/RNEG pins, and the recovered clock drives the RCLK pin. Received data is clocked out of the LIU on the active edge of RCLK. The user can specify either the rising or falling edge of RCLK for clocking out data on RDATA or RPOS/RNEG. The receiver LOS function monitors the received signal level and indicates if the signal drops below the levels given in Table 7. In the unipolar mode, the RNEG output indicates received BPV. BPVs are also counted in the internal BPV counter when BPV count is enabled. Refer to “Monitoring BPV and EXZ Line Coding Violations” on page 49. 36 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 10.2.1 Receiver Idle Conditions The receiver is powered down under either of the following conditions: • When the RXPD bit described in “Port Master Control Page Register, 01h” on page 57 is set. • When the CHANEN bit described in “Port Receive Enable Page Register, 02h” on page 58 is set. This bit also powers down the transmitter when set. Under the powered down condition, the RPOS, RNEG, and RDATA are not defined. The RCLK signal stays at 1.544 MHz when the LIU port is configured in T1 or J1 mode. The RCLK signal stays at 2.048 MHz when the LIU port is configured in E1 mode. 10.3 Receiver Line Interface The LXT3108 receiver line interface provides: • Programmable line termination described in “Termination Control Page Register, 05h” on page 59. • Programmable sensitivity described in “Receive Control Page Register, 04h” on page 58. • Monitor mode, also in “Receive Control Page Register, 04h”. The LXT3108 internally terminates the input line for twisted pair applications with a combination of a single external resistor and programming the termination register to match the line impedance. An advanced DSP- based receiver provides equalization and timing recovery for signals with up to -43 dB of cable loss (E1) or -36 dB of cable loss (T1) in the presence of input noise and jitter as specified in ANSI T1.408. The receiver provides up to -43 dB of sensitivity @ 1024 KHz (E1) or up to 36 dB of sensitivity @ 772 KHz (T1) in steps of approximately 2 db under software control as described in “Receive Control Page Register, 04h”. The advantage these features provide is industry standard performance without component changes. 10.3.1 Receive Termination Impedance The receiver is coupled to the line through a 1:1 transformer. In E1 mode, the receiver input impedance is high (above 10K Ω). Figure 14. Typical Receiver Interface 1:1 RTIP 121Ω Rx LINE RRING Datasheet 37 LXT3108 — Octal T1/E1/J1 LH/SH LIU For E1 120 Ω, the receiver termination is set by the parallel combination of a precision 121 Ω ± 1% external resistor and the internal (high) impedance. Figure 14 shows a typical receiver interface. The total input impedance can be set by the user by setting the appropriate bits in register RXTERM, address 05h, in the page registers. For T1 100 Ω, the internal resistor value is 580 Ω ± 5%. For J1 110 Ω, the internal resistor value is 1200 Ω ± 5%. 10.3.2 Receiver Sensitivity Programming Under some conditions it may be desirable to limit the sensitivity of the receiver. This can be done by programing “Receive Control Page Register, 04h” on page 58. This limits the range of the receiver equalizer to the approximate values shown in Table 7. The designer selects the affected port as described in the “Port Page Select Register, CPS, 00h” on page 55 for all ports simultaneously or for each port individually. Table 7. Programming Receiver Sensitivity RXCON RX[4:0] hex T1/E1 Maximum receiver sensitivity (dB) Maximum receiver sensitivity (dB) 00 -43 -36 01 -40 -34 02 -38 -32 03 -36 -30 04 -34 -28 05 -32 -26 06 -30 -24 07 -28 -22 08 -26 -20 09 -24 -18 0A -22 E1 10.3.2.1 T1/E1 -16 T1 0B -20 -14 0C -18 -12 0D -16 -10 0E -14 -8 0F -12 -6 10 -10 -4 11 -8 -2 12 -6 0 13 -4 -36 14 2 -36 15 - 1F -43 -36 Receiver Monitor Mode The receive equalizer of the LXT3108 can be used in Monitor Mode applications. Monitor Mode applications require a resistive attenuation of the signal in addition to a small amount of cable attenuation (less than 6 dB). Asserting the MON bit in “Receive Control Page Register, 04h” on 38 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU page 58 configures the device to work in its Monitor Mode. The device must be in its LH receiver mode for Monitor Mode which, is controlled by the RXSH bit in “Receive Control Page Register, 04h”. With the device in Monitor Mode, the receive equalizer handles signals attenuated resistively by 20 to 35 dB, plus 0 to 6 dB of cable attenuation for both E1 and T1 applications. 10.4 Receiver Status Information The status of the receiver can be monitored though “Receiver Equalizer Status Zero Page Register, 06h” on page 59, while equalizer settings can be checked with “Receiver Equalizer Status One Page Register, 07h” on page 59 and “Receiver Equalizer Status Two Page Register, 08h” on page 60. “Receiver Equalizer Status Two Page Register, 08h” contains status bits that indicate LOS. The contents of “Receiver Equalizer Status Zero Page Register, 06h”and “Receiver Equalizer Status One Page Register, 07h” can be used to estimate the line attenuation, which can be translated to line length. 11.0 Jitter Attenuation (JA) A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) FIFO provides Jitter attenuation. The FIFO depth is selectable for either 32 or 64 bits, through “JA Control Two Page Register, 1Dh” on page 63. The JAL is internal and does not require an external crystal or a highfrequency (higher than line rate) reference clock. The JA can be placed in either the receive or transmit data path. The “JA Control Two Page Register, 1Dh” selects JA enabled or disabled, and selects either the receive or the transmit path. Figure 15. Jitter Attenuation Loop TPOS TPOSo RPOS RPOSi TNEG FIFO RNEGi IN CK TCLK RCLKi 1.544/2.048 MHz IN OUT CK DPLL OUT TNEGo RNEG TCLK RCLK x 32 The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the register x1D). Data is clocked into the FIFO with the associated clock signal (TCLK or RCLK) and clocked out of the FIFO with the dejittered JAL clock, as seen in Figure 15. When the FIFO is within two bits of overflowing or underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator Datasheet 39 LXT3108 — Octal T1/E1/J1 LH/SH LIU produces a delay of up to 16 or 32 bits in the associated path. Please refer to “Test Specifications” for details. This advanced digital jitter attenuator meets the latest jitter attenuation specifications shown in Table 8. Table 8. Jitter Attenuation Specifications T1 E1 AT&T Pub 62411 ITU-T G.735 GR-253-CORE ITU-T G.742 TR-TSY-000009 ETSI CTR12/13 ITU-T G.783 BAPT 220 11.1 Digital Jitter Attenuator (DJA) Status DJA status detection for both underflow and overflow conditions is reported in “Alarm Status One Page Register, 12h” on page 61. Two maskable processor interrupts for the DJA are controlled by “Interrupt Enable Page Register, 11h” on page 61. Details about both types of DJA interrupt status are reported in “Interrupt Status Two Page Register, 13h” on page 62. 12.0 Network Control and Maintenance Functions 12.1 Diagnostic Modes The LXT3108 offers the following diagnostic modes: • Network Loop (NLOOP) Code Generator/Detector. • Analog loopback (ALOOP) digital transmitter to analog transmitter/receiver pins back to digital receiver pins. • Remote loopback (RLOOP) analog receiver to analog transmitter pins. • Digital loopback (DLOOP) digital transmitter to digital receiver pins. • Transmit All Ones (TAOS) signal sent by transmitter driver to line. The LXT3108 offers three loopback modes for diagnostic purposes: Analog, Remote, and Digital Loopback. Network Loop codes activate Remote Loopback from a pattern contained in the signal traffic passing through the LIU receiver. Loopbacks are selected by writing to the appropriate port’s ALOOP bit in “Port Master Control Page Register, 01h” on page 57, or DLOOP, NLOOP or RLOOP bits in “Loopback Enable Page Register, 10h” on page 61. The Transmit All Ones control bit is set in “Transmit Control Page Register, 03h” on page 58. 12.1.1 In-Band Network Loop Up or Down Code Generator/Detector The LXT3108 can transmit in-band Network Loop Up or Loop Down codes. The Loop Up code is 00001. The Loop Down code is 001. A Loop Up code transmission occurs when the respective bits in register x10, are set. A Loop Down code transmission occurs when the respective bits in register x10 are set. 40 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Network Loopback (NLOOP) can be initiated only when the Network Loopback detect function is enabled. Writing a “1” to the NLOOP bit in “Loopback Enable Page Register, 10h”enables this mode. With NLOOP detection enabled, the receiver looks for the NLOOP data patterns (00001 = enable, 001 = disable) in the input data stream. When the receiver detects an NLOOP enable data pattern repeated for a minimum of five seconds, the device enables RLOOP. The device responds to both framed and unframed NLOOP patterns. Once NLOOP detection is enabled at the chip and activated by the appropriate data pattern, it is identical to Remote Loopback (RLOOP). NLOOP is disabled by receiving the 001 pattern for five seconds, or by activating RLOOP or ALOOP, or by disabling NLOOP detection in software. 12.1.2 Analog Loopback Analog Loopback (ALOOP) exercises the maximum number of functional blocks. ALOOP operation disconnects the RTIP/RRING signal path inputs from the line and routes the transmit outputs back into the receive inputs. This tests the transmitter, receiver and timing recovery sections. The ALOOP function overrides all other loopback modes. When analog loopback is selected the receive line is still terminated by the internal termination. When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver inputs (RTIP & RRING) as shown in Figure 16. Data and clock are output at RCLK, RPOS & RNEG pins for the corresponding LIU. Note that signals on the RTIP & RRING pins are ignored during analog loopback. The ALOOP bit is in“Loopback Enable Page Register, 10h”. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* Figure 16. Analog Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled 12.1.3 Digital Loopback When digital loopback is selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and are output on the RCLK, RPOS and RNEG pins (see Figure 17). The data presented on TCLK, TPOS and TNEG is also output on the TTIP and TRING pins. Note that signals on the RTIP and RRING pins are ignored during digital loopback. Datasheet 41 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 17. Digital Loopback MCLK HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* TAOS Mode TCLK TPOS TNEG JA* Timing & Control TTIP TRING (ALL 1s) Timing Recovery RTIP RRING * If Enabled 12.1.4 Remote Loopback During remote loopback as shown in Figure 18, the RTIP and RRING inputs are routed to the transmit circuits and are output on the TTIP and TRING pins. Note that input signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* Figure 18. Remote Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled 12.1.5 Transmit All Ones (TAOS) The TAOS mode is set by asserting the TAOS bit in “Transmit Control Page Register, 03h”. Note that the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability as shown in Table 54, “Master and Transmit Clock Timing Characteristics” on page 72. Both DLOOP and ALOOP modes function correctly with TAOS active. However, RLOOP is inhibited when TAOS mode is active. 42 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 19. TAOS Data Path MCLK TCLK TPOS TNEG HDB3/B8ZS Encoder* RCLK RPOS RNEG HDB3/B8ZS Decoder* TAOS mode Timing & Control TTIP TRING (ALL 1s) Timing Recovery JA* RTIP RRING * If Enabled Figure 20. TAOS with Digital Loopback MCLK HDB3 Encoder* RCLK RPOS RNEG HDB3 Decoder* TAOS Active TCLK TPOS TNEG Timing & Control TTIP TRING (ALL 1s) Timing Recovery RTIP RRING * If Enabled Figure 21. TAOS with Analog Loopback MCLK TAOS Mode RCLK RPOS RNEG Timing & Control HDB3/B8ZS Encoder* HDB3/B8ZS Decoder* TCLK TPOS TNEG TTIP TRING (ALL 1s) JA* Timing Recovery RTIP RRING * If Enabled 12.2 Line Coding This section describes the LXT3108 functionality related to line coding and monitoring. The LIU’s digital framer interface performs two functions: • Provides a bipolar or unipolar interface to a framer. Datasheet 43 LXT3108 — Octal T1/E1/J1 LH/SH LIU • Offers line coding and decoding of AMI, B8ZS and HDB3. Each of these functions is described in detail below: The LIU digital framer interface can be operated in one of two functional modes as described in Table 38, “Line Coding Control One Page Register, 1Ch” on page 62: • BIPOLAR - Digital Positive/Negative/Clock signals, indicating signal polarity. • UNIPOLAR - Digital Data/Clock, indicating NRZ data. 12.2.1 Alternate Mark Inversion (AMI) (per: ITU G.703) AMI is a Return-to-Zero (RZ) format where a binary “one” (mark) is represented by either a positive or negative going pulse and a binary “zero” (space) is represented by the absence of a pulse. The LXT3108 supports either of the standards listed below by user selection in Table 38, “Line Coding Control One Page Register, 1Ch” on page 62 as well as Table 31, “LOS Window Page Register, 0Bh” on page 60 through Table 33 on Page 60. AMI coding alone does not provide any method of ensuring compliance to mark/space requirements. The term “AMI coding” is often used to mean that no specific methods are used to suppress excess zeroes in the signal. — ANSI T1.403: No more than 15 consecutive zeros. At least N ones in each and every time window of 8*(N+1) bits, where N = 1 through 23. — FCC Part 68.318: No more than 80 consecutive zeroes. An average ones density of at least 12.5%. Each consecutive pulse should alternate in polarity (i.e., a positive pulse should always be followed by a negative pulse and a negative pulse should always be followed by a positive pulse) regardless of the number of intervening spaces between the two pulses. AMI comes from this: alternating marks inversion. Two consecutive pulses of the same polarity are known as a bipolar violation (BPV). The LXT3108 actively monitors the line signal and provides a count of detected BPVs for performance monitoring purposes. By definition, all T1 line signals use basic AMI line coding. However, because T1 receivers rely on the presence of marks in the signal to recover clocking, various standards specify maximum space and minimum mark density requirements. These are cited below. 12.2.1.1 Bipolar with Eight Zero Substitution (B8ZS) (per: ANSI T1.102) The LXT3108 allows separately controlled transmit and receive B8ZS encoding for each port at T1 line rate described in “Line Coding Control One Page Register, 1Ch” on page 62. The LXT3108 performs both B8ZS coding (on the T1 transmitted signal) and B8ZS decoding (on the T1 received signal). Received BPVs that are part of the B8ZS pattern are not counted as BPVs in the coding error counter. B8ZS overcomes limitations of ZCS discussed below and allows the support of clear port (64 kbps) data. It is compatible with all standard T1 framing formats. In B8ZS coding, eight consecutive zeroes in the T1 data stream will be replaced by the B8ZS substitution pattern of “000VB0VB” in which “V” is an intentional BiPolar Violation (BPV) and “B” is a valid bipolar mark. Note that the 44 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU polarity of the BPVs and marks depends upon the polarity of the last mark before the “eighth zero” occurs. This substitution is made regardless of where the eight consecutive zeroes occur in the datastream, including framing, signaling, and alarm bits. As opposed to ZCS, which operates on data within a DS0 port, B8ZS coding can occur across frame boundaries. 12.2.1.2 High Density Bipolar Three (HDB3) (per: ITU G.703) The LXT3108 allows separately controlled transmit and receive HDB3 encoding for each port at E1 line rate described in “Line Coding Control One Page Register, 1Ch” on page 62. Receive side HDB3 decoding is selected by setting the decoding bit in “Line Coding Control One Page Register, 1Ch”. Similarly, transmit side HDB3 encoding is selected by setting the encoding bit in “Line Coding Control One Page Register, 1Ch”. Received BPVs that are part of the HDB3 pattern are not counted as BPVs in the coding violation error counter. In HDB3 coding, four consecutive zeroes in the E1 data stream will be replaced by the HDB3 substitution pattern of either “000V” or “B00V, in which “V” is an intentional bipolar violation (BPV) and “B” is a valid bipolar mark. This limits the maximum number of consecutive spaces to three. The choice of substitution pattern is made so that the number of B pulses between consecutive V pulses is odd (i.e., successive V pulses are of alternate polarity). This substitution is made regardless of where the four consecutive zeroes occur in the datastream, including framing, signaling, and alarm bits. The LXT3108 performs both HDB3 coding on the E1 transmitted signal and HDB3 decoding on the E1 received signal. 12.3 Network Maintenance Functions 12.3.1 Loss Of Signal (LOS) While LOS appears at each port’s LOS pin, it can be detected by software reading the LOS bit in the “Receiver Equalizer Status Two Page Register, 08h” on page 60. A maskable processor interrupt controlled by “Interrupt Enable Page Register, 11h” on page 61 is available. Details about LOS interrupt status are reported in “Interrupt Status Two Page Register, 13h” on page 62. Depending on whether the port is configured for T1 or E1 service, the LOS will be cleared for the appropriate zeros density after the detection of LOS as discussed below. Three user registers are provided for customizing the received marks density LOS detector. Users can select: • The number of consecutive spaces that must be received to declare LOS in “LOS Window Page Register, 0Bh” on page 60. • The number of marks that must be received within that window to clear LOS “LOS Set Threshold One Page Register, 0Ch” on page 60. • The number of consecutive zeros that, if received while LOS is asserted, will continue to reassert LOS in “LOS Reset Threshold Two Page Register, 0Dh” on page 60. The default values are given in Table 11. Each receiver has a multi-function LOS detector that is used to meet ITU T1.231 or G.775 requirements for T1 or E1 systems. These detectors monitor both the received signal amplitude and the received marks density according to the following table. Datasheet 45 LXT3108 — Octal T1/E1/J1 LH/SH LIU Users may change these values by setting the USR_LOS bit in “Port Master Control Page Register, 01h” on page 57. If this bit is set, then the desired LOS Window, LOS Set, and LOS Reset values must be programmed for proper LOS operation. For E1 SH operation the LOS operates based on the peak received amplitude during a fixed window. For G.775 the window length can be programmed by “LOS Window Page Register, 0Bh”. A minimum data density of 1 in 16 is required to clear LOS. Table 9. LOS Criteria for LXT3108 Standard LOS Declared LOS Cleared T1.231 No pulse transitions for 175 consecutive clock cycles 12.5% mark density in 175 clock cycles and less than 100 consecutive zeroes T1 ITU I.431 More than 28dB below nominal output level, for 1544 bit periods Less than 25dB, and 12.5% mark density in a 32-bit window, and less than 15 consecutive zeroes E1 G.775 More than 18dB below nominal output level, for 32 bit periods Less than 15dB, and 12.5% mark density in a 32-bit window, and less than 15 consecutive zeroes E1 ITU I.431 More than 18dB below nominal output level, for 2048 bit periods Less than 15dB, and 12.5% mark density in a 32-bit window, and less than 15 consecutive zeroes E1 ETSI 300 233 More than 18dB below nominal output level, for 2048 bit periods Less than 15dB, and 12.5% mark density in a 32-bit window, and less than 15 consecutive zeroes E1 long haul No pulse transitions for 175 consecutive clock cycles 12.5% mark density in a 32-bit window, and less than 15 consecutive zeroes Table 10. LOS Register Configurations Reg addr: 01H (master) 04H (rxcon) LOS Criteria Description bit-4 bit-3 bit-0 bit-7 usr_los I431 E1/T1 rxah 0 0 0 x T1.231 Marks density detection 0 1 0 x I.431 Amplitude detection 0 0 1 1 G.775 Amplitude detection 0 0 1 x I.431/ETSI Amplitude detection 0 0 1 0 E1 long haul Marks density detection 1 0 x x User LOS 1 Marks density detection 1 1 x x User LOS 2 Amplitude detection NOTE: 1. x: don’t care. . Table 11. LOS Selection Defaults 46 T1/E1 Window Size Marks in Window to Clear Marks in Window to Reset T1 175 21 100 E1 32 4 16 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU The receiver monitor loads a digital counter at the RCLK frequency. The counter will increment each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is replaced by MCLK at the RCLK output with a minimum amount of phase errors. (MCLK is required for receive operation.) When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will be high during the entire LOS detection period for that port. 12.3.2 Alarm Indication Signal (AIS) Alarm Indication Signal reports all ones signal received at the RTIP and RRING pins. Once AIS is detected, the port status flag is set in “Alarm Status One Page Register, 12h” on page 61. A maskable processor interrupt controlled by “Interrupt Enable Page Register, 11h” on page 61 is available. Details about AIS interrupt status are reported in “Interrupt Status Two Page Register, 13h” on page 62. Depending on whether the port is configured for T1 or E1 service, the AIS will be cleared for the appropriate zeros density after the detection of AIS as shown below. . Table 12. AIS Service Condition Variations T1/E1 Window Size Spaces in Window to Clear Spaces in Window to Reset T1 3 msec. 6 5 E1 512 3 2 (per: ETSI 300233) E1 AIS is declared when less than three spaces (i.e., 2 or less zeroes) are detected in a 250 µsec period of data (512 bit window). This condition should be reliably detected in the presence of a 1.0E-03 Bit Error Rate (BER), implying that a framed all-ones pattern will not be mistaken as an AIS. (per ITU G.775) E1 AIS is detected when less than three spaces are detected in two consecutive 512-bit wide windows. The AIS is cleared when three or more zeros are detected in two consecutive 512-bit wide windows. (per: ANSI T1.231) T1 AIS (Blue Alarm) is declared when less than nine spaces (i.e., 8 or less zeros) are detected in a 8192-bit wide window. When AIS is detected, the appropriate bit in the AIS status register is set and a microprocessor interrupt is generated (unless masked). AIS is cleared when 9 or more zeros are detected in a 8192-bit wide window. 12.3.3 NLOOP Status With NLOOP detection enabled in “Loopback Enable Page Register, 10h” on page 61, the receiver looks for the NLOOP data patterns (00001 = enable, 001 = disable) in the input data stream. When the receiver detects an NLOOP enable data pattern repeated for a minimum of five seconds, the device enables RLOOP and the port status flag is set in “Alarm Status One Page Register, 12h” on page 61. The device responds to both framed and unframed NLOOP patterns. NLOOP is cleared by: • Receiving the 001 pattern for five seconds. Datasheet 47 LXT3108 — Octal T1/E1/J1 LH/SH LIU • Activating RLOOP in “Loopback Enable Page Register, 10h” on page 61 or ALOOP in “Port Master Control Page Register, 01h” on page 57. • Disabling NLOOP detection in “Loopback Enable Page Register, 10h”. A maskable processor interrupt for NLOOP is controlled by “Interrupt Enable Page Register, 11h” on page 61. Details about NLOOP interrupt status are reported in “Interrupt Status Two Page Register, 13h” on page 62. 12.3.3.1 T1 AMI/B8ZS BPVs In T1 service, only one type of T1 BPV line coding violation is used: A Bipolar Violation (BPV) is defined as any two consecutive pulses (marks) of the same polarity with AMI coded bit stream. BPVs that are part of the B8ZS zero-substitution coding will not be reported. All other BPVs are reported and counted. The LXT3108 actively monitors the line signal for this type of coding violation and increments the BPV counter for performance monitoring purposes. BPVs detected in the receive direction are also reported on RNEG/RBPV output, when the LIU is configured in unipolar mode of operation. 12.3.3.2 E1 AMI/HDB3 BPVs Two basic types of E1 line coding violations are defined: 1. ITU G.703 - A BiPolar Violation (BPV) is defined as any two consecutive pulses (marks) of the same polarity with AMI coded bit stream. 2. ITU O.161- An HDB3 coding violation is defined as the occurrence of two consecutive BPVs of the same polarity that are not part of the HDB3 zero substitution coding. The LXT3108 actively monitors the line signal for both types coding violations and increments the BPV counter for performance monitoring purposes. Receive BPVs are also reported on the RNEG/ RBPV output, when the LIU operates in unipolar mode. 12.3.3.3 Excess Zeroes (EXZ) The definition of an EXZ depends upon the line coding format, as explained in Table 13. The line signal is monitored for any violations of the maximum space rule as set in “Line Coding Control One Page Register, 1Ch” on page 62. If selected, EXZ occurrences increment the BPV counter for performance monitoring purposes. Table 13. Excess Zero (EXZ) Definitions 48 Coding Method EXZ Definition (ANSI) EXZ Definition (FCC) AMI Any string greater than 15 consecutive 0s Any string with greater than 80 consecutive zeroes HDB3 Any string greater than 3 consecutive 0s Any string with greater than 3 consecutive zeroes B8ZS Any string greater than 8 consecutive 0s Any string with greater than 8 consecutive zeroes Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 12.3.4 Monitoring BPV and EXZ Line Coding Violations BPV and EXZ line coding violations are reported on signal traffic received at RTIP and RRING pins. Once a BPV or EXZ condition is detected, the port status flag is set in “Alarm Status One Page Register, 12h” on page 61. The LXT3108 has two registers that form a 16-bit counter for each port to monitor BPVs and excess zeroes. The counter mode is set by bits 7 through 5 in “Line Coding Control One Page Register, 1Ch”. The counter can be enabled to count both BPVs and excess zeroes or, for trouble-shooting purposes, to count either BPVs or Excess Zeroes only. These counters, “BPV Counter High Byte Page Register, 1Eh” and “BPV Counter Low Byte Page Register, 1Fh”, will increment when there is a valid code violation. The counter has a shadow register that is updated at one second intervals. This is done with an internal one second timer. The one second timer is based on the RCLK. Each port uses its own one second timer. The user should read the 16 bit shadow register (addr 1Eh & 1Fh) for BPV count accumulated during the previous one second time frame. The count value stored in the shadow register can be read by the host. 13.0 Host Interface The microprocessor interface is used to relay configuration, control, status, and data information between the LXT3108 and an external microprocessor or micro controller. The microprocessor interface supports MPC860/M68360 (memory like bus), M68302 (standard Motorola bus), the i960/i486 processor bus. 8-bit address and data buses are supported. Nonmultiplexed address and data busses are supported along with a multiplexed address and data bus mode. The user selects the processor type by tying the MPI_TYPE 1 & 2 pins appropriately. The processor interface can operate up to a bus cycle of 33 Mhz. The MPC860 requires five wait states and the i960 also requires five wait states. Handshaking and automatic wait state generation are supported. The latency of processor access is fixed so the use of the wait state signal is optional. The LXT3108 provides extensive interrupt support. All interrupts are independently maskable. One interrupt output is provided. 13.1 Supported Processors and Connections The LXT3108 supports direct connection to the MPC860, M68360, M68302 (M68000 family), i486, and i960 processors. The user selects the type of processor by tying the TYPEx pins to the appropriate GND and Vcc connections. The connections between the processor pins and the MPI_TYPE programming are defined as below. 13.1.1 MPC860/M68360 The Motorola MPC860 and M68360 are supported in this mode. Note the LXT3108 host interface pins follow the MPC860 data endian fashion. For the MPC860, though there is no need for asynchronous wait states, relaxed write timing should be used. The LXT3108 requires write data to be valid prior to the falling edge of the write enable. Datasheet 49 LXT3108 — Octal T1/E1/J1 LH/SH LIU . Table 14. MPC860/M68360 Mode 8-Bit Mode Pin 13.1.2 MPC860 68360 TYPE1 0 0 TYPE2 0 0 DB0 D0 D7 DB7 D7 D0 AD0 A24 A7 AD7 A31 A0 CS CS CS DS OE OE RW R/W# R/W# MPI_CLK WE0 WE0 RDY TA DSACK1 M68302 The M68302 (or the M68000) is supported in this mode. This is commonly referred to as the Motorola bus. Table 15. 68302 8-bit mode 13.1.3 Pin 68302 TYPE1 0 TYPE2 1 DB0 D0 DB7 D7 AD0 A0 AD7 A7 CS CS DS DS RW R/W# MPI_CLK 1 RDY DTACK i960/i486 The Intel i960/i486 family is supported in this mode. This is a synchronous bus interface with the timing being derived from the MPI_CLK input. Internally all operations will be performed on the next cycle after ADS is asserted. Five wait states are required. 50 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 16. i960/i486 Mode Pin i960/i986 TYPE1 1 TYPE2 0 DB0 D0 DB1 D1 DB7 D7 AD0 A0 AD7 A7 CS CS DS ADS RW W/R# MPI_CLK CLKO1 RDY 13.2 READY Interrupts There are four interrupt sources: 1. Status change in the Loss of Signal, LOS, bit of “Receiver Equalizer Status Two Page Register, 08h” The LXT3108’s analog/digital LOS processor continuously monitors the receiver signal and updates the specific LOS status bit to indicate presence or absence of a LOS condition. 2. Status change in the AIS (Alarm Indication Signal) bit of “Alarm Status One Page Register, 12h”. The LXT3108’s receiver monitors the incoming data stream and updates the specific AIS status bit to indicate presence or absence of an AIS condition. 3. Status change in NLOOP (Network Loop Code) bit of “Alarm Status One Page Register, 12h”. 4. Elastic Store overflow or underflow (DJA overflow or underflow) bits of “Alarm Status One Page Register, 12h”. The LXT3108 jitter attenuator updates these based on DJA response to jitter on incoming signal. 13.2.1 Interrupt Enable The LXT3108 provides a latched interrupt output (INT). An interrupt occurs any time there is a transition on any enabled bit in the status register. Writing a logic “1” into the enable register will enable the respective bit in the respective Interrupt status register to generate an interrupt. The power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers. When there is a transition on any enabled bit in a status register, the associated bit of the interrupt status register is set and an interrupt is generated (if one is not already pending). When an interrupt occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down device. Datasheet 51 LXT3108 — Octal T1/E1/J1 LH/SH LIU 13.2.2 Interrupt Clearing There are two status registers: LOS (08h), AIS, and NLOOP (12h). Reading either status register will clear the corresponding interrupts with the rising edge of the read or data strobe. When there are no pending interrupts left INT pin will go back high. Refer to Figure 22, “Interrupt Processing FlowChart” on page 53 for details. 52 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 22. Interrupt Processing FlowChart Start Enable Interrupts? No Disable Interrups? Yes Yes Write "1" into corresponding interrupt bit in reg 11h No No Write "0" into corresponding interrupt bit in reg. 11h Does interrupt conditions exist? Yes Pin INT* goes Low Read reg. ISR at addr. 02h for port# Read interrupt status Register(ISR), addr 13h for each port that shows an interrupt. Pin INT* on the device goes High when interrupts on all ports are cleared. LOS No LOS Cleared DJAx, NLOOP, AIS Read reg. 08h to get status of LOS Read reg. 12h to get status of DJAx, NLOOP and AIS Is LOS active? Is DJAx, NLOOP or AIS active? Yes LOS condition exists Datasheet Which Interrupt condition exists? Yes No DJAx, NLOOP or AIS condition cleared DJAx, NLOOP or AIS condition exists 53 LXT3108 — Octal T1/E1/J1 LH/SH LIU 14.0 Register Definitions Since the LXT3108 has both global registers and Page Port Registers (PPRs), the first subsection covers the global registers and the second subsection covers the PPRs. The global registers control parameters affecting operation for the entire device. One set of PPR registers controls parameters affecting operation for a single port. Of the nine sets of PPR registers, there is one for each of the eight ports and there is an additional set that controls all eight ports at the same time. Because global registers are programmed differently than PPRs, this section describes the differences: • Access a global register by reading or writing directly to the global register address. This is a single operation to read or write a global register. The CPS register must be set to 00h first. • Access PPRs by writing to a global register, Port Page Select (PPS) at address 00h, with the selected port number. Immediately following this action, access the PPR for the selected port by reading or writing to the chosen PPR address. This is a double operation, one write access to the PPS with the port number followed by a single read or write to a PPR. 14.1 Global Registers This subsection is organized with a summary of the global registers in Table 17 followed by a descriptive listing of each global register starting at Table 18 on Page 55 and ending at Table 43 on Page 64. Table 17 includes the global register names and addresses for the LXT3108. Table 17. Global Register Addresses Name Port Page Select Register ID Register Interrupt Port Register CLAD Configuration Register 1 54 Symbol Binary Address A7-A0 HEX Address Mode CPS 00000000 00 R/W ID 00000001 01 R ICR 00000010 02 R CLAD_CONFIG1 00010001 11H R/W Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 18. Port Page Select Register, CPS, 00h Bit Name Function Writing to this register selects the index to the page for individual port control registers. 7 Soft-reset, resets all ports, and the entire device. 6:4 not used [3 2 1 0] 7-0 PS4-PS0 Index/Page 0000 Selects Global Register Page 0001 Selects Page 1 - control registers for Port 0 0010 Selects Page 2 - control registers for Port 1 0011 Selects Page 3 - control registers for Port 2 0100 Selects Page 4 - control registers for Port 3 0101 Selects Page 5 - control registers for Port 4 0110 Selects Page 6 - control registers for Port 5 0111 Selects Page 7 - control registers for Port 6 1000 Selects Page 8 - control registers for Port 7 1001 Selects write to all page control registers at one time. Note: When CPS Register value equals 9h, Read is disabled Table 19. ID Register, ID, 01h Bit Name 7-0 ID7-ID0 Function This register contains a unique revision code and is mask programmed. Table 20. Interrupt Port Register, ICR, 02h Bit Name Function A “1” indicates that an interrupt occurred in the respective port. Bit 0 = 1, interrupt occurred on Port 0. Bit 1 = 1, interrupt occurred on Port 1. Bit 2 = 1, interrupt occurred on Port 2. 7-0 ICR7-ICR0 Bit 3 = 1, interrupt occurred on Port 3. Bit 4 = 1, interrupt occurred on Port 4. Bit 5 = 1, interrupt occurred on Port 5. Bit 6 = 1, interrupt occurred on Port 6. Bit 7 = 1, interrupt occurred on Port 7. Datasheet 55 LXT3108 — Octal T1/E1/J1 LH/SH LIU hh Table 21. CLAD Configuration Register1, 11h3 Address 11h Description CLAD Configuration Register 1 (CLAD_CONFIG1) Name Status Bit Function CLAD_PSRST 7 This bit initializes the CLAD. Default for this bit is “0”. It must be set to “1” for CLAD to work. If during operation a “0” is written into this bit by an accident, the CLAD will stop working. A hardware Reset must follow and the CLAD has to be re initialized. CLAD_PWDN 6 RESERVED - write as “0” CLAD_CSSEL 5 RESERVED - write as “0” CLAD_OT1E1 4 MCLK definition bit. When set, clock applied to MCLK pin must be T1- based. When clear (default) MCLK must be E1- based R/W MCLK definition bits. Bits 4,3, and 2 define MCLK frequency 00 = 8x(T1 or E1)(default) DIV<1:0> 3 :2 10 = 4x(T1 or E1) 01 = 2x(T1 or E1) 11 = 1x(T1 or E1) CLAD_TFB 1 RESERVED - write as “0” CLAD_TRST 0 RESERVED - write as “0” NOTE: 1. Upon reset, restored default value is 00h. 2. If an accidental write of 1 during normal operation into any of the RESERVED bits occurs, a hardware RESET must be applied and followed by CLAD initialization. 3. This register is not affected by the soft reset bit. The CLAD configuration register should only be written after reset operation initiated by the RSTB pin. 14.2 Port Page Register Bank (PPRB) Each of the eight LIU ports in the LXT3108 has independent register control available through its Port Page Register Bank. Writing to each bank of registers is a two-step process: • Select the port by writing the port number to the global register Port Page Select (PPS), address 00h. The CPS register at address 00h is a global register across all the pages. Therefore, writing to address 00h at any time will switch the register to read/write access to the last specified value written to address 00h. • Immediately after, access LIU registers for a port by reading or writing the chosen CPRB address. There is an additional mode where all eight ports can be set up to the identical settings by writing first to address 00h with a value of 09h. Table 18 on Page 55 gives an overview of the CPRB structure for each port’s LIU. Each port in the LXT3108 has an individual CPRB. The registers in the port bank structure are descriptively listed in the range of Table 23 on Page 57 through Table 43 on Page 64. 56 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 22. Port Page Register Bank Addresses Symbol Binary Address A7-A0 Address Mode MASTER 0000 0001 01h R/W Port Enable, Not Used RENEN 0000 0010 02h R/W Transmit Control TXCON 0000 0011 03h R/W Receiver Control RXCON 0000 0100 04h R/W TERM 0000 0101 05h R/W RX Equalizer Status 0 RXSTATUS0 0000 0110 06h R RX Equalizer Status 1 RXSTATUS1 0000 0111 07h R RX Equalizer Status 2 RXSTATUS2 0000 1000 08h R LOS Window LOSWINLEN 0000 1011 0Bh R/W Name Port Master Control Termination Control LOS Set Threshold LOSTHRES1 0000 1100 0Ch R/W LOS Reset Threshold LOSTHRES2 0000 1101 0Dh R/W Loopback Enable Register LER 0001 0000 10h R/W Interrupt Enable Register IER 0001 0001 11h R/W Alarm Status Register 1 SR1 0001 0010 12h R Interrupt Status Register 2 SR2 0001 0011 13h R Control Register 1 CR1 0001 1100 1Ch R/W Control Register 2 CR2 0001 1101 1Dh R/W BPV counter High Byte BPVCTRHB 0001 1110 1Eh R BPV counter Low Byte BPVCTRLB 0001 1111 1F R 40h-6Fh R/W Transmit Pulse Shape Coefficients TXCOEF Table 23. Port Master Control Page Register, 01h Address 01h Description Port Master Control Name MASTER Status Bit Description 7 Reserved; writer as “0” 6 TXPD, “1” powers down transmitter section 5 RXPD, “1” powers down receiver section 4 USR_LOS, “1” enables programmable control of digital LOS window, set, and clear conditions 3 I431, “1” enables programmable control of analog LOS levels for set and clear 2 Reserved; writer as “0” 1 ALOOP, “1” enable analog loopback diagnostic mode 0 T1E1, “0” enables T1, 1.544 MHz operation, while “1” enables E1, 2.048 MHz operation R/W Note: Upon reset, restored default value is 0h. Datasheet 57 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 24. Port Receive Enable Page Register, 02h Address Description Name Status 02h Port Enable CHANEN R/W Function If bit 0 is set high, port receiver starts Note: Upon reset, restored default value is 0h. G25 Table 25. Transmit Control Page Register, 03h Address Description Name Status Bit Function 7 Transmit all ones enable (TAOS) 6 Transmit output high impedance (OES) Transmit Clock Detect Enable 5 TCLK detection is enabled when this bit is set to zero. [4..1] 03h Transmit Control TXCON R/W Decode bits 4 to 0 for pre-programmed pulse shapes. 0h • T1 SH 0-133 ft. 1h • T1 SH 134 -266 ft. 2h • 3h • T1 SH 400 -533 ft. 4h • T1 SH 534 - 655 ft. 5h • T1 0dB LH 6h • T1 LH -7.5 dB 7h • 8h • T1 LH -22.5 dB 9h • E1 SH 75 Ω 0Ah • E1 SH 120 Ω E1 LH 75 Ω T1 SH 267 - 399 ft. T1 LH -15 dB 0Bh • 0Ch • E1 LH 120 Ω 0Dh • J1 (no encoded pulse) 0Eh • Not used 0Fh • Not used 0 • ATWG_EN active high enables ATWG operation Note: Upon reset, restored default value is 0h. Table 26. Receive Control Page Register, 04h Address 04h Description Name Status Bit Function RXSH 7 active high limits receiver to SH operation MON_MOD 6 active high enables monitor mode 5 Not used Receiver Control R/W bits 4 to 0 select receiver sensitivity in dB. RXCON [4..0] Refer to Table 7 for details. 58 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 27. Termination Control Page Register, 05h Address Description Name Status Bit [7..6] 05h Termination Control TX/RX TERM Function Decode bits 7 to 6 selecting transmit termination control 0 • 100 Ω 1 • 110 Ω 2 • 120 Ω 3 • 120 Ω [5..2] Bit 5 through 2 are not assigned [1..0] Decode bits 1 to 0 selecting receive termination control R/W 0 • 100 Ω 1 • 110 Ω 2 • 120 Ω 3 • 100 Ω Note: Upon reset, restored default value is 0h. Table 28. Receiver Equalizer Status Zero Page Register, 06h Address 06h Description RX Equalizer Status0 Name Status RXSTATUS0 R Bit [7..0] Function Reserved Note: Upon reset, restored default value is 0h. Table 29. Receiver Equalizer Status One Page Register, 07h Address 07h Description RX Equalizer Status1 Name Status RXSTATUS1 R Bit Function [7..4] Reserved [3..0] Decode AGC state settings. Bits 0 through 3 can be used to determine the cable/attenuation length. Note: Upon reset, restored default value is 0h. Datasheet 59 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 30. Receiver Equalizer Status Two Page Register, 08h Address 08h Description RX Equalizer Status 2 Name RXSTATUS2 Status Bit Function 4 LOS status bit, 1=LOS has occurred. 3 Not used 2 Reserved 1 Reserved 0 Reserved R Note: Upon reset, restored default value is 0h. Table 31. LOS Window Page Register, 0Bh Address 0Bh Description LOS Window Name LOSWINLEN Status R/W Function LOS detector evaluation window. When LOS USER Mode is selected, this register must be programmed to the length of the LOS evaluation window. This is the number of consecutive bits for which the LOS condition must be true before LOS is asserted, (e.g., If set to 255, then 255 consecutive 0s will assert LOS). Note: Upon reset, restored default value is 0h. Table 32. LOS Set Threshold One Page Register, 0Ch Address Description Name Status Function This register controls two functions: 0Ch LOS Set Threshold • In LOS AMP detection mode, it is the treshold to set LOS LOSTHRES1 R/W • In LOS DEN detection mode, it is RSPACELIM Note: Upon reset, restored default value is 0h. Table 33. LOS Reset Threshold Two Page Register, 0Dh Address Description Name Status LOSTHRES2 R/W Function This register controls two functions: 0Dh LOS Reset Threshold • In LOS Amplitude detection mode, it is threshold to reset LOS • In LOS DEN detection mode, it is RMARKCLR Note: Upon reset, restored default value is 0h. 60 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 34. Loopback Enable Page Register, 10h Address Description Name Status Bit 7 [6,5] 10h Loopback Enable Register LER Function Bit 7 inverts the RCLK, if set to 1. Reserved: write as “0” 4 DLOOP, Digital loopback, if set to ‘1’ 3 Transmit network Loop Down code 2 Transmit network Loop Up code 1 NLOOP, Network loopback enabled if set to ‘1’, (Receive) 0 RLOOP, Remote loopback, if set to ‘1’ R/W Note: Upon reset, restored default value is 0h. Table 35. Interrupt Enable Page Register, 11h Address Description Name Status Bit [7..5] 11h Interrupt Enable Register IER R/W Function Reserved: write as “0” 4 DJA Underflow Interrupt Enable, if set to ‘1’ 3 DJA Overflow Interrupt Enable, if set to ‘1’ 2 NLOOP Interrupt Enable, if set to ‘1’ 1 AIS Interrupt Enable, if set to ‘1’ 0 LOS Interrupt Enable, if set to ‘1’ Note: Upon reset, restored default value is 0h. Table 36. Alarm Status One Page Register, 12h Address Description Name Status Bit [7..4] 12h Alarm Status Register 1 SR1 Function Bits 7 to 4 not used. 3 DJA overflow status 2 DJA underflow status 1 NLOOP status 0 AIS status R Note: Upon reset, restored default value is 0h. Datasheet 61 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 37. Interrupt Status Two Page Register, 13h Address 13h Description Interrupt Status Register 2 Name SR2 Status Bit Function [7..5] Bits 7 to 5 not used. 4 LOS interrupt status 3 DJA overflow interrupt status 2 DJA underflow interrupt status 1 NLOOP interrupt status 0 AIS interrupt status R Note: Upon reset, restored default value is 0h. Table 38. Line Coding Control One Page Register, 1Ch Address Description Name Status Bit 7 [6..5] 1Ch Control Register 1 CR1 R/W Function ez mode - 0: ANSI, 1: FCC Decode bits 6 to 5 selecting BPV Counter mode 0h • Enable counting of both BPVs and Excess Zero 1h • Enable counting of BPVs only 2h • Enable counting of Excess Zeroes only 3h • Bit 4 invalid code Functions E1AIS_Sel, 0 = ITU G.775, 1 = ETSI 300233 3 Transmit B8ZS/HDB3 enable, 1 = HDB3/B8ZS 2 Receive B8ZS/HDB3 enable, 1 = HDB3/B8ZS 1 Transmit Unipolar/Bipolar select, 0 = Bipolar 0 Receive Unipolar/Bipolar select, 0 = Bipolar Note: Upon reset, restored default value is 0h. 62 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 39. JA Control Two Page Register, 1Dh Address Description 1Dh Name Status Bit Function JARES 7 1 = reset DJA’s elastic store JARST 6 1 = completely reset DJA JAJC 5 0=jamming enabled, 1=jamming disabled ES64 4 DJA depth select, 0 = 32 bits, 1 = 64 bits, bits 2, 3, and 4 determine the DJA corner frequency. 3 JABW1, bits 2, 3, and 4 determine the DJA corner frequency. Refer to Table 40. JABW0 2 JABW0, bits 2, 3, and 4 determine the DJA corner frequency. Refer to Table 40. JA transmit or receive path 1 0 = JA in receive path; 1 = JA in transmit path JA enable 0 1 = JA enable Control Register 2 R/W JABW1 Note: Upon reset, restored default value is 0h. Table 40. DJA Corner Frequency Selection T1/E1 Mode JA Control Register Bit 4 JA Control Register Bit 3 JA Control Register Bit 2 DJA Corner Frequency T1 0 0 0 3 T1 0 0 1 6 T1 0 1 x 14 T1 1 0 0 3 T1 1 0 1 6 T1 1 1 x 8 E1 0 x x 3 E1 1 x x 3 Table 41. BPV Counter High Byte Page Register, 1Eh Address 1Eh Description BPV counter high byte Name Status BPVCTRHB R Function High byte of the 16-bit BPV counter shadow register Note: Upon reset, restored default value is 0h. Table 42. BPV Counter Low Byte Page Register, 1Fh Address Description Name Status 1Fh BPV counter low byte BPVCTRLB R Function Low byte of the 16-bit BPV counter shadow register Note: Upon reset, restored default value is 0h. Datasheet 63 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 43. Transmit Coefficient Page Register Range, 40h-6Fh Address 40-6F Description Transmit Coefficients for pulse shaping Name Status TXCOEF R/W Function 16/48 8-bit TX filter coefficients Note: Upon reset, restored default value is 0h. 15.0 JTAG Boundary Scan The LXT3108 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. 15.1 Architecture Figure 23 represents the LXT3108 basic JTAG architecture: Figure 23. LXT3108 JTAG Architecture Boundry Scan Data Register BSR Analog Port Scan Register ASR TDI Device Identification Register IDR MUX TDO Bypass Register BYR Instruction Register IR TCK TMS TAP Controller TRST The LXT3108 JTAG architecture includes a TAP Test Access Port Controller, data registers and an instruction register. The following paragraphs describe these blocks in detail. 15.2 TAP Controller The TAP controller is a 16-state synchronous state machine controlled by the TMS input and clocked by TCK (see Figure 24). The TAP controls whether the LXT3108 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 44 describes in detail each of the states represented in Figure 24. 64 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU . Table 44. TAP State Description State Test Logic Reset Description In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the instruction register is set to the ICODE instruction. Run -Test/Idle The TAP controller stays in this state as long as TMS is low. Used to perform tests. Capture - DR The Boundary Scan Data Register (BSR) is loaded with input pin data. Shift - DR Shifts the selected test data registers by one stage toward its serial output. Update - DR Data is latched into the parallel output of the BSR when selected. Capture - IR Used to load the instruction register with a fixed instruction. Shift - IR Shifts the instruction register by one stage. Update - IR Loads a new instruction into the instruction register. Pause - IR Pause - DR Momentarily pauses shifting of data through the data/instruction registers. Exit1 - IR Exit1 - DR Exit2 - IR Exit2 - DR Temporary states that can be used to terminate the scanning process. Datasheet 65 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 24. JTAG State Diagram 1 TEST-LOGIC RESET 0 0 RUN TEST/IDLE 1 SELECT-DR 1 SELECT-IR 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 0 PAUSE-IR 1 1 EXIT2-DR 0 EXIT2-IR 1 0 UPDATE-DR 1 15.3 1 0 PAUSE-DR 0 1 0 UPDATE-IR 1 0 JTAG Register Description The following paragraphs describe each of the registers represented in Figure 23. 66 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 15.3.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register. Bidirectional pins or tristatable pins require more than one position in the register. Data into the BSR is shifted in LSB first. 15.3.2 Device Identification Register (IDR) The IDR register provides access to the manufacturer number, part number and the LXT3108 revision. The register is arranged per IEEE 1149.1 and is represented in Table 45. Data into the IDR is shifted in LSB first. Table 45. Device Identification Register (IDR) 15.3.3 Bit # Value Comments 31 - 28 0010 Revision Number “B” 27 - 12 0000110000100100 Part Number = 3108 11 - 1 00000001001 0 1 Manufacturer ID Set to “1” Bypass Register (BYR) The Bypass Register is a 1-bit register that allows direct connection between the TDI input and the TDO output. 15.3.4 Instruction Register (IR) The IR is a 3-bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 46 shows the valid instruction codes and the corresponding instruction description. Table 46. Instruction Register (IR) Instruction Code # EXTEST 000 Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR. Output pins values are loaded from the BSR. INTEST_ANALOG 010 Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and AT2. SAMPLE/PRELOAD 100 Connects the BSR to TDI and TDO. The normal path between the LXT3108 logic and the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins. IDCODE 110 Connects the IDR to the TDO pin. 111 Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass Register. BYPASS Datasheet Comments 67 LXT3108 — Octal T1/E1/J1 LH/SH LIU 16.0 Test Specifications Table 47. Absolute Maximum Ratings Parameter Sym DC supply (reference to GND)1 Min Max Unit VCC, TvCC -0.5 3.6 V Input voltage, RTIP/RRING VRX TBD TBD V Input voltage, any digital pin VIN GND-0.5 5.5 V Input current, any pin IIN -10 10 mA Storage temperature TSTG -65 150 °C Thermal Resistance, junction to ambient, QFP θJA 16 °C/W Thermal Resistance, junction to ambient, PBGA θJA 17.7 °C/W – V ESD voltage, any pin 2,3 VIN 2000 Caution: Operation at these limits may permanently damage the device. Normal operation at these extremes not guaranteed. 1. TVCC and VCC must not differ by more than 0.3 V during operation. TGND and GND must not differ by more than 0.3 V during operation. 2. Human body model. 3. This is a design target and not a product specification. Table 48. Recommended Operating Conditions Parameter DC supply 2 Ambient operating temperature Sym Min Typ1 Max VCC, TVCC 3.135 3.3 3.465 V TA -40 – 85 °C PD – TBD 2.95 W 100% mark density PD – TBD 2.3 W 50% mark density Unit Test Conditions 3.3V +/- 5% SH Total power dissipation3, 4 T1 PD – TBD 2.5 W 100% mark density PD – TBD – W 50% mark density SH/ PD – TBD 2.8 W 100% mark density LH PD – TBD 2.25 W 50% mark density – TBD – 100 110 120 Ω For T1 mode. For J1 mode. LH E1 Recommended line load to TTIP/ TRING 1. 2. 3. 4. 68 For E1, 120 Ω twisted pair. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. TVCC and VCC must not differ by more than 0.3 V. Power dissipation specifications are TBD. Power dissipation values include shared circuit. Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 49. Electrical Characteristics (Over Recommended Operating Conditions) Parameter Sym Min Typ High level input voltage1 VIH 2 – 5 V Low level input voltage1 VIL – – 0.8 V Output High voltage2 VOH 2.4 VCCIO V 2 VOL – 0.4 V Output Low voltage – Max Unit Test Conditions In idle and power down IDDQ 0 – ±10 µA Input leakage current ILL 0 – ±50 µA Three-state leakage current (all outputs) I3L 0 – ±10 µA TTIP/TRING leakage current ITR – – ±10 µA In idle and power down Output driver rise time TR – – 10 ns 1 pF load Quiescent current 1. LXT3108 interface via CMOS logic levels. 2. Output drivers will output TTL logic levels. Table 50. E1 Transmitter Analog Characteristics Parameter Sym Min. Typ. Max. Unit Internal transmitter impedance tolerance – – TBD 5 % Pulse amplitude variation per LSB CEPT (ITU) – TBD – TBD mV Output pulse amplitude 120 Ω – 2.7 3.0 3.3 V Peak voltage of a space 120 Ω – -0.3 – 0.3 V Transmit amplitude variation with supply – -1 – +1 % Difference between pulse sequences – – 200 mV Transmit return loss 120 Ω twisted pair cable. Measured with PRBS pattern.1 51 kHz to 102 kHz – 6 16 – dB 102 kHz to 2.048 MHz – 8 12 – dB 2.048 MHz to 3.072 MHz – 8 11 – dB Transmit intrinsic jitter; 20 Hz to 100 kHz – – .025 .05 UI Bipolar mode – TBD 60 – ns Unipolar mode – TBD 60 – ns Transmit path delay Test Condition Matching line load TBD Tested at the line side For 17 consecutive pulses Tx path TCLK is jitter free JA Disabled 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. Datasheet 69 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 51. E1 Receiver Analog Characteristics Parameter Sym Min. Typ.1 Max. Unit Test Condition Permissible cable attenuation – – – 43 dB (E1 SH/12 dB) – -13.6 – – dB (E1 LH/43 dB) – -43 – – dB Receiver dynamic range DR – – – Vp Signal to noise interference margin S/I -12 – – dB Per G.703, O.151 @ 6 dB cable Attenuation Programmable Receiver sensitivity @ 1024 kHz (E1 line loss) Loss of signal threshold @1024 kHz Receiver sensitivity @ 1024 kHz – – TBD – mV – – 32 – – G.775 recommendation – – 2048 – – ETSI 300 233 specification – 12.5% – – – 1s density µs Data recovery mode 255 marks Data recovery mode Consecutive zeros before loss of signal LOS reset LOS delay time 30 LOS reset 10 Low limit 1 Hz – 37 – – U.I input jitter 20 Hz to 2.4 kHz – 1.5 – – U.I tolerance 2 100 kHz – 0.2 – – U.I Differential receiver input impedance – – TBD TBD kΩ Common mode input impedance to ground – – TBD Input termination resistor tolerance – – – ±1 % 51 kHz - 102 kHz – TBD – 12 dB 102 - 2048 kHz – TBD – 18 dB 2048 kHz - 3072 kHz – TBD – 14 dB – – 0.03 0.05 UI Input return loss2 Receive intrinsic jitter, RCLK output Receive path delay G.823 recommendation Cable Attenuation is 6 dB @1.024 MHz kΩ Bipolar mode – – 5 – UI Unipolar mode – – 5 – UI Wide band jitter JA Disabled 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. Table 52. T1 Transmitter Analog Characteristics Sym Min. Typ.1 Max. Unit Internal transmitter impedance tolerance – – TBD – % Pulse amplitude variation per LSB – – 30 40 mV Measured on the line side termination. Output pulse amplitude – 2.4 3.0 3.6 V Measured at the DSX Peak voltage of a space – -0.15 – +0.15 V Parameter DSX-1, DS1 Test Condition Matching line load 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. 3. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern. 70 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 52. T1 Transmitter Analog Characteristics (Continued) Sym Min. Typ.1 Max. Unit Transmit amplitude variation with power supply – TBD 1 TBD % Difference between pulse sequences – – – 200 mV Pulse width variation at half amplitude1 – – – 20 ns Line side short circuit current (T1) – – – 150 mA RMS 10Hz - 8 KHz – – – 0.025 UIpk-pk 8KHz - 40 KHz – – – 0.025 UIpk-pk AT&T Pub 62411 10Hz - 40 KHz – – – 0.05 UIpk-pk TCLK is jitter free Wide Band – – – 0.05 UIpk-pk @ 772 KHz – 12.6 – 17.9 dBm T1.102 - 1993 Referenced to power at 772 KHz Parameter Jitter added by Transmitter2 Output power levels3 Transmit Return Loss 2 1544 KHz – -29 – 17.9 dBm 39 KHz - 77 KHz – 6 TBD – dB 77- 1544 KHz – 8 TBD – dB 1544 KHz - 2316KHz – 8 TBD – dB Bipolar mode – 60 – ns Unipolar mode – 60 – ns Transmit path delay Test Condition For 17 consecutive pulses, GR-499-CORE JA Disabled 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. 3. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern. Table 53. T1 Receiver Analog Characteristics Sym Min. Typ.1 Max. Unit Permissible cable attenuation – – 36 TBD dB (T1 SH/12 dB) – -13.6 – – dB (T1 LH/36 dB) – -36 – – dB Receiver dynamic range DR TBD – – Vp Signal to noise interference margin S/I TBD – – dB – – TBD – mV Programmable T1.231 - 1993 Parameter Receiver sensitivity @ 772 kHz (T1 line loss) Loss of signal threshold Loss of signal Hysteresis Consecutive zeros before loss of signal Test Condition @ 772 KHz Receiver sensitivity @ 772 kHz (T1 line loss) TBD – 100 175 250 – 138 – – UI Low limit 1 Hz – input jitter 10 Hz to 300 Hz – 28 – – UI tolerance 2 10 KHz to 100 KHz – 0.4 – – UI Differential receiver input impedance – – 100 – Ω Common mode input impedance to ground – – 120 – Ω AT&T Pub. 62411 @772 kHz 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. Datasheet 71 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 53. T1 Receiver Analog Characteristics (Continued) Parameter Sym Input termination resistor tolerance Input return loss1 Typ.1 Max. Unit – – – ±1 % 39 KHz - 77KHz – TBD – 12 dB 77- 1544 KHz – TBD – 18 dB – TBD – 14 dB 1544 KHz - 2316KHz Receive intrinsic jitter, RCLK output Receive path delay Min. 2 – – 0.03 0.05 UI Bipolar mode – – TBD – UI Unipolar mode – – TBD – UI Test Condition Wide band jitter JA Disabled 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. Table 54. Master and Transmit Clock Timing Characteristics Parameter Master clock frequency2 Sym Min Typ1 Max Unit MCLK 1.544 – 16.384 MHz Master clock tolerance MCLKt – ±50 – ppm Master clock duty cycle MCLKd 40 – 60 % T1 Transmit clock frequency TCLK – 1.544 – MHz E1 Transmit clock frequency TCLK – 2.048 – MHz Transmit clock tolerance TCLKt – – ±50 ppm Transmit clock duty cycle TCLKd 10 – 100 % TPOS/TNEG to TCLK setup time Tsut 10 – – ns TCLK to TPOS/TNEG hold time Tht 10 – – ns Notes Must be supplied 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. MCLK frequency options are listed in Table 2 on page 28. Figure 25. Transmit Clock Timing Diagram TCLK TPOS Tsut Tht TNEG 72 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 55. Jitter Attenuator Characteristics Min. Typ.1 Max. Unit – 2.5 – Hz – 3.5 – Hz – 2.5 – Hz – 3.5 – Hz – 3 – Hz – 3 – Hz – 6 – Hz – 6 – Hz E1 – 3.5 – Hz T1 – 6 – Hz – 16 – UI – 32 – UI – 24 – UI – 56 – UI Parameter 32bit FIFO Test Condition JACF=0 64bit FIFO E1 jitter attenuator 3dB corner frequency 32bit FIFO JACF=1 64bit FIFO 32bit FIFO Sinusoidal jitter modulation JACF=0 64bit FIFO T1 jitter attenuator 3dB corner frequency 32bit FIFO JACF=1 64bit FIFO Jitter attenuator 3dB corner frequency2 32bit FIFO Data latency delay 64bit FIFO 32bit Input jitter tolerance before FIFO overflow or underflow FIFO 64bit FIFO E1 jitter attenuation T1 jitter attenuation @ 3 Hz – -0.5 TBD – dB @ 40 Hz – -0.5 TBD – dB @ 400 Hz – +19.5 TBD – dB @ 100 KHz – +19.5 TBD – dB @ 1 Hz – 0 TBD – dB @ 20 Hz – 0 TBD – dB @ 1 KHz – 33.3 TBD – dB @ 1.4 KHz – 40 TBD – dB – 40 TBD – dB – TBD TBD – UI Delay through the Jitter attenuator only. Add TBD UI for total receive path delay and TBD UI for total transmit path delay. ITU-T G.736 @ 70 KHz Output jitter in remote loopback 2 AT&T Pub. 62411 ETSI CTR12/13 Output jitter 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Guaranteed by design and other correlation methods. Datasheet 73 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 56. Receive Timing Characteristics for T1 Operation Typ1 Max 40 50 60 % – 648 – ns tPWH – 324 – ns T1 Receive clock pulse width Low tPWL 260 324 388 ns RPOS/RNEG to RCLK rising time tSUR – 274 – ns RCLK rising to RPOS/RNEG hold time tHR – 274 – ns Parameter Receive clock duty cycle 2, 3 T1 Receive clock pulse width 2, 3 T1 Receive clock pulse width High 1,3 Sym Min RLCKd tPW Unit 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are for worst case jitter conditions. 3. Worst case conditions guaranteed by design only. Table 57. Receive Timing Characteristics for E1 Operation Parameter E1 Receive clock duty cycle 2, 3 E1 Receive clock pulse width 2, 3 Sym Min Typ1 Max Unit RLCKd 40 50 60 % tPW – 488 – ns tPWH – 244 – ns tPWL 195 244 293 ns RPOS/RNEG to RCLK rising time tSUR – 194 – ns RCLK rising to RPOS/RNEG hold time tHR – 194 – ns E1 Receive clock pulse width High E1 Receive clock pulse width Low 1,3 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles are for worst case jitter conditions. 3. Worst case conditions guaranteed by design only. Figure 26. Receive Clock Timing Diagram tPW RCLK tPWH tPWL tSUR tHR RPOS RNEG RCLK_INV = 0 (bit 7 in reg. 10h = 0) tSUR tHR RPOS RNEG RCLK _INV = 1 (bit 7 in reg. 10h = 1 74 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 27. LXT3108 Output Jitter for CTR12/13 Applications Jitter Amplitude (Ulpp) 0.2 0.15 0.1 7%' 0.05 0 10 Hz 20 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency Figure 28. JTAG Timing Table 58. JTAG Timing Characteristics Parameter Sym Min Typ Max Unit Cycle time Tcyc 200 – – ns J-TMS/J-TDI to J-TCK rising edge time Tsut 50 – – ns J-CLK rising to J-TMS/L-TDI hold time Tht 50 – – ns Tdod - – 50 ns J-TCLK falling to J-TDO valid Datasheet Test Conditions 75 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 59. G.703 2.048 Mbps Pulse Mask Specifications Cable Parameter Unit TWP Coax Test load impedance 120 75 Ω Nominal peak mark voltage 3.0 2.37 V Nominal peak space voltage 0 ±0.30 0 ±0.237 V Nominal pulse width 244 244 ns Ratio of positive and negative pulse amplitudes at center of pulse 95-105 95-105 % Ratio of positive and negative pulse amplitudes at nominal half amplitude 95-105 95-105 % Figure 29. E1, G.703 Mask Templates Table 60. T1.102 1.544 Mbps Pulse Mask Specifications Cable Parameter Unit TWP Test load impedance 100 Ω Nominal peak mark voltage 3.0 V Nominal peak space voltage 0 ±0.15 V 324 ns 95-105 % Nominal pulse width Ratio of positive and negative pulse amplitudes 76 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 30. LXT3108 Jitter Tolerance Performance 1000 UI 7%' Jitter 100 UI 28 UI @ 4.9 Hz AT&T 62411, Dec 1990 (T1) 28 UI @ 300 Hz 18 UI @ 1.8 Hz 10 UI GR-499-CORE, Dec 1995 (T1) 5 UI @ 500 Hz ITU G.823, Mar 1993 (E1) 0.4 UI @ 10 kHz 1 UI 1.5 UI @ 2.4 kHz 1.5 UI @ 20 Hz .1 UI 1 Hz Datasheet 0.2 UI @ 18 kHz 0.1 UI @ 8 kHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 77 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 31. LXT3108 Jitter Transfer Performance 10 dB ITU G.736 Template E1 0.5 dB @ 3Hz 0 dB 0.5 dB @ 40Hz Gain -10 dB -19.5 dB @ 20 kHz -20 dB -19.5 dB @ 400 Hz -30 dB -40 dB -60 dB 1 Hz T1 10 Hz 100 Hz 1 kHz Frequency 10 dB 0 dB @ 1 Hz 0 dB @ 20 Hz 0.1 dB @ 20 Hz 0.5 dB @ 350 Hz 0 dB -10 dB Gain 10 kHz 100 kHz AT&T Pub 62411 GR-253-CORE TR-TSY-000009 -6 dB @ 2 Hz -20 dB -33.3 dB @ 1 kHz -33.7 dB @ 2.5kHz -30 dB -40 dB @ 1.4 kHz -40 dB @ 70 kHz -40 dB -49.2 dB @ 15kHz -60 dB @ 57 kHz -60 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency 78 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 16.1 Microprocessor Interface Timing Diagrams Figure 32. MPC860 Write Timing clk (ALE_AS) Tadrs Tadrh ADR (AD) Tadsh Tadss TS# (DS) Trws Trwh R/W# (RD_WR) Tcss Trwh CS# (CS) Tdh Tds Data (D(7:0)) Trdys Trdyh TA# (RDY_ACK) Table 61. MPC860 Write Timing Characteristics Symbol Min. Max Unit Address setup to clock 15 -- ns Tadrh Address hold from clock 13 -- ns Tadss TS# setup to clock 6 -- ns Tadsh TS# hold from clock 2 -- ns Trws R/W# setup to clock 10 -- ns Tcss CS# setup to clock TBD -- ns Trwh R/W# and CS# hold from clock 0 -- ns Tds Data setup to clock 7 -- ns Tdh Data hold from clock 16 -- ns Trdys clock to TA# asserted 13 16 ns Trdyh clock to TA# deasserted 13 16 ns Tadrs Datasheet Parameter 79 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 33. MPC860 Read Timing clk (ALE_AS) Tadrh Tadrs ADR (AD) Tadsh Tadss ADS# (DS) Trwsr Trwh W/R# (RD_WR) Tcss Trwh CS# (CS) Tdhwr Tdhcs Tdd Data (D(7:0)) Trdys Trdyh RDY# (RDY_ACK) Table 62. MPC860 Read Timing Characteristics Symbol Min. Max Unit Address setup to clock 10 -- ns Tadrhr Address hold from clock 10 -- ns Tadss TS# setup to clock 6 -- ns Tadsh TS# hold from clock 2 -- ns Trwsr R/W# setup to clock 8 -- ns Tcss CS# setup to clock TBD -- ns Trwh R/W#, CS hold to clock 0 -- ns Tdd clock to data valid -- 41 ns Tdhwr Data hold from R/W# 18 27 ns Tdhcs Data hold from CS# 16 24 ns Trdys clock to TA# asserted 13 16 ns Trdyh clock to TA# deasserted 13 16 ns Tadrsr 80 Parameter Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 34. M68302 Write Timing ADR (AD) CS# (CS) R/W# (RW) Tdsmin Trdss Tcsdss Tadss Tcsdsh Trdsh Tadsh LDS# (DS) Tdsds Tdssh Data (DB) Trdyh DTACK (RDY) Table 63. M68302 Write Timing Characteristics Datasheet Symbol Parameter Min. Max Unit Tadss Address setup to LDS asserted -8 -- ns Tadsh Address hold from LDS asserted 44 -- ns Trdss R/W# setup to LDS asserted (-14) 0 -- ns Trdsh R/W# hold from LDS asserted 41 -- ns Tddss Data setup to LDS asserted -17 -- ns Tddsh Data hold from LDS asserted 46 -- ns Tdsmin LDS minimum width 60 -- ns Tdstas LDS asserted to DTACK valid 18 -- ns Tdsrdh LDS desserted to DTACK invalid 19 -- ns Tcsdss CS to DS setup 3 -- ns Tcsdsh CS to DS hold 4 -- ns 81 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 35. M68302 Read Timing ADR (AD) CS# (CS) R/W# (RW) Trdss Tadss Tdsmin Trdsh Tadsh LDS# (DS) Tdsdd Tdsdh Data (DB) Tdtds DTACK (RDY) Table 64. M68302 Read Timing Characteristics Symbol 82 Parameter Min. Max Unit Tadss Address setup to LDS asserted 23.77 -- ns Tadsh Address hold from LDS assserted (41) 0 -- ns Trdss R/W# setup to LDS asserted (-11) 0 -- ns Trdsh R/W# hold from LDS asserted (38) 0 -- ns Tdsdd LDS low to data valid -- 71 ns Tdsdh Data hold from LDS deasserted 17 -- ns Tdsmin LDS minimum width 71 -- ns Tdtds DTACK to data valid 39 -- ns Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 36. i486/i960 Nonmuxed Mode Write Timing CLK (MPI_CLK) Tadrh Tadrs ADR (AD) Tadsh Tadss ADS# (DS) Trws Trwh W/R# (RW) Trws Trwh CS# (CS) Tdh Tds Data (D(7:0)) Trdyh Trdys RDY# (RDY) Figure 37. i960 Muxed Mode Write Timing CLK (MPI_CLK) Tadrh Tadrs Tdh Tds AD (AD) Tadsh Tadss ADS# (DS) Trws Trwh W/R# (RW) Trws Trwh CS# (CS) Trdys Trdyh RDY# (RDY) Datasheet 83 LXT3108 — Octal T1/E1/J1 LH/SH LIU Table 65. i486/i960 Write Timing Characteristics Symbol Parameter Min. Max Unit Tadrs Address setup to clock 7 -- ns Tadrh Address hold from clock 5 -- ns Tadss ADS setup to clock 6 -- ns Tadsh ADS hold from clock 2 -- ns Trws W/R# and CS# setup to clock 10 -- ns Trwh W/R# and CS# hold from clock 0 -- ns Tds Data setup to clock 7 -- ns Tdh Data hold from clock 16 -- ns Trdys clock to READY# asserted 13 16 ns Trdyh clock to READY# deasserted 13 16 ns Figure 38. i486/i960 Nonmuxed Mode Read Timing CLK (MPI_CLK) Tadrh Tadrs ADR (AD) Tadsh Tadss ADS# (DS) Trwsr Trwh W/R# (RW) Trwsr Trwh CS# (CS) Tdhwr Tdd Tdhcs Data (D(7:0)) Trdys Trdyh RDY# (RDY) 84 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 39. i960 Muxed Mode Read Timing CLK (MPI_CLK) Tadrh Tadrs Tdd AD (AD) Tadsh Tadss ADS# (DS) Tdhwr Trwh Trwsr W/R# (RW) Tdhcs Trwsr Trwh CS# (CS) Trdys Trdyh RDY# (RDY) Table 66. i486/i960 Read Timing Characteristics Datasheet Symbol Parameter Min. Max Unit Tadrs Address setup to clock 7 -- ns Tadrh Address hold from clock 5 -- ns Tadss ADS setup to clock 6 -- ns Tadsh ADS hold from clock 2 -- ns Trwsr W/R# and CS setup to clock 8 -- ns Trwh W/R# and CS hold from clock 0 -- ns Tdd clock to Data valid -- 41 ns Tdhwr Data hold from R/W# 18 27 ns Tdhcs Data hold from CS# 16 24 ns Trdys clock to READY# asserted 13 16 ns Trdyh clock to READY# deasserted 13 16 ns 85 LXT3108 — Octal T1/E1/J1 LH/SH LIU 16.2 Referenced Standards AT&T Pub 62411 Accunet T1.5 Service Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria Bellcore GR-499-CORE Transport Systems Generic Requirements ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 -1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring ETSI CTR12/13 Business TeleCommunications (BTC): 2048 Kbps Digital Unstructured/ Structured Leased Line. ETS 300166 Physical and Electrical Characteristics G.703 Physical/electrical characteristics of hierarchical digital interfaces G.735 Characteristics of Primary PCM multiplex equipment operating at 2048 kbps and offering digital access at 384 kbps and/or synchronous digital access at 64 kbps G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbps G.742 General Aspects of Digital Transmission Systems G.772 Protected Monitoring Points provided on Digital Transmission Systems G.775 Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks G.823 The control of jitter and wander within digital networks which are based on the 2048 kbps hierarchy O.161 In - service code violations monitors for digital systems. Blue Book Fasc.IV.4 BAPT220 Short Circuit Current Requirements ITU I.431Primary Rate ISDN User-Network Interface - Layer 1 ETS 300 233Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate. 86 Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 17.0 Mechanical Specification Figure 40. LXT3108 256 PBGA Mechanical Specification 17.00 ±0.10 7.00 REF 1.00 REF 15.00 PIN #A1 CORNER 1.00 PIN #A1 CORNER A PIN #A1 ID 0.50 B C D 7.00 REF 1.00 E F 17.00 ±0.10 G H 15.00 ±0.05 J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1.00 REF TOP VIEW BOTTOM VIEW 0.70 1.80 ±0.05 MAX NOTE: 1. ALL DIMENSIONS IN MILLIMETERS. SEATING PLANE SIDE VIEW Datasheet 0.35 0.56 MIN ± 0.04 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994. 3. TOLERANCE = ± 0.05 UNLESS SPECIFIED OTHERWISE. 87 LXT3108 — Octal T1/E1/J1 LH/SH LIU Figure 41. LXT3108 208 Pin QFP Mechanical Specifications Millimeters Dim D Min Max A - 4.10 A1 0.25 - A2 3.20 3.60 b 0.17 0.27 D 30.30 30.90 D1 27.70 28.30 E 30.30 30.90 E1 27.70 28.30 D1 e E1 E e /2 e L θ2 A2 A θ A1 88 0.50 L1 L1 θ3 L .50 BASIC 0.75 1.30 REF θ1 0° 7° θ2 5° 16° θ3 5° 16° b Datasheet LXT3108 — Octal T1/E1/J1 LH/SH LIU 18.0 Glossary Term Categories Datasheet Term Term definition ADC AFE AGC ATWG BPV BSR BYR CLAD DAC DJA DSP FIR GUI HPS IADs IDR IMAPs IR JTAG LIU LH LH/SH LOS NRZ PBGA POR PPR PPRB PPS PTM QFP SH TBD TAOS UI Analog to Digital Converter Analog Front End Automatic Gain Control Arbitrary Transmit Wave Generation Bi-Polar Violation Boundary Scan Register BYpass Register CLock ADapter Digital to Analog Converter Digital Jitter Attenuator Digital Signal Processor Finite Infinite Response Graphical User Interface Intel® Hitless Protection Switching, Intel® HPS Integrated Access Devices Device Identification Register Integrated Multi-service Access Platforms Instruction Register Joint Test Action Group Line Interface Unit Long Haul Long Haul/Short Haul Loss Of Signal Non-Return-to-Zero Plastic Ball Grid Array Power On Reset Port Page Register Port Page Register Bank Port Page Select Intel® Pulse Template Matching, Intel® PTM Quad Flat Pack Short Haul To Be Determined Transmit All Ones Unit Interval 89