STMICROELECTRONICS M41T63Q6F

M41T62, M41T63
M41T64, M41T65
Serial real-time clocks with alarm
Features
■
Serial RTC with alarm functions
– 400 kHz I2C serial interface
– Memory mapped registers for seconds,
minutes, hours, day, date, month, year, and
century
– Tenths/hundredths of seconds register
■
350 nA timekeeping current at 3 V
■
Timekeeping down to 1.0 V
■
1.3 V to 4.4 V I2C bus operating voltage
– 4.4 V max VCC suitable for lithium-ion
battery operation
■
Low operating current of 35 µA (at 400 kHz)
■
32 KHz square wave output is on at power-up.
Suitable for driving a microcontroller in lowpower mode. Can be disabled.
(M41T62/63/64)
3mm
3mm
QFN16 (Q)
3 mm x 3 mm
■
Programmable 1 Hz to 32 KHz square wave
output (M41T62/63/64)
■
Programmable alarm with interrupt function
(M41T62/65)
■
32 KHz crystal oscillator integrates crystal load
capacitors, works with high series resistance
crystals
■
Accurate programmable watchdog
– 62.5 ms to 31 min timeout
■
Software clock calibration. Can adjust
timekeeping to within ±2 parts per million (±5
seconds per month)
■
Automatic leap year compensation
■
–40 to +85 °C operation
■
Very small 3 mm x 3 mm, Lead-free
16-lead QFN
■
Oscillator stop detection monitors clock
operation
Table 1.
Device summary
Basic RTC
Alarms
OSC fail
detect
M41T62
✔
✔
✔
✔
M41T63
✔
✔
✔
M41T64
✔
✔
M41T65
✔
✔
May 2010
Watchdog
Calibration
timer
SQW
output
IRQ
output
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Doc ID 10397 Rev 14
WDO
output
F32K
output
✔
✔
✔
✔
1/41
www.st.com
1
Contents
M41T62/63/64/65
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3
Setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5
Watchdog output (WDO - M41T63/65 only) . . . . . . . . . . . . . . . . . . . . . . . 27
3.6
Square wave output (M41T62/63/64) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7
Full-time 32 KHz square wave output (M41T64) . . . . . . . . . . . . . . . . . . . 28
3.8
Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.9
Output driver pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.10
Oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.11
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/41
Doc ID 10397 Rev 14
M41T62/63/64/65
8
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Doc ID 10397 Rev 14
3/41
List of tables
M41T62/63/64/65
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
4/41
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M41T62 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
M41T63 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
M41T64 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M41T65 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Crystals suitable for use with M41T6x series RTCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, mechanical data . . . 37
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Doc ID 10397 Rev 14
M41T62/63/64/65
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
M41T63 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
M41T64 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M41T65 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M41T62 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M41T63 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M41T64 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M41T65 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M41T62 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M41T63 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M41T64 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M41T65 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Hardware hookup for SuperCap™ backup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Buffer/transfer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 37
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 38
Doc ID 10397 Rev 14
5/41
Description
1
M41T62/63/64/65
Description
The M41T6x serial access TIMEKEEPER® is a low power serial RTC with a built-in
32.768 kHz oscillator. Eight registers are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format. An additional 8 registers provide
status/control of alarm, 32 KHz output, calibration, and watchdog functions. Addresses and
data are transferred serially via a two line, bi-directional I2C interface. The built-in address
register is incremented automatically after each WRITE or READ data byte.
Functions available to the user include a time-of-day clock/calendar, alarm interrupts
(M41T62/65), 32 KHz output (M41T62/63/64), programmable square wave output
(M41T62/63/64), and watchdog output (M41T63/65). The eight clock address locations
contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a
second in 24 hour BCD format. Corrections for 28-, 29- (leap year), 30- and 31-day months
are made automatically.
The M41T6x is supplied in a tiny, 3 mm x 3 mm 16-pin QFN which requires a user-supplied
32 KHz crystal.
Figure 1.
M41T62 logic diagram
VCC
XI
IRQ/OUT(1)
XO
M41T62
(2)
SCL
SQW
SDA
VSS
AI09103
1. Open drain.
2. Defaults to 32 KHz on power-up.
Figure 2.
M41T63 logic diagram
VCC
XI
(1)
XO
WDO
M41T63
SCL
SQW(2)
SDA
VSS
1. Open drain.
2. Defaults to 32 KHz on power-up.
6/41
Doc ID 10397 Rev 14
AI09189
M41T62/63/64/65
Figure 3.
Description
M41T64 logic diagram
VCC
XI
SQW(1)
XO
M41T64
F32K(2)
SCL
SDA
VSS
AI09108
1. Open drain.
2. Defaults to 32 KHz on power-up.
Figure 4.
M41T65 logic diagram
VCC
XI
(1)
XO
WDO
M41T65
IRQ/FT/OUT(1)
SCL
SDA
VSS
AI09109
1. Open drain.
2
VSS
3
(1)
4
SQW
NC
VCC
NC
14
13
QFN
5
6
7
8
NC
XO
15
NC
1
16
NC
XI
NC
M41T62 connections
VSS
Figure 5.
12
NC
11
IRQ/OUT(2)
10
SCL
9
SDA
AI09100
1. SQW output defaults to 32 KHz upon power-up.
2. Open drain.
Doc ID 10397 Rev 14
7/41
Description
M41T62/63/64/65
NC
NC
VCC
NC
M41T63 connections
16
15
14
13
NC
XO
2
11
WDO
VSS
3
10
SCL
SQW(1)
4
9
SDA
5
6
7
8
NC
12
NC
1
NC
XI
VSS
Figure 6.
(2)
AI09190
1. SQW output defaults to 32 KHz upon power-up.
2. Open drain.
NC
NC
VCC
NC
M41T64 connections
16
15
14
13
NC
XO
2
11
SQW(2)
VSS
3
10
SCL
F32K(1)
4
9
SDA
5
6
7
8
NC
12
NC
1
NC
XI
VSS
Figure 7.
AI09101
1. Enabled on power-up.
2. Open drain.
NC
NC
VCC
NC
M41T65 connections
16
15
14
13
NC
XO
2
11
IRQ/FT/OUT
VSS
3
10
SCL
(1)
4
9
SDA
WDO
5
6
7
8
NC
12
NC
1
NC
XI
VSS
Figure 8.
1. Open drain.
8/41
Doc ID 10397 Rev 14
(1)
AI09102
M41T62/63/64/65
Description
Table 2.
Signal names
XI
Oscillator input
XO
Oscillator output
SDA
Serial data input/output
SCL
Serial clock input
Interrupt or OUT output (open drain)
IRQ/OUT
IRQ/FT/OUT
Interrupt, frequency test, or OUT output (open drain)
SQW
Programmable square wave - defaults to 32 KHz on power-up (open drain for
M41T64 only)
F32K
Dedicated 32 KHz output (M41T64 only)
WDO
Watchdog timer output (open drain)
VCC
Supply voltage
VSS
Ground
Figure 9.
M41T62 block diagram
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL OFIE
DETECT
RTC W/ALARM
SDA
I2C
INTERFACE
SCL
AFE
IRQ/OUT(1)
WATCHDOG
SQUARE WAVE
SQWE
(2)
SQW
AI08899a
1. Open drain.
2. Defaults to 32 KHz on power-up.
Figure 10. M41T63 block diagram
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL
DETECT
RTC W/ALARM
SDA
I2C
INTERFACE
SCL
WDO(1)
WATCHDOG
SQUARE WAVE
SQWE
SQW(2)
AI09191
1. Open drain.
2. Defaults to 32 KHz on power-up.
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9/41
Description
M41T62/63/64/65
Figure 11. M41T64 block diagram
32KE
(1)
F32K
REAL TIME CLOCK
CALENDAR
XTAL
OSCILLATOR FAIL
DETECT
32KHz
OSCILLATOR
RTC W/ALARM
SDA
WATCHDOG
I2C
INTERFACE
SQUARE WAVE
SCL
SQWE
SQW(2)
AI09192
1. Defaults enabled on power-up.
2. Open drain.
Figure 12. M41T65 block diagram
REAL TIME CLOCK
CALENDAR
XTAL
32KHz
OSCILLATOR
OSCILLATOR FAIL OFIE
DETECT
FT
RTC W/ALARM
SDA
I2C
INTERFACE
WATCHDOG
AFE
IRQ/FT/OUT(1)
(1)
WDO
SCL
AI09193
1. Open drain.
10/41
Doc ID 10397 Rev 14
M41T62/63/64/65
Description
Figure 13. Hardware hookup for SuperCap™ backup operation
VCC
(1)
MCU
M41T6x
VCC
XI
XO
VSS
VCC
(2)
IRQ/FT/OUT
(3)
WDO
(4)
SQW
Port
Reset Input
SQWIN
SCL
Serial Clock Line
SDA
Serial Data Line
F32K
32KHz CLKIN
AI10400b
1. Diode required on open drain pin (M41T65 only) for SuperCap (or battery) backup. Low threshold BAT42
diode recommended.
2. For M41T62 and M41T65 (open drain).
3. For M41T63 and M41T65 (open drain).
4. For M41T64 (open drain).
Doc ID 10397 Rev 14
11/41
Operation
2
M41T62/63/64/65
Operation
The M41T6x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 16 bytes
contained in the device can then be accessed sequentially in the following order:
2.1
●
1st byte: tenths/hundredths of a second register
●
2nd byte: seconds register
●
3rd byte: minutes register
●
4th byte: hours register
●
5th byte: square wave/day register
●
6th byte: date register
●
7th byte: century/month register
●
8th byte: year register
●
9th byte: calibration register
●
10th byte: watchdog register
●
11th - 15th bytes: alarm registers
●
16th byte: flags register
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
12/41
Doc ID 10397 Rev 14
M41T62/63/64/65
2.1.4
Operation
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 14. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Doc ID 10397 Rev 14
13/41
Operation
M41T62/63/64/65
Figure 15. Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
1
DATA OUTPUT
BY TRANSMITTER
2
8
MSB
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
2.2
READ mode
In this mode the master reads the M41T6x slave after setting the slave address (see
Figure 17 on page 15). Following the WRITE mode control bit (R/W=0) and the
acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ mode control bit
(R/W=1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an acknowledge
bit to the slave transmitter. the address pointer is only incremented on reception of an
acknowledge clock. The M41T6x slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume due to a stop condition or when the
pointer increments to any non-clock address (08h-0Fh).
Note:
This is true both in READ mode and WRITE mode.
An alternate READ mode may also be implemented whereby the master reads the M41T6x
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 18 on page 15).
Figure 16. Slave address location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
14/41
Doc ID 10397 Rev 14
M41T62/63/64/65
Operation
DATA n+1
SLAVE
ADDRESS
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 17. READ mode sequence
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
AI00899
STOP
P
NO ACK
SLAVE
ADDRESS
DATA n+X
ACK
BUS ACTIVITY:
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
START
Figure 18. Alternative READ mode sequence
AI00895
Doc ID 10397 Rev 14
15/41
Operation
2.3
M41T62/63/64/65
WRITE mode
In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is
shown in Figure 19 on page 16. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T6x slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see Figure 16 on page 14 and again after it has received the word address and each data
byte.
STOP
SLAVE
ADDRESS
16/41
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 19. WRITE mode sequence
AI00591
Doc ID 10397 Rev 14
M41T62/63/64/65
3
Clock operation
Clock operation
The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of
32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The eight byte clock register (see Table 3: M41T62 register map, Table 4: M41T63 register
map, Table 5: M41T64 register map, and Table 6: M41T65 register map) is used to both set
the clock and to read the date and time from the clock, in a binary coded decimal format.
Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to
“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and
07h contain the date (day of month), month, and years. The ninth clock register is the
calibration register (this is described in the clock calibration section). Bit D7 of register 01h
contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When
reset to a '0' the oscillator restarts within one second (typical).
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bit D7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (OFIE).
When the user sets this bit to '1,' any condition which sets the oscillator fail bit (OF) (see
Oscillator stop detection on page 29) will also generate an interrupt output.
Bits D6 and D7 of clock register 06h (century/month register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1).
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the OFIE bit, RS0-RS3 bit, and CB0-CB1 bits will result in an update of the system
clock and a reset of the divider chain. This could result in an inadvertent change of the
current time. These non-clock related bits should be written prior to setting the clock, and
remain unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Doc ID 10397 Rev 14
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Clock operation
3.1
M41T62/63/64/65
RTC registers
The M41T6x user interface is comprised of 16 memory mapped registers which include
clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock
counters are accessed indirectly via a set of buffer/transfer registers while the other eight
registers are directly accessed. Data in the clock and alarm registers is in BCD format.
Figure 20. Buffer/transfer registers
CLOCK COUNTERS ARE
ACCESSED INDIRECTLY
THRU BUFFER/TRANSFER
REGISTERS
AT START OF READ, UDATES FROM COUNTERS
ARE HALTED AND PRESENT TIME IS FROZEN
IN BUFFER/TRANSFER REGISTERS.
32KHz
OSC
DIVIDE BY
32768
1 Hz
READ / WRITE
BUFFER
TRANSFER
REGISTERS
I2C
2
COUNTER
COUNTER
SECONDS
MINUTES
HOURS
DAY-OF-WEEK
DATE
MONTHS
YEARS
CENTURIES
I2C
INTERFACE
NON-CLOCK
REGISTERS
DATA TRANSFERRED
OUT OF I2C INTERFACE
ON 8th FALLING EDGE
OF SCL (ON WRITES)
CALIBRATION
WATCHDOG
FLAGS
NON-CLOCK REGISTERS
ARE DIRECTLY ACCESSED
COUNTER
COUNTER
COUNTER
COUNTER
COUNTER
COUNTER
ON WRITES, DATA TRANSFERRED
FROM BUFFERS TO COUNTERS
WHEN ADDRESS POINTER
INCREMENTS TO 8 OR WHEN I2C
STOP CONDITION IS RECEIVED
AM04890v1
Updates
During normal operation when the user is not accessing the device, the buffer/transfer
registers are kept updated with a copy of the RTC counters. At the start of an I2C read or
write cycle, the updating is halted and the present time is frozen in the buffer/transfer
registers.
Reads of the clock registers
By halting the updates at the start of an I2C access, the user is ensured that all the data
transferred out during a read sequence comes from the same instant in time.
18/41
Doc ID 10397 Rev 14
M41T62/63/64/65
Clock operation
Write timing
When writing to the device, the data is shifted into the M41T62's I2C interface on the rising
edge of the SCL signal. As shown in Figure 20, on the 8th clock cycle, the data is
transferred from the I2C block into whichever register is being pointed to by the address
pointer (not shown).
Writes to the clock registers (addresses 0-7)
Data written to the clock registers (addresses 0-7) is held in the buffer registers until the
address pointer increments to 8, or an I2C stop condition occurs, at which time the data in
the buffer/registers is simultaneously copied into the counters, and then the clock is restarted.
Doc ID 10397 Rev 14
19/41
Clock operation
M41T62/63/64/65
Table 3.
M41T62 register map
Addr
D7
00h
D6
D5
D4
D3
0.1 seconds
D2
D0
0.01 seconds
10ths/100ths
of seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
OFIE
10 minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24-hour format)
Hours
00-23
04h
RS3
RS2
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
CB1
CB0
Month
Century/
month
0-3/01-12
Year
Year
00-99
07h
10 hours
RS1
RS0
0
10 date
0
Day of week
10M
10 years
08h
OUT
0
S
Calibration
09h
RB2
BMB4
BMB3
BMB2
0Ah
AFE
SQWE
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
BMB1 BMB0
Calibration
RB1
RB0
Watchdog
Alarm month
Al month
01-12
AI 10 date
Alarm date
Al date
01-31
AI 10 hour
Alarm hour
Al hour
00-23
Alarm 10 minutes
Alarm minutes
Al min
00-59
Alarm 10 seconds
Alarm seconds
Al sec
00-59
AF
0
0
0
OF
Keys:
0 = must be set to '0'
AF = alarm flag (read only)
AFE = alarm flag enable flag
BMB0 - BMB4 = watchdog multiplier bits
CB0-CB1 = century bits
OF = oscillator fail bit
OFIE = oscillator fail interrupt enable bit
OUT = output level
RB0 - RB2 = watchdog resolution bits
RPT1-RPT5 = alarm repeat mode bits
RS0-RS3 = SQW frequency bits
S = sign bit
SQWE = square wave enable bit
ST = stop bit
WDF = watchdog flag bit (read only)
20/41
D1
Function/range BCD
format
Doc ID 10397 Rev 14
0
0
Flags
M41T62/63/64/65
Clock operation
Table 4.
M41T63 register map
Addr
D7
00h
D6
D5
D4
D3
0.1 seconds
D2
D1
D0
Function/range BCD
format
0.01 seconds
10ths/100ths
of seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
0
10 minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24-hour format)
Hours
00-23
04h
RS3
RS2
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
CB1
CB0
Month
Century/
month
0-3/01-12
Year
Year
00-99
07h
10 hours
RS1
RS0
0
10 date
0
Day of week
10M
10 years
08h
0
09h
RB2
0Ah
0
S
Calibration
BMB4 BMB3
BMB2
0
SQWE
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
BMB1 BMB0
Calibration
RB1
RB0
Watchdog
Alarm month
Al Month
01-12
AI 10 date
Alarm date
Al date
01-31
AI 10 hour
Alarm hour
Al hour
00-23
Alarm 10 minutes
Alarm minutes
Al min
00-59
Alarm 10 seconds
Alarm seconds
Al sec
00-59
AF
0
0
0
OF
0
0
Flags
Keys:
0 = must be set to '0'
AF = alarm flag (read only)
BMB0 - BMB4 = watchdog multiplier bits
CB0-CB1 = century bits
OF = oscillator fail bit
RB0 - RB2 = watchdog resolution bits
RPT1-RPT5 = alarm repeat mode bits
RS0-RS3 = SQW frequency bits
S = sign bit
SQWE = square wave enable bit
ST = stop bit
WDF = watchdog flag bit (read only)
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Clock operation
M41T62/63/64/65
Table 5.
M41T64 register map
Addr
D7
D6
00h
D5
D4
D3
0.1 seconds
D2
D0
0.01 seconds
10ths/100ths
of seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
0
10 minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24-hour format)
Hours
00-23
04h
RS3
RS2
Day of week
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
CB1
CB0
Month
Century/
month
0-3/01-12
Year
Year
00-99
07h
10 hours
RS1
RS0
0
10 Date
0
10M
10 years
08h
0
0
S
09h
RB2
BMB4
BMB3
0Ah
0
SQWE
32KE Al 10M
Alarm month
Al month
01-12
0Bh
RPT4
RPT5
AI 10 date
Alarm date
Al date
01-31
0Ch
RPT3
0
AI 10 hour
Alarm hour
Al hour
00-23
0Dh
RPT2
Alarm 10 minutes
Alarm minutes
Al min
00-59
0Eh
RPT1
Alarm 10 seconds
Alarm seconds
Al sec
00-59
0Fh
WDF
AF
Calibration
BMB2 BMB1 BMB0
0
0
0
OF
Keys:
0 = must be set to '0'
32KE = 32 KHz enable bit
AF = alarm flag (read only)
BMB0 - BMB4 = watchdog multiplier bits
CB0-CB1 = century bits
OF = oscillator fail bit
RB0 - RB2 = watchdog resolution bits
RPT1-RPT5 = alarm repeat mode bits
RS0-RS3 = SQW frequency bits
S = sign bit
SQWE = square wave enable bit
ST = stop bit
WDF = watchdog flag bit (read only)
22/41
D1
Function/range BCD
format
Doc ID 10397 Rev 14
Calibration
RB1
0
RB0
0
Watchdog
Flags
M41T62/63/64/65
Clock operation
Table 6.
M41T65 register map
Addr
D7
D6
00h
D5
D4
D3
0.1 seconds
D2
D1
D0
Function/range BCD
format
0.01 seconds
10ths/100ths
of seconds
00-99
01h
ST
10 seconds
Seconds
Seconds
00-59
02h
OFIE
10 minutes
Minutes
Minutes
00-59
03h
0
0
Hours (24-hour format)
Hours
00-23
04h
0
0
Day of week
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
CB1
CB0
Month
Century/
month
0-3/01-12
Year
Year
00-99
07h
10 hours
0
0
0
10 date
0
10M
10 years
08h
OUT
FT
S
Calibration
09h
RB2
BMB4
BMB3
BMB2
0Ah
AFE
0
0
Al 10M
0Bh
RPT4
RPT5
0Ch
RPT3
0
0Dh
RPT2
0Eh
RPT1
0Fh
WDF
BMB1 BMB0
Calibration
RB1
RB0
Watchdog
Alarm month
Al month
01-12
AI 10 date
Alarm date
Al date
01-31
AI 10 hour
Alarm hour
Al hour
00-23
Alarm 10 minutes
Alarm minutes
Al min
00-59
Alarm 10 seconds
Alarm seconds
Al sec
00-59
AF
0
0
0
OF
0
0
Flags
Keys:
0 = must be set to '0'
AF = alarm flag (read only)
AFE = alarm flag enable flag
BMB0 - BMB4 = watchdog multiplier bits
CB0-CB1 = century bits
FT = frequency test bit
OF = oscillator fail bit
OFIE = oscillator fail interrupt enable bit
OUT = output level
RB0 - RB2 = watchdog resolution bits
RPT1-RPT5 = alarm repeat mode bits
S = sign bit
ST = stop bit
WDF = watchdog flag bit (read only)
Doc ID 10397 Rev 14
23/41
Clock operation
3.2
M41T62/63/64/65
Calibrating the clock
The M41T6x real-time clock is driven by a quartz controlled oscillator with a nominal
frequency of 32,768 Hz. This provides the time-base for the RTC. The accuracy of the clock
depends on the frequency accuracy of the crystal, and the match between the capacitive
load of the oscillator circuit and the capacitive load for which the crystal was trimmed. The
M41T6x oscillator is designed for use with a 6 - 7 pF crystal load capacitance. When the
calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25 °C.
The oscillation rate of crystals changes with temperature (see Figure 21 on page 25).
Therefore, the M41T6x design employs periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as
shown in Figure 22 on page 25. The number of times pulses which are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into
the five calibration bits found in the calibration register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the calibration register (08h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register.
Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in
the calibration byte would represent +10.7 or –5.35 seconds per day which corresponds to a
total range of +5.5 or –2.75 minutes per month (see Figure 22 on page 25).
Two methods are available for ascertaining how much calibration a given M41T6x may
require:
●
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration
values, including the number of seconds lost or gained in a given period, can be found
in application note AN934, “TIMEKEEPER® calibration.” This allows the designer to
give the end user the ability to calibrate the clock as the environment requires, even if
the final product is packaged in a non-user serviceable enclosure. The designer could
provide a simple utility that accesses the calibration byte.
●
The second approach is better suited to a manufacturing environment, and involves the
use of either the SQW pin (M41T62/63/64) or the IRQ/FT/OUT pin (M41T65). The
SQW pin will toggle at 512 Hz when RS3 = '0,' RS2 = '1,' RS1 = '1,' RS0 = '0,' SQ
WE = '1,' and ST = '0.' Alternatively, for the M41T65, the IRQ/FT/OUT pin will toggle at
512 Hz when FT and OUT bits = '1' and ST = '0.'
Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test or square wave output frequency.
24/41
Doc ID 10397 Rev 14
M41T62/63/64/65
Clock operation
Figure 21. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
ΔF = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
Temperature °C
40
50
60
70
80
AI07888
Figure 22. Calibration waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594b
Doc ID 10397 Rev 14
25/41
Clock operation
3.3
M41T62/63/64/65
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go
off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every
year, month, day, hour, minute, or second. Bits RPT5–RPT1 put the alarm in the repeat
mode of operation. Table 7 on page 26 shows the possible configurations. Codes not listed
in the table default to the once per second mode to quickly alert the user of an incorrect
alarm setting.
When the clock information matches the alarm clock settings based on the match criteria
defined by RPT5–RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set
(M41T62/65), the alarm condition activates the IRQ/OUT or IRQ/FT/OUT pin. To disable the
alarm, write '0' to the alarm date register and to RPT5–RPT1.
Note:
If the address pointer is allowed to increment to the flag register address, an alarm condition
will not cause the interrupt/flag to occur until the address pointer is moved to a different
address. It should also be noted that if the last address written is the “Alarm Seconds,” the
address pointer will increment to the flag address, causing this situation to occur.
The IRQ output is cleared by a READ to the flags register as shown in Figure 23 on
page 26. A subsequent READ of the flags register is necessary to see that the value of the
alarm flag has been reset to '0.'
Figure 23. Alarm interrupt reset waveform
0Eh
Register address
0Fh
00h
ALARM FLAG BIT (AF)
HIGH-Z
IRQ/OUT or
IRQ/FT/OUT
Table 7.
26/41
AI08898
Alarm repeat modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
Doc ID 10397 Rev 14
M41T62/63/64/65
3.4
Clock operation
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the watchdog
register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the three bits RB2-RB0 select the resolution
where:
000=1/16 second (16 Hz);
001=1/4 second (4 Hz);
010=1 second (1 Hz);
011=4 seconds (1/4 Hz); and
100 = 1 minute (1/60 Hz).
Note:
Invalid combinations (101, 110, and 111) will NOT enable a watchdog time-out. Setting
BMB4-BMB0 = 00000 with any combination of RB2-RB0, other than 000, will result in an
immediate watchdog time-out.
The amount of time-out is then determined to be the multiplication of the five-bit multiplier
value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3
seconds). If the processor does not reset the timer within the specified period, the M41T6x
sets the WDF (watchdog flag) and generates an interrupt on the IRQ pin (M41T62), or a
watchdog output pulse (M41T63 and M41T65 only) on the WDO pin. The watchdog timer
can only be reset by having the microprocessor perform a WRITE of the watchdog register.
The time-out period then starts over.
Should the watchdog timer time-out, any value may be written to the watchdog register in
order to clear the IRQ pin. A value of 00h will disable the watchdog function until it is again
programmed to a new value. A READ of the flags register will reset the watchdog flag (bit
D7; register 0Fh). The watchdog function is automatically disabled upon power-up, and the
watchdog register is cleared.
Note:
A WRITE to any clock register will restart the watchdog timer.
3.5
Watchdog output (WDO - M41T63/65 only)
If the processor does not reset the watchdog timer within the specified period, the watchdog
output (WDO) will pulse low for trec (see Table 18 on page 35). This output may be
connected to the reset input of the processor in order to generate a processor reset. After a
watchdog time-out occurs, the timer will remain disabled until such time as a new
countdown value is written into the watchdog register.
Note:
The crystal oscillator must be running for the WDO pulse to be available.
The WDO output is an N-channel, open drain output driver (with IOL as specified in Table 14
on page 33).
Doc ID 10397 Rev 14
27/41
Clock operation
3.6
M41T62/63/64/65
Square wave output (M41T62/63/64)
The M41T62/63/64 offers the user a programmable square wave function which is output on
the SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency.
These frequencies are listed in Table 8. Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 0Ah.
The SQW output is an N-channel, open drain output driver for the M41T64, and a full CMOS
output driver for the M41T62/63. The initial power-up default for the SQW output is 32 KHz
(except for M41T64, which defaults disabled).
Table 8.
Square wave output frequency
Square wave bits
3.7
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
Full-time 32 KHz square wave output (M41T64)
The M41T64 offers the user a special 32 KHz square wave function which is enabled on
power-up to output on the F32K pin as long as VCC ≥ 1.3 V, and the oscillator is running
(ST bit = '0'). This function is available within one second (typ) of initial power-up and can
only be disabled by setting the 32KE bit to '0' or the ST bit to '1.' If not used, the F32K pin
should be disconnected and allowed to float.
28/41
Doc ID 10397 Rev 14
M41T62/63/64/65
3.8
Clock operation
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all
leap years correctly. See Table 10 on page 30 for additional explanation.
3.9
Output driver pin (M41T62/65)
When the OFIE bit, AFE bit, and watchdog register are not set to generate an interrupt, the
IRQ/OUT pin becomes an output driver that reflects the contents of D7 of the calibration
register. In other words, when D7 (OUT Bit) is a '0,' then the IRQ/OUT pin will be driven low.
Note:
The IRQ/OUT pin is an open drain which requires an external pull-up resistor.
3.10
Oscillator stop detection
If the oscillator fail (OF) bit is internally set to a '1,' this indicates that the oscillator has either
stopped, or was stopped for some period of time and can be used to judge the validity of the
clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator.
The following conditions can cause the OF bit to be set:
●
Note:
The first time power is applied (defaults to a '1' on power-up).
If the OF bit cannot be written to '0' four (4) seconds after the initial power-up, the STOP bit
(ST) should be written to a '1,' then immediately reset to '0.'
●
The voltage present on VCC or battery is insufficient to support oscillation.
●
The ST bit is set to '1.'
●
External interference of the crystal
If the oscillator fail interrupt enable bit (OFIE) is set to a '1,' the IRQ pin will also be activated.
The IRQ output is cleared by resetting the OFIE or OF bit to '0' (NOT by reading the flag
register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event
occurs during a power-down condition, this bit will be set correctly.
3.11
Initial power-on defaults
Upon application of power to the device, the register bits will initially power-on in the state
indicated in Table 9.
Doc ID 10397 Rev 14
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Clock operation
M41T62/63/64/65
Table 9.
Initial power-on default values
Condition
Device
Initial
power-up(1)
ST OF OFIE OUT FT AFE SQWE 32KE RS3-1 RS0 Watchdog
M41T62
0
1
0
M41T63
0
1
N/A
M41T64
0
1
N/A
M41T65
0
1
0
1
1
N/A
0
1
0
N/A N/A N/A
1
N/A
0
1
0
N/A N/A N/A
0
1
0
1
0
N/A
N/A
N/A
N/A
0
1
N/A
0
0
0
1. All other control bits power up in an undetermined state.
Table 10.
Century bits examples
CB0
CB1
Leap year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by
100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).
30/41
Doc ID 10397 Rev 14
M41T62/63/64/65
4
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 11.
Absolute maximum ratings
Sym
Parameter
Conditions(1)
Value(2)
Unit
TSTG
Storage temperature (VCC off, oscillator off)
–55 to 125
°C
VCC
Supply voltage
–0.3 to 5.0
V
260
°C
–0.2 to Vcc+0.3
V
TSLD(3)
VIO
Lead solder temperature for 10 seconds
Input or output voltages
IO
Output current
20
mA
PD
Power dissipation
1
W
VESD(HBM)
Electro-static discharge voltage
(human body model)
TA = 25 °C
>1500
V
VESD(RCDM)
Electro-static discharge voltage
(robotic charged device model)
TA = 25 °C
>1000
V
1. Test conforms to JEDEC standard.
2. Data based on characterization results, not tested in production.
3. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
Doc ID 10397 Rev 14
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DC and AC parameters
5
M41T62/63/64/65
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 12.
Operating and AC measurement conditions(1)
Parameter
M41T6x
Supply voltage (VCC)
1.3 V to 4.4 V
Ambient operating temperature (TA)
–40 to 85 °C
Load capacitance (CL)
50 pF
Input rise and fall times
≤ 5 ns
Input pulse voltages
0.2 VCC to 0.8 VCC
Input and output timing ref. voltages
0.3 VCC to 0.7 VCC
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 24. AC measurement I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 25. Crystal isolation example
Local Grounding Plane
(Layer 2)
XI
Crystal
XO
GND
AI09127
Note:
32/41
Substrate pad should be tied to VSS.
Doc ID 10397 Rev 14
M41T62/63/64/65
DC and AC parameters
Table 13.
Capacitance
Parameter(1)(2)
Symbol
CIN
COUT(3)
tLP
Min
Max
Unit
Input capacitance
-
7
pF
Output capacitance
-
10
pF
Low-pass filter input time constant (SDA and SCL)
-
50
ns
Max
Unit
1. Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested.
2. At 25°C, f = 1 MHz.
3. Outputs deselected.
Table 14.
Sym
VCC(2)
DC characteristics
Parameter
Operating voltage
Test condition(1)
Min
Clock
1.0
4.4
V
1.3
4.4
V
100
µA
70
µA
I2C
bus (400 kHz)
Typ
4.4 V
ICC1 Supply current
ICC2
Supply current
(standby)
SCL = 400 kHz
(no load)
3.6 V
50
3.0 V
35
µA
2.5 V
30
µA
2.0 V
20
µA
4.4 V
SCL = 0 Hz
3.6 V
all inputs
SQW off
≥ VCC – 0.2 V
3.0 V at 25 °C
≤ VSS + 0.2 V
2.0 V at 25 °C
375
950
nA
700
nA
350
nA
310
nA
VIL
Input low voltage
–0.2
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+0.3
V
VCC = 4.4 V, IOL = 3.0 mA
(CMOS or open drain)
0.4
V
VCC = 4.4 V, IOL = 1.0 mA
(SQW, WDO, IRQ)
0.4
V
VOL
Output low voltage
VOH Output high voltage
VCC = 4.4 V, IOH = –1.0 mA (push-pull)
2.4
V
Pull-up supply
voltage (open drain)
IRQ/OUT, IRQ/FT/OUT, WDO, SQW
(M41T64 only)
4.4
V
ILI
Input leakage current
0 V ≤ VIN ≤ VCC
±1
μA
ILO
Output leakage
current
0 V ≤ VOUT ≤ VCC
±1
μA
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.3 V to 4.4 V (except where noted).
2. Oscillator startup guaranteed at 1.5 V only.
Doc ID 10397 Rev 14
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DC and AC parameters
Table 15.
Crystal electrical characteristics
Parameter(1)(2)
Sym
fO
M41T62/63/64/65
Resonant frequency
Min
Typ
-
32.768
RS
Series resistance (TA = –40 to 70 °C, oscillator startup at 2.0 V)
-
CL
Load capacitance
-
Max
Units
kHz
75
(3)(4)
6
kΩ
pF
1. For the QFN16 package, user-supplied external crystals are required. The 6 and 7 pF crystals listed in Table 16 below
have been evaluated by ST and have been found to be satisfactory for use with the M41T6x series RTC.
2. Load capacitors are integrated within the M41T6x. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
4. RS (max) = 65 kΩ for TA = –40 to 85 °C and oscillator startup at 1.5 V.
Table 16.
Crystals suitable for use with M41T6x series RTCs
Manufacturer’s specifications
Vendor
Order number
Package
8.3 x 2.5 mm
leaded SMT
Citizen
CMJ206T-32.768KDZB-UB
Citizen
CM315-32.768KDZY-UB
Ecliptek
E4WCDA06-32.768K
2.0 x 6.0 mm thru-hole
Ecliptek
E5WSDC 07 - 32.768K
7 x 1.5 x 1.4 mm SMT
ECS
ESR
max
Rated
Rated
Temp.
tolerance load
range (°C)
at 25 °C
cap.
50 kΩ
–40/+85
±20 ppm
6 pF
3.2 x 1.5 x 0.9 mm SMT 70 kΩ
–40/+85
±20 ppm
7 pF
50 kΩ
–10/+60
±20 ppm
6 pF
65 kΩ
–40/+85
±20 ppm
7 pF
ECS-.327-6-17X-TR
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–10/+60
±20 ppm
6 pF
ECS
ECS-.327-7-34B-TR
3.2 x 1.5 x 0.9 mm SMT 70 kΩ
–40/+85
±20 ppm
7 pF
ECS
ECS-.327-7-38-TR
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Epson
MC-146 32.7680KA-AG: ROHS(1)
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Fox
298LF-0.032768-19
1.5 x 5.0 mm thru-hole
50 kΩ
–20/+60
±20 ppm
6 pF
Fox
299LF-0.032768-37
2.0 x 6.0 mm thru-hole
50 kΩ
–20/+60
±20 ppm
6 pF
Fox
414LF-0.032768-12
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–40/+85
±20 ppm
6 pF
Fox
501LF-0.032768-5
Micro
Crystal
MS3V-T1R 32.768KHZ 7PF 20PPM
Pletronics SM20S - 32.768K - 6pF
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
6.7 x 1.4 mm
leaded SMT
65 kΩ
–40/+85
±20 ppm
7 pF
3.8 x 8.5 x 2.5 mm SMT 50 kΩ
–40/+85
±20 ppm
6 pF
Seiko
SSPT7F-7PF20PPM
7 x 1.5 x 1.4 mm SMT
65 kΩ
–40/+85
±20 ppm
7 pF
Seiko
VT200F-6PF20PPM
2.0 x 6.0 mm thru-hole
50 kΩ
–10/+60
±20 ppm
6 pF
1. Epson MC-146 32.7680KA-E: ROHS is 6 pF version.
34/41
Doc ID 10397 Rev 14
M41T62/63/64/65
DC and AC parameters
Table 17.
Oscillator characteristics
Symbol
Parameter
VSTA
Oscillator start voltage
tSTA
Oscillator start time
Cg
XIN capacitance
Cd
XOUT capacitance
Conditions
Min
≤ 10 seconds
1.5
Typ
Max
V
VCC = 3.0 V
IC-to-IC frequency variation
(1)
Unit
1
s
12
pF
12
pF
–10
+10
ppm
1. Reference value. TA = 25 °C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by Citizen,
CL = Cg • Cd / (Cg + Cd).
Figure 26. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tF
tR
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
SR
tSU:STA
P
tSU:STO
AI00589
Table 18.
AC characteristics
Parameter(1)
Sym
Min
Max
Units
0
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT(2)
Data setup time
100
ns
tHD:DAT
Data hold time
0
µs
tSU:STO
STOP condition setup time
600
ns
tBUF
Time the bus must be free before a new
transmission can start
1.3
µs
trec
Watchdog output pulse width
96
98
ms
1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.3 to 4.4 V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Doc ID 10397 Rev 14
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Package mechanical information
6
M41T62/63/64/65
Package mechanical information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
36/41
Doc ID 10397 Rev 14
M41T62/63/64/65
Package mechanical information
Figure 27. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
Ch
E2
3
K
D2
QFN16-A
Note:
Drawing is not to scale.
Table 19.
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size,
mechanical data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
A
N
16
Doc ID 10397 Rev 14
16
37/41
Package mechanical information
M41T62/63/64/65
Figure 28. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended
footprint
1.60
3.55
2.0
0.28
AI09126
Note:
38/41
Dimensions shown are in millimeters (mm).
Doc ID 10397 Rev 14
M41T62/63/64/65
7
Part numbering
Part numbering
Table 20.
Ordering information scheme
Example:
M41T
62
Q
6
F
Device family
M41T
Device type and supply voltage
62 = VCC = 1.3 V to 4.4 V
63 = VCC = 1.3 V to 4.4 V
64 = VCC = 1.3 V to 4.4 V
65 = VCC = 1.3 V to 4.4 V
Package
Q = QFN16 (3 mm x 3 mm)
Temperature range
6 = –40 °C to 85 °C
Shipping method for SOIC
F = ECOPACK® package, tape & reel
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 10397 Rev 14
39/41
Revision history
8
M41T62/63/64/65
Revision history
Table 21.
40/41
Document revision history
Date
Revision
Changes
13-Nov-2003
1.0
First issue
19-Nov-2003
1.1
Add features, update characteristics (Figure 1, Figure 3, Figure 4,
Figure 9, Figure 23; Table 2, Table 3, Table 9, Table 11, Table 14,
Table 18)
25-Dec-2003
2
14-Jan-2004
2.1
Update characteristics (Figure 1, Figure 9, Figure 25; Table 1,
Table 3. Table 9, Table 14)
27-Feb-2004
2.2
Update characteristics and mechanical dimensions (Figure 1,
Figure 3, Figure 2, Figure 4, Figure 5, Figure 6, Figure 9,
Figure 10, Figure 11, Figure 12, Figure 27, Figure 28; Table 3,
Table 4, Table 5, Table 6, Table 9, Table 11, Table 14, Table 19)
02-Mar-2004
2.3
Update characteristics (Figure 7, Figure 8, Figure 11; Table 2,
Table 14)
26-Apr-2004
3
Reformat and republish
13-May-2004
4
Update characteristics (Figure 5, Figure 6, Figure 7, Figure 8,
Figure 25, Figure 28; Table 11, Table 14, Table 15)
06-Aug-2004
5
Correct diagrams; update characteristics (Figure 3, Figure 2,
Figure 25; Table 2, Table 14, Table 17)
11-Oct-2004
6
Update characteristics (Table 11, Table 14)
18-Jan-2005
7
Correct footprint dimensions; update characteristics (Figure 3,
Figure 7, Figure 11, Figure 13, Figure 28; Table 1, Table 2,
Table 5, Table 8, Table 9, Table 11, Table 12, Table 14, Table 15,
Table 17, Table 18)
05-May-2005
8
Add package comparison and mechanical data (in Feature
summary on page 1, Figure 28)
31-Oct-2005
9
Update: bus operating voltage, characteristics, add Lead-free text
(Figure 13; Table 11, Table 12, Table 14, Table 18, Table 20)
30-Nov-2005
10
Update ESD:HBM rating, crystal characteristics (Table 11,
Table 15)
22-Aug-2006
11
Changed document to new template; small text changes for
Feature summary on page 1
26-Jan-2010
12
Minor textual changes; updated Section 3.2; footnote 3 in
Table 11; footnote 1 in Table 15; text in Section 6; Table 16, 18.
07-May-2010
13
Updated title of datasheet, Features, Section 1, Section 3.1, 3.2,
3.4, 3.10, Section 4, Figure 23, Table 16; added Figure 20, added
embedded crystal package LCC8 (updated Figure 1, 5, 29,
Table 20)
25-May-2010
14
Removed LCC8 package option throughout document; removed
footnote from Table 14.
Reformatted; add crystal isolation, footprint (Figure 25)
Doc ID 10397 Rev 14
M41T62/63/64/65
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