To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI LSIs January 31, 2003 Rev.0.1 M5M5T5672TG – 25,22,20 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM DESCRIPTION The M5M5T5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5672TG operates on a single 2.5V power supply and are 2.5V CMOS compatible. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 2.5V –5% and +5% power supply VDD • Individual byte write (BWa# - BWh#) controls may be tied LOW • Single Read/Write control pin (W#) • Snooze mode (ZZ) for power down • Linear or Interleaved Burst Modes • JTAG boundary scan support FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the SRAM in the power-down state. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV Low input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. APPLICATION High-end networking products that require high bandwidth, such as switches and routers. PACKAGE M5M5T5672TG Bump Body Size Bump Pitch 209(11X19) bump BGA 14mm X 22mm 1mm PART NAME TABLE Part Name Frequency Access Cycle Active Current (max.) Standby Current (max.) M5M5T5672TG -25 250MHz 2.6ns 4.0ns 550mA 30mA M5M5T5672TG -22 225MHz 2.8ns 4.4ns 500mA 30mA M5M5T5672TG -20 200MHz 3.2ns 5.0ns 450mA 30mA 1/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM BUMP LAYOUT(TOP VIEW) 209 bump BGA 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A6 E2 A7 ADV A8 E3# A9 DQb DQb B DQg DQg BWc# BWg# NC W# A17 BWb# BWf# DQb DQb C DQg DQg BWh# BWd# NC E1# NC BWe# BWa# DQb DQb D DQg DQg VSS NC NC G# NC NC VSS DQb DQb E DQPg DQPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPf DQPb F DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf G DQc DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf H DQc DQc VSS VSS VSS NC VSS VSS VSS DQf DQf J DQc DQc VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQf DQf K NC NC CLK NC VSS CKE# VSS NC NC NC NC L DQh DQh VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS MCH VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa R DQPd DQPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPa DQPe T DQd DQd VSS NC NC LBO# NC NC VSS DQe DQe U DQd DQd NC A3 NC A15 NC A11 NC DQe DQe V DQd DQd A5 A4 A16 A1 A13 A12 A10 DQe DQe W DQd DQd TMS TDI A2 A0 A14 TDO TCK DQe DQe Note1. MCH means “Must Connect High”. MCH should be connected to HIGH. 2/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM BLOCK DIAGRAM VDD A0 A1 A2~17 VDDQ 18 18 16 ADDRESS REGISTER A1' A1 D1 LINEAR/ Q1 D0 INTERLEAVED BURST COUNTER Q0 A0 A0' LBO# CLK CKE# 18 WRITE ADDRESS REGISTER1 WRITE ADDRESS REGISTER2 18 ZZ ADV BYTE3 WRITE DRIVERS 256Kx36 MEMORY ARRAY BYTE4 WRITE DRIVERS BWe# BWf# BWg# BWh# W# G# BYTE2 WRITE DRIVERS OUTPUT BUFFERS AND DATA COHERENCY CONTROL LOGIC OUTPUT SELECT WRITE REGISTRY OUTPUT REGISTERS BWa# BWb# BWc# BWd# BYTE1 WRITE DRIVERS 72 INPUT INPUT REGISTER1 REGISTER0 DQa DQPa DQb DQPb DQc DQPc DQd DQPd DQe DQPe DQf DQPf DQg DQPg DQh DQPh READ LOGIC E1# E2 E3# VSS Note2. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter. Note3. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION and timing diagrams for detailed information. 3/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM PIN FUNCTION Pin Name A0~A17 Synchronous Address Inputs BWa#, BWb#, BWc#, BWd#, Bwe#, BWf#, BWg#, BWh# Synchronous Byte Write Enables CLK E1# E2 E3# Clock Input Synchronous Chip Enable Synchronous Chip Enable Synchronous Chip Enable CKE# Synchronous Clock Enable G# Output Enable ADV Synchronous Address Advance/Load Function These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address. BWs are associated with addresses and apply to subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc# controls DQc, DQPc pins; BWd# controls DQd, DQPd pins; BWe# controls DQe, DQPe pins; BWf# controls DQf, DQPf pins; BWg# controls DQg, DQPg pins; BWh# controls DQh, DQPh pins. This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This active HIGH input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active LOW input is used to enable the device and is sampled only when a new external address is loaded (ADV is LOW). This input can be used for memory depth expansion. This active LOW input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK. This active LOW asynchronous input enable the data I/O output drivers. When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. This active HIGH asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. When this pin is LOW or NC, the SRAM normally operates. This active input determines the cycle type when ADV is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. ZZ Snooze Enable W# Synchronous Read/Write DQa,DQPa,DQb,DQPb, DQc,DQPc,DQd,DQPd, DQe,DQPe,DQf,DQPf, DQg,DQPg,DQh,DQPh Synchronous Data I/O Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is DQd,DQPd pins; Byte “e” is DQe, DQPe pins; Byte “f” is DQf, DQPf pins; Byte “g” is DQg, DQPg pins; Byte “h” is DQh, DQPh pins. Input data must meet setup and hold times around CLK rising edge. Burst Mode Control This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input leak current to this pin. LBO# VDD VDD Core Power Supply VSS VSS Ground VDDQ I/O buffer Power supply VDDQ TDI Test Data Input TDO Test Data Output TCK Test Clock TMS Test Mode Select NC No Connect These pins are used for Boundary Scan Test. These pins are not internally connected and may be connected to ground. 4/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM DC OPERATED TRUTH TABLE Name Input Status Operation HIGH or NC LBO# Interleaved Burst Sequence LOW Linear Burst Sequence Note4. LBO# is DC operated pin. Note5. NC means No Connection. Note6. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence. BURST SEQUENCE TABLE (1) Interleaved Burst Sequence (when LBO# = HIGH or NC) Operation A17~A2 First access, latch external address A17~A2 A1,A0 0,0 0,1 1,0 1,1 Second access(first burst address) latched A17~A2 0,1 0,0 1,1 1,0 Third access(second burst address) latched A17~A2 1,0 1,1 0,0 0,1 Fourth access(third burst address) latched A17~A2 1,1 1,0 0,1 0,0 1,0 1,1 (2) Linear Burst Sequence (when LBO# = LOW) Operation A17~A2 First access, latch external address A17~A2 A1,A0 0,0 0,1 Second access(first burst address) latched A17~A2 0,1 1,0 1,1 0,0 Third access(second burst address) latched A17~A2 1,0 1,1 0,0 0,1 Fourth access(third burst address) latched A17~A2 Note7. The burst sequence wraps around to its initial state upon completion. 1,1 0,0 0,1 1,0 TRUTH TABLE E1# E2 E3# ADV W# BWx# G# CKE# ZZ# CLK Address used H X X X L X X X H L L L X X X X X X X X X L L L L L L L->H None L->H None L->H None Deselect Cycle Deselect Cycle Deselect Cycle Continue Deselect Cycle X X X H X X X L L L->H None L X L X H X H X L X L X L H L H H X H X X X X X L L H H L L L L L L L L L->H External L->H Next L->H External L->H Next L X L X H X H X L X L X L H L H L X L X L L H H X X X X L L L L L L L L L->H External L->H Next L->H None L->H Next X X X X X X X H L L->H Current Operation Read Cycle, Begin Burst Read Cycle, Continue Burst NOP/Dummy Read, Begin Burst Dummy Read, Continue Burst Write Cycle, Begin Burst Write Cycle, Continue Burst NOP/Write Abort, Begin Burst Write Abort, Continue Burst Ignore Clock edge, Stall H X None X X X X X X X X Snooze Mode Note8. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL. Note9. BWx#=H means all Synchronous Byte Write Enables (BWa#,BWb#,BWc#,BWd#) are HIGH. BWx#=L means one or more Synchronous Byte Write Enables are LOW. Note10. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM STATE DIAGRAM F,L,X Deselect F,L,X T,L,H T,L,L X,H,X Read Begin Burst T,L,H X,H,X T,L,H Write Begin Burst T,L,L T,L,H X,H,X X,H,X Read Continue Burst T,L,L Key F,L,X T,L,H T,L,L T,L,L Write Continue Burst X,H,X Input Command Code f Current State Transition Next State Note11. The notation "x , x , x" controlling the state transitions above indicate the state of inputs E, ADV and W# respectively. Note12. If (E1# = L and E2 = H and E3# = L) then E="T" else E="F". Note13. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL; “T” = input “true”; “F” = input “false”. 6/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM WRITE TRUTH TABLE BWb# BWc# BWd# BWe# BWf# BWg# Function W# BWa# BWh# H X X X X X X X X Read L L H H H H H H H Write Byte “a” L H L H H H H H H Write Byte “b” L H H L H H H H H Write Byte “c” L H H H L H H H H Write Byte “d” L H H H H L H H H Write Byte “e” L H H H H H L H H Write Byte “f” L H H H H H H L H Write Byte “g” L H H H H H H H L Write Byte “h” L L L L L L L L L Write All Bytes L H H H H H H H H Write Abort / NOP Note14. “H” = input VIH; “L” = input VIL; “X” = input VIH or VIL. Note15. All inputs must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDD Power Supply Voltage VDDQ I/O Buffer Power Supply Voltage VI Input Voltage VO Output Voltage Conditions With respect to VSS Ratings Unit -1.0*~3.6 V -1.0*~3.6 V -1.0~VDDQ+1.0 ** V -1.0~VDDQ+1.0 ** V PD Maximum Power Dissipation (VDD) 1050 mW TOPR Operating Temperature 0~70 °C TSTG(bias) Storage Temperature(bias) -10~85 °C -55~125 °C TSTG Storage Temperature Note16. * This is -1.0V~3.6V when pulse width≤2ns, and -0.5V in case of DC. ** This is -1.0V~VDDQ+1.0V when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC. 7/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM DC ELECTRICAL CHARACTERISTICS Limits Symbol Parameter Condition Unit Min Max VDD Power Supply Voltage 2.375 2.625 V VDDQ I/O Buffer Power Supply Voltage 2.375 2.625 V VIH High-level Input Voltage 1.7 VDDQ+0.3* V VIL Low-level Input Voltage -0.3* 0.7 V VOH High-level Output Voltage IOH = -2.0mA VOL Low-level Output Voltage IOL = 2.0mA 0.4 VI = 0V ~ VDDQ 10 ILI Input Leakage Current except ZZ and LBO# Input Leakage Current of LBO# Input Leakage Current of ZZ VI = 0V ~ VDDQ VI = 0V ~ VDDQ 100 100 ILO Output Leakage Current VI/O = 0V ~ VDDQ 4.0ns cycle(250MHz) 550 Power Supply Current : Operating Device selected; Output Open VI≤VIL or VI≥VIH ZZ≤VIL 4.4ns cycle(225MHz) 500 5.0ns cycle(200MHz) 450 Device deselected VI≤VIL or VI≥VIH ZZ≤VIL 4.0ns cycle(250MHz) 200 4.4ns cycle(225MHz) 190 5.0ns cycle(200MHz) 180 ICC1 ICC2 Power Supply Current : Deselected VDDQ-0.4 V µA 10 Device deselected; Output Open VI≤VSS+0.2V or VI≥VDDQ-0.2V CLK frequency=0Hz, All inputs static Snooze mode ICC4 Snooze Mode Standby Current ZZ≥VDDQ-0.2V, LBO#≥VDD-0.2V Device selected; 4.0ns cycle(250MHz) Output Open ICC5 Stall Current CKE#≥VIH 4.4ns cycle(225MHz) VI≤VSS+0.2V or 5.0ns cycle(200MHz) VI≥VDDQ-0.2V Note17.*VILmin is –1.0V and VIH max is VDDQ+1.0V in case of AC(Pulse width≤2ns). Note18."Device Deselected" means device is in power-down mode as defined in the truth table. ICC3 V CMOS Standby Current (CLK stopped standby mode) µA mA mA 30 mA 30 mA 180 160 mA 140 CAPACITANCE Symbol CI Parameter Input Capacitance CO Input / Output (DQ) Capacitance Note19. This parameter is sampled. Condition Limits Min Typ Max Unit VI=GND, VI=25mVrms, f=1MHz 6 pF VO=GND, VO=25mVrms, f=1MHz 8 pF 8/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM THERMAL RESISTANCE 4-Layer PC board mounted (70x70x1.6mmT) Symbol θJA θJC Parameter Limits Condition Thermal resistance Junction Ambient Min Typ Unit Max Air velocity=0m/sec 25.56 °C/W Air velocity=2m/sec 17.63 °C/W 6.12 °C/W Thermal resistance Junction to Case AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted) (1) MEASUREMENT CONDITION Input pulse levels ········································ VIH=VDDQ, VIL=0V Input rise and fall times ······························· faster than or equal to 1V/ns Input timing reference levels ······················· VIH=VIL=VDDQ / 2 Output reference levels ······························· VIH=VIL=VDDQ / 2 Output load ·················································· Fig.1 30pF (Including wiring and JIG) Q ZO=50Ω 50Ω VT=VDDQ / 2 Fig.1 Output load Input Waveform VDDQ / 2 toff tplh Output Waveform Input Waveform VDDQ / 2 VDDQ / 2 Fig.2 Tdly measurement tphl Vh Output Waveform (toff) Vl ton Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz)) Vz 0.2(Vz-Vl) Vz-(0.2(Vz-Vl)) (ton) Fig.3 Tri-State measurement Note20.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform. Input waveform should have a slew rate of faster than or equal to 1V/ns. Note21.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial to final Value VDDQ/2. Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note22. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20% from its initial Value VDDQ/2 to its final Value. Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table. Note23.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns. 9/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM (2)TIMING CHARACTERISTICS Symbol Parameter Clock tKHKH Clock Cycle Time tKHKL Clock HIGH Time tKLKH Clock LOW Time Output times tKHQV Clock HIGH to Output Valid tKHQX Clock HIGH to Output Invalid tKHQX1 Clock HIGH to Output in Low-Z tKHQZ Clock HIGH to Output in High-Z tGLQV G# to output valid tGLQX1 G# to output in Low-Z G# to output in High-Z tGHQZ Setup Times Address Valid to Clock HIGH tAVKH tadvVKH ADV Valid to Clock HIGH tWVKH Write Valid to Clock HIGH tBxVKH Byte Write Valid to Clock HIGH (BWa#~BWh#) tEVKH Enable Valid to Clock HIGH (E1#,E2,E3#) tDVKH Data In Valid Clock HIGH Hold Times tKHAX Clock HIGH to Address don’t care tKHadvX Clock HIGH to ADV don’t care tKHWX Clock HIGH to Write don’t care tKHBxX Clock HIGH to Byte Write don’t care (BWa#~BWh#) tKHEX Clock HIGH to Enable don’t care (E1#,E2,E3#) tKHDX Clock HIGH to Data In don’t care ZZ tZZS ZZ standby tZZREC ZZ recovery 250MHz -25 Min Max Limits 225MHz -22 Min Max 200MHz -20 Min Max 4.0 1.5 1.5 4.4 1.6 1.6 5.0 1.8 1.8 2.6 1.5 1.5 1.5 2.6 2.6 0.0 2.8 1.5 1.5 1.5 2.8 2.8 0.0 2.6 ns ns ns 3.2 1.5 1.5 1.5 3.2 3.2 0.0 2.8 Unit 3.2 ns ns ns ns ns ns ns 0.8 0.8 0.8 0.8 0.8 0.8 1.0 1.0 1.0 1.0 1.0 1.0 1.2 1.2 1.2 1.2 1.2 1.2 ns ns ns ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns 2*tKHKH 2*tKHKH 2*tKHKH 2*tKHKH Note24.All parameter except tZZS, tZZREC in this table are measured on condition that ZZ=LOW fix. Note25.Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted. Note26. tKHQX1, tKHQZ, tGLQX1, tGHQZ are sampled. Note27.LBO# is static and must not change during normal operation. 2*tKHKH 2*tKHKH ns ns 10/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM (3)READ TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# BWx# tAVKH ADD tKHAX A1 A2 A3 tKHQX1 DQ tGLQV Q(A1) tKHQV Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) tGHQZ tKHQX Q(A2) Q(A3) Q(A3+1) tKHQZ tGLQX1 G# Read A1 Read A2 Burst Read A2+1 Stall Burst Read Burst Read Burst Read A2+2 A2+3 A2 Deselect Continue Deselect Read A3 Burst Read Burst Read Burst Read A3+1 A3+2 A3+3 DON'T CARE UNDEFINED Note28.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note29. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note30.ZZ is fixed LOW. 11/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM (4)WRITE TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# tBVKH tKHBX BWx# tAVKH ADD tKHAX A1 A2 A3 A4 tDVKH tKHDX DQ D(A1) D(A2) D(A2+1) D(A2+3) D(A2) D(A3) D(A4) D(A4+1) G# Write A1 Write A2 Burst Write A2+1 NOP Burst Write A2+3 Write A2 Write A3 NOP Write A4 Burst Write A4+1 Stall Burst Write Burst Write A4+2 A4+3 DON'T CARE UNDEFINED Note31.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note32. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note33.ZZ is fixed LOW. 12/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM (5)READ/WRITE TIMING tKHKH CLK tKHKL tKLKH tckeVKH tKHckeX CKE# tEVKH tKHEX E# tadvVKH tKHadvX ADV tWVKH tKHWX W# tBVKH tKHBX BWx# tAVKH ADD tKHAX A1 A2 A2 A3 A3 A4 A5 tDVKH tKHQX1 tKHDX DQ Q(A1) tKHQV D(A2) Q(A2) D(A3) D(A3+1) Q(A3) Q(A3+1) D(A4) Q(A5) tKHQV G# Read A1 Write A2 Read A2 Write A3 Burst Write A3+1 Read A3 Burst Read A3+1 Deselect Write A4 Stall Read A5 DON'T CARE Burst Read Burst Read A5+1 A5+2 UNDEFINED Note34.Q(An) refers to output from address An. Q(An+1) refers to output from the next internal burst address following An. Note35. E# represents three signals. When E# is LOW, it represents E1# is LOW, E2 is HIGH and E3# is LOW. Note36.ZZ is fixed LOW. 13/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM (6)SNOOZE MODE TIMING CLK tZZS tZZREC ZZ All Inputs (except ZZ) DESELECT or READ only Q Snooze Mode 14/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM JTAG PORT OPERATION Overview The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. Unlike JTAG implementations that have been common among SRAM vendors for the last several years, this implementation dose offer a form of EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test program compiler errors caused by previous non-compliant implementation. The JTAG Port interfaces with conventional CMOS logic level signaling. Disabling the JTAG port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The TDO pin should be left unconnected. JTAG Pin Description Pin TCK Name Test Clock TMS Test Mode Select TDI Test Data In TDO Test Data Out Function The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins. the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce the same result as a logic one input level. The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between the TDI and TDO pins. Note: This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up. JTAG Port Registers Overview The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and 0s applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in the Test-Logic-Reset state. 15/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Bypass Register The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instruction can be used to activate the Boundary Scan Register. Identification (ID) Register The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the Capture-DR state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It describes various attributes of the SRAM (see page 25). The register is then placed between the TDI and TDO pins when the controller is moved into the Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins. TAP Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. Although the TAP Controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of the mandatory instructions, EXTEST, is uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads. This device will not perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in the Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the TAP controller is moved to the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction Set for this device is listed in the following table. Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the BSDL file. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins. 16/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic 0s. EXTEST is not implemented in the TAP Controller, and therefore this device is not compliant to the 1149.1 Standard. When the EXTEST instruction is loaded into the Instruction Register, the device responds as if the SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST place the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at power-up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and the Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state. RFU These instructions are reserved for future use. Do not use these instructions. 17/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM JTAG TAP BLOCK DIAGRAM Bypass Register 0 Instruction Register 2 1 0 TDI Identification Register TDO 31 30 29 . . . . . . . . 2 1 0 Boundary Scan Register .. .............. .. 2 1 0 TMS TCK Test Access Port (TAP) Controller 18/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM BOUNDARY SCAN ORDER Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Bump 5V 6U 8U 7V 7W 8V 9V 10W 10V 10U 11W 11V 11U 11T 10T 11R 10R 11P 10P 11N 10N 11M 10M 11L 10L 6P 6J 10J 11J 10H 11H 10G 11G 10F 10E 11F 11E 10D 11D 11C Pin Name A16 A15 A11 A13 A14 A12 A10 DQe DQe DQe DQe DQe DQe DQe DQe DQPe DQPa DQa DQa DQa DQa DQa DQa DQa DQa ZZ MCH DQf DQf DQf DQf DQf DQf DQf DQPf DQf DQPb DQb DQb DQb Bit 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Bump 11B 11A 10C 10B 10A 9A 7A 7B 8C 9C 9B 8B 6A 6D 6K 6B 3K 8A 4B 3B 3C 4C 4A 6C 5A 3A 2A 2B 2C 1A 1B 1C 1D 2D 1E 1F 2E 2F 1G 2G Pin Name DQb DQb DQb DQb DQb A9 A8 A17 BWe# BWa# BWf# BWb# ADV G# CKE# W# CLK E3# BWg# BWc# BWh# BWd# E2 E1# A7 A6 DQg DQg DQg DQg DQg DQg DQg DQg DQPg DQc DQPc DQc DQc DQc Bit 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Bump 1H 2H 1J 2J 6L 6M 2L 1L 2M 1M 2N 1N 2P 1P 2R 1R 2T 1T 1U 1V 1W 2U 2V 2W 6T 3V 4V 4U 5W 6V 6W Pin Name DQc DQc DQc DQc MCH MCH DQh DQh DQh DQh DQh DQh DQh DQh DQPh DQPd DQd DQd DQd DQd DQd DQd DQd DQd LBO# A5 A4 A3 A2 A1 A0 19/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM JTAG TAP CONTROLLER STATE DIAGRAM Test-Logic-Reset 1 0 Run-Test/Idle 1 Select-DR-Scan 0 1 Select-IR-Scan 0 1 0 1 Capture-DR 0 Capture-IR 0 Shift-DR Shift-IR 0 1 1 0 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR Pause-IR 0 1 Exit2-DR 0 0 1 Exit2-IR 1 0 1 Update-DR 1 1 Update-IR 0 1 0 TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted) Limits Unit Min Max Test Port Input High Voltage 0.65*VDDQ VDDQ+0.3 ** V VIHT VILT Test Port Input Low Voltage -0.3 ** 0.35*VDDQ V VOHT Test Port Output High Voltage IOH=-100µA VDDQ-0.1 V VOLT Test Port Output Low Voltage IOL=+100µA 0.1 V IINT TMS, TCK and TDI Input Leakage Current -10 10 µA IOLT TDO Output Leakage Current Output Disable, VOUT=0V~VDDQ -10 10 µA Note37. **Input Undershoot/Overshoot voltage must be –1.0V<Vi<VDDQ+1V(max. 3.6V) with a pulse width not to exceed 20% tTCK. Symbol Parameter Condition 20/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=2.375~2.625V, unless otherwise noted) (1)MEASUREMENT CONDITION Input pulse levels ········································ VIH=VDDQ, VIL=0V Input rise and fall times ······························· faster than or equal to 1V/ns Input timing reference levels ······················· VIH=VIL=VDDQ / 2 Output reference levels ·······························VIH=VIL=VDDQ / 2 Output load ·················································· Fig.4 30pF (Including wiring and JIG) Q ZO=50Ω 50Ω VT=VDDQ / 2 Fig.4 Output load (2)TIMING CHARACTERISTICS Symbol Limits Min Max 20 50 20 20 10 10 20 Parameter tTF tTKC tTKH tTKL tTS tTH tTKQ TCK Frequency TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TDI, TMS setup time TDI, TMS hold time TCK Low to TDO valid Unit MHz ns ns ns ns ns ns (3) TIMING tTKC tTKH tTKL TCK tTS tTH TMS tTS tTH TDI tTKQ TDO 21/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM JTAG TAP INSTRUCTION SET SUMMARY Instruction Code EXTEST 000 IDCODE 001 SAMPLE-Z 010 RFU SAMPLE/PRELOAD RFU RFU BYPASS 011 100 101 110 111 Description Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. Preloads ID Register and places it between TDI and TDO Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all Data and Clock output drivers to High-Z Do not use this instruction; Reserved for Future Use. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Do not use this instruction; Reserved for Future Use. Do not use this instruction; Reserved for Future Use. Places the BYPASS Register between TDI and TDO. STRUCTURE OF IDENTIFICATION REGISTER Revision Bit No. M5M5T5672 Device Information Capacity Function VDD Width Gen. JEDEC Vendor Code of MITSUBISHI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 MSB 0 1 LSB Note38. Bit of Device Information “Gen.(Generation)” means Bit No. 1st Generation 2nd Generation 3rd Generation 13 0 0 1 12 0 1 0 Note39. Bit of Device Information ”Width” means Bit No. X16 X18 X32 X36 X64 X72 16 0 0 0 0 1 1 15 0 0 1 1 0 0 14 0 1 0 1 0 1 Note40. Bit of Device Information ”Function” means Bit No. Network SRAM PB 20 0 0 19 1 0 18 0 0 17 0 1 Note41. Bit of Device Information ”Capacity” means Bit No. 1M or 1.15M 2M or 2.3M 4M or 4.5M 8M or 9M 16M or 18M 32M or 36M 24 0 0 0 0 0 0 23 0 0 0 1 1 1 22 0 1 1 0 0 1 21 1 0 1 0 1 0 Note42. Bit of Device Information ”VDD” means Bit No. 3.3V 2.5V 1.8V / 2.5V 1.5V 27 0 0 0 0 26 0 0 1 1 25 0 1 0 1 22/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM PACKAGE OUTLINE 209(11x19) bump Ball Grid Array(BGA) Pin Pitch 1.0mm Refer to JEDEC Standard MS-028, Variation BC, which can be seen at: http://www.jedec.org/download/search/MS-028C.pdf 23/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM REVISION HISTORY Rev.No. 0.0 0.1 History First revision DC ELECTRICAL CHARACTERISTICS Changed ILI limit from 10uA to 100uA (Input Leakage Current of ZZ and LBO#) Changed Icc3 and Icc4 limit from 20mA to 30mA (Standby Current) Date September 25, 2002 January 31, 2003 Preliminary Preliminary 24/25 Preliminary M5M5T5672TG REV.0.1 MITSUBISHI LSIs M5M5T5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. 25/25 Preliminary M5M5T5672TG REV.0.1