CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles •Supports 133-MHz bus operations •1M × 36/2M × 18/512K × 72 common I/O •Fast clock-to-output times — 6.5 ns (for 133-MHz device) — 7.5 ns (for 117-MHz device) • Single 3.3V –5% and +5% power supply VDD • Separate VDDQ for 3.3V or 2.5V • Clock Enable (CEN) pin to suspend operation • Burst Capability–linear or interleaved burst order • Available in 119-ball bump BGA, 165-ball FBGA, and 100-pin TQFP packages (CY7C1461V33 and CY7C1463V33). 209-ball FBGA package for CY7C1465V33. Functional Description The CY7C1461V33, CY7C1463V33 and CY7C1465V33 SRAMs are designed to eliminate dead cycles when transitions from Read to Write or vice versa. These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency. They integrate 1,048,576 × 36/2,097,152 × 18/ 524,288 × 72 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. The Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE1, CE2 and CE3), cycle start input (ADV/LD), Clock Enable (CEN), Byte Write Selects (BWSa, BWSb, BWSc,BWSd,BWSe, BWSf, BWSg, BWSh), and Read-Write control (WE). BWSc and BWSd apply to CY7C1461V33 and CY7C1465V33 only. BWSe, BWSf, BWSg and BWSh apply to CY7C1465V33 only A Clock Enable (CEN) pin allows operation of the CY7C1461V33, CY7C1463V33, and CY7C1465V33 to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is high and the internal device registers will hold their previous values. There are three Chip Enable (CE1, CE2, CE3) pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is low, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (READ or WRITE) will be completed. The data bus will be in high impedance state two cycles after chip is deselected or a Write cycle is initiated. The CY7C1461V33, CY7C1463V33 and CY7C1465V33 have an on-chip two-bit burst counter. In the burst mode, CY7C1461V33, CY7C1463V33 and CY7C1465V33 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH) Output Enable (OE) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. Logic Block Diagram CLK CE D Data-In REG. Q ADV/LD Ax AX DQX DPX CEN CE1 CE2 CE 3 BWSX WE X = 19:0 2M×18 X = 20:0 X = a, b X = a, b X = a, b X = a, b, X = a, b 512K×72 X = 18:0 X = a, b, DQx DPx OE c,d,e,f,g,h c,d,e,f,g,h c,d,e,f,g,h Cypress Semiconductor Corporation Document #: 38-05193 Rev. *B 1M × 36 2M × 18 512K × 72 Memory Array BWSx Mode X = a, b, X= a, b, X = a, b , c, d c, d c, d 1M×36 CONTROL and WRITE LOGIC • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised November 18, 2002 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current CY7C1461V33 CY7C1461V33 CY7C1461V33 CY7C1461V33 CY7C1463V33 CY7C1463V33 CY7C1463V33 CY7C1463V33 CY7C1465V33 CY7C1465V33 CY7C1465V33 CY7C1465V33 -150 -133 -117 -100 Unit 5.5 6.5 7.5 8.5 ns Commercial TBD TBD TBD TBD mA TBD TBD TBD TBD mA Shaded areas contain advance information. Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DPb DQb DQb VDDQ VSS VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DPb NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1463V33 (2M × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05193 Rev. *B A NC NC VDDQ VSS NC DPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DPa NC NC NC MODE A A A A A1 A0 NC NC VS VDD NC A CY7C1461V33 (1M × 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A DPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ A A A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD A A 100-pin TQFP Package Page 2 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Pin Configurations (continued) 119-ball Bump BGA CY7C1461V33 (1M × 36)–7 × 17 BGA 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B C D E F G H J K L M N P NC NC CE2 A A A ADV/LD VDD A A CE3 A NC NC DQc DPc VSS NC VSS DPb DQb R T U DQc DQc VSS CE1 VSS DQb DQb VDDQ DQc VSS OE VSS DQb VDDQ DQc DQc BWSc A BWSb DQb DQb DQc VDDQ DQc VDD VSS NC WE VDD VSS NC DQb VDD DQb VDDQ DQd DQd DQd DQd VSS BWSd CLK NC VSS BWSa DQa DQa DQa DQa VSS CEN VSS DQa VDDQ VDDQ DQd DQd DQd VSS A1 VSS DQa DQa DQd DPd VSS A0 VSS DPa DQa NC A MODE VDD NC A NC NC 72M A A A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ CY7C1463V33 (2M × 18)–7 × 17 BGA A B C D E F G H J K L M N P R T U Document #: 38-05193 Rev. *B 1 2 3 4 5 6 7 VDDQ A A A A A VDDQ NC CE2 A ADV/LD A CE3 NC NC A A VDD A A NC DQb NC VSS NC VSS DPa NC NC DQb VSS CE1 VSS NC DQa VDDQ NC VSS OE VSS DQa VDDQ NC DQb VDDQ DQb NC VDD BWSb VSS NC A WE VDD VSS VSS NC NC DQa VDD DQa NC VDDQ DQa NC DQb VSS CLK VSS NC DQb NC VSS NC BWSa DQa NC VDDQ DQb VSS CEN VSS NC VDDQ DQb NC VSS A1 VSS DQa NC NC DPb VSS A0 VSS NC DQa NC NC A MODE VDD NC A 72M A A A A A ZZ VDDQ TMS TDI TCK TDO NC VDDQ Page 3 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Pin Configurations (continued) 165-ball Bump FBGA CY7C1461V33 (1M × 36)–11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 11 A NC A CE1 BWSc BWSb CE3 CEN ADV/LD A A NC B C D E F G H J K L M N P NC DPc A NC CE2 VDDQ BWSd VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC NC DPb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb NC DQd VDD DQd NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ DQa DQd DQd DQd DQd VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DPd NC VDDQ VSS NC NC NC VSS VDDQ NC DPa NC 72M A A TDI A1 TDO A A A NC MODE A A A TMS A0 TCK A A A A 11 R CY7C1463V33 (2M × 18)–11 × 15 FBGA 1 2 3 4 5 6 7 8 9 10 A NC A CE1 BWSb NC CE3 CEN ADV/LD A A A B C D E F G H J K L M N P NC NC A NC CE2 VDDQ NC VSS BWSa VSS CLK VSS WE VSS OE VSS A VDDQ A NC NC DPa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC DQb VDD NC NC VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD NC VDDQ NC DQa ZZ NC DQb DQb NC NC VDDQ VDDQ VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD VDDQ VDDQ DQa DQa NC NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DPb NC VDDQ VSS NC NC NC VSS VDDQ NC NC NC 72M A A TDI A1 TDO A A A NC MODE A A A TMS A0 TCK A A A A R Document #: 38-05193 Rev. *B Page 4 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Pin Configurations (continued) CY7C1465 (512K × 72) 1 2 A DQg DQg B DQg DQg C DQg D E 3 4 5 6 7 8 9 10 11 ADV/LD A CE3 A DQb DQb CE2 A BWSc BWSg NC WE A BWSb BWSf DQb DQb DQg BWSh BWSd NC CE1 NC BWSe BWSa DQb DQb DQg DQg VSS NC NC OE NC NC VSS DQb DQb DPg DPc VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DPf DPb DQc VSS VSS VSS NC VSS VSS VSS DQf DQc VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQf DQf VSS VSS NC VSS VSS VSSQ DQf DQf VDDQ VDD NC VDD VDDQ VDDQ DQf DQf CEN VSS NC NC NC NC A F DQc G DQc H DQc DQc VSS J DQc DQc VDDQ K NC NC CLK NC VSS L DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa M DQh DQh VSS VSS VSS NC VSS VSS VSS DQa DQa N DQh DQh VDDQ VDDQ VDD NC VDD VDDQ VDDQ DQa DQa P DQh DQh VSS VSS VSS ZZ VSS VSS VSS DQa DQa DPh VDDQ VDDQ VDD VDD VDD VDDQ VDDQ NC NC MODE NC NC R DPd T DQd DQd VSS U DQd DQd NC A V DQd DQd A W DQd DQd TMS DPa DQf DPe VSS DQe DQe 72M A A A NC DQe DQe A A A1 A A A DQe DQe TDI A A0 A TDO TCK DQe DQe Pin Definitions Pin Name I/O Type Pin Description A0 A1 A InputSynchronous Address Inputs used to select one of the 1048576/2097152/524,288 address locations. Sampled at the rising edge of the CLK. BWSa BWSb BWSc BWSd BWSe BWSf BWSg BWSh InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.BWSe controls DQe and DPe, BWSf controls DQf and DPf, BWSg controls DQg and DPg, BWSh controls DQh and DPh. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Document #: 38-05193 Rev. *B Page 5 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Pin Definitions (continued) Pin Name I/O Type Pin Description CLK InputClock CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. DQa DQb DQc DQd DQe DQf DQg DQh I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[x:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.DQ a,b,c,d,e,f,g,h are eight bits wide DPa DPb DPc DPd DPe DPf DPg DPh I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[x:0]. DP a,b,c,d,e,f,g and h are one bit wide. ZZ InputAsynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved.This pin can also be left as a NC. MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. VDD VDDQ Power Supply Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. VSS Ground TDO JTAG Serial Output Synchronous Ground for the device. Should be connected to ground of the system. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).This pin can be left as a NC if JTAG is not used. TDI JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).This pin can Synchronous be left as a NC if JTAG is not used. TMS Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK Synchronous (BGA only).This pin can be left as a NC if JTAG is not used. TCK JTAG Serial Clock 72M – No connects. Reserved for address expansion. NC – No connects. Document #: 38-05193 Rev. *B Serial clock to the JTAG circuit (BGA only).This pin can be left as a NC if JTAG is not used. Page 6 of 26 PRELIMINARY Introduction Functional Overview The CY7C1461V33/CY7C1463V33/CY7C1465V33 is a synchronous Flow-Thru Burst NoBL SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting Chip Enable(s) (CE1, CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). Byte Write Selects can be used to conduct byte Write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed Write circuitry. Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP, CE1 on the BGA) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A Read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a Read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133-MHz device) provided OE is active LOW. After the first clock of the Read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The CY7C1461V33/CY7C1463V33/CY7C1465V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the Document #: 38-05193 Rev. *B CY7C1461V33 CY7C1463V33 CY7C1465V33 burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip Enable(s) asserted active, and (3) the Write signal WE is asserted LOW. The address presented is loaded into the Address Register. The Write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DP. On the next clock rise the data presented to DQ and DP (or a subset for byte Write operations, see Write Cycle Description table for details) inputs is latched into the device and the Write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by Byte Write Select signals. The CY7C1461V33 / CY7C1463V33 / CY7C1465V33 provide byte Write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively Write to only the desired bytes. Bytes not selected during a byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte Write operations. Because the CY7C1461V33/CY7C1463V33/CY7C1465V33 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DP are automatically three-stated during the data portion of a Write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1461V33/CY7C1463V33/CY7C1465V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWSa,b,c,d,e,f,g,h/ BWSa,b,c,d / BWSa,b inputs must be driven in each cycle of the burst Write in order to Write the correct bytes of data. Page 7 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Operation Address Used CE Deselected CEN ADV/LD WE BWSx CLK Comments External 1 0 0 X X L-H I/Os three-state following next recognized clock. – X 1 X X X L-H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L-H Address latched. Begin Write External 0 0 0 0 Valid Burst Read Operation Internal X 0 1 X X Burst Write Operation Internal X 0 1 X Valid Suspend Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWSa,b,c,d,e,f,g,h/ BWSa,b,c,d/BWSa,b. Sleep Mode Interleaved Burst Sequence First Address A[1:0] 00 01 10 11 L-H Address latched, data presented two valid clocks later. The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V Min. Max. 15 2tCYC Unit mA ns ns 2tCYC Notes: 1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte Write selects are asserted. See Write Cycle Description table for details. 2. Write is defined by WE and BWSx. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN = 1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05193 Rev. *B Page 8 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Write Cycle Descriptions[1, 2] Function (CY7C1461V33) WE BWSd BWSc BWSb BWSa Function (CY7C1461V33) Read 1 X X X X Read Write – No Bytes Written 0 1 1 1 1 Write – No Bytes Written Write Byte 0 − (DQa and DPa) 0 1 1 1 0 Write Byte 0 − (DQa and DPa) Write Byte 1 − (DQb and DPb) 0 1 1 0 1 Write Byte 1 − (DQb and DPb) Write Bytes 1, 0 0 1 1 0 0 Write Bytes 1, 0 Write Byte 2 − (DQc and DPc) 0 1 0 1 1 Write Byte 2 − (DQc and DPc) Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Bytes 2, 1, 0 Write Byte 3 − (DQd and DPd) 0 0 1 1 1 Write Byte 3 − (DQd and DPd) Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 1, 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write Bytes 3, 2, 1 Write All Bytes 0 0 0 0 0 Write All Bytes WE BWSb BWSa Read 1 x x Read Write – No Bytes Written 0 1 1 Write – No Bytes Written Write Byte 0 – (DQa and DPa) 0 1 0 Write Byte 0 – (DQa and DPa) Write Byte 1 – (DQb and DPb) 0 0 1 Write Byte 1 – (DQb and DPb) Write Both Bytes 0 0 0 Write Both Bytes Function (CY7C1463V33) IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1463V33/CY7C1461V33 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Document #: 38-05193 Rev. *B Function (CY7C1463V33) Test Access Port–Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current Page 9 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset TAP Instruction Set A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired Document #: 38-05193 Rev. *B Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all -0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. Page 10 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Bypass Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 38-05193 Rev. *B Page 11 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY TAP Controller State Diagram 1[7] TEST-LOGIC RESET 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-DR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 ote: 7. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05193 Rev. *B Page 12 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register . . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range[8, 9] Parameter Description Test Conditions Min. VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 VOH2 Output HIGH Voltage IOH = −100 µA 3.0 VOL1 Output LOW Voltage IOL = 8.0 mA VOL2 Output LOW Voltage IOL = 100 µA VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Load Current GND ≤ VI ≤ VDDQ TAP AC Switching Characteristics Over the Operating Range Parameter Description Max. Unit V V 0.4 V 0.2 V 1.8 VDD + 0.3 V –0.5 0.8 V –5 5 µA [10, 11] Min. Max. 100 Unit tTCYC TCK Clock Cycle Time ns tTF TCK Clock Frequency tTH TCK Clock HIGH 40 ns tTL TCK Clock LOW 40 ns 10 MHz Notes: 8. All voltage referenced to ground. 9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. Document #: 38-05193 Rev. *B Page 13 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY TAP AC Switching Characteristics Over the Operating Range (continued)[10, 11] Parameter Description Min. Max. Unit Set-up Times tTMSS TMS Set-up to TCK Clock Rise 10 ns tTDIS TDI Set-up to TCK Clock Rise 10 ns tCS Capture Set-up to TCK Rise 10 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 10 ns tTDIH TDI Hold after Clock Rise 10 ns tCH Capture Hold after clock rise 10 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 0 ns ns TAP Timing and Test Conditions 1.25V 50Ω ALL INPUT PULSES TDO VIH Z0 = 50Ω CL = 20 pF 0V GND tTH tTL (a) Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Document #: 38-05193 Rev. *B tTDOX Page 14 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Identification Register Definitions Instruction Field x 18 x36 Description Revision Number (31:29) 000 000 Reserved for version number. Department Number (27:25) 101 101 Department Number Voltage (28&24) 00 00 Architecture (23:21) 001 001 Architecture Type Memory Type (20:18) 001 001 Defines type of memory Device Width (17:15) 010 100 Defines width of the SRAM. x36 or x18 111 111 Defines the density of the SRAM Device Density (14:12) Cypress JEDEC ID (11:1) ID Register Presence (0) 00011100100 00011100100 Allows unique identification of SRAM vendor. 1 1 Indicate the presence of an ID register. Scan Register Sizes Register Name Bit Size (x18) Bit Size (x36) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan 51 70 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05193 Rev. *B Page 15 of 26 PRELIMINARY Boundary Scan Order (1M × 36) Document #: 38-05193 Rev. *B CY7C1461V33 CY7C1463V33 CY7C1465V33 Boundary Scan Order (2M × 18) Page 16 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Current into Outputs (LOW)......................................... 20 mA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Supply Voltage on VDD Relative to GND ...... –0.5V to +4.6V Range DC Voltage Applied to Outputs in High-Z State[12] ............................... –0.5V to VDDQ + 0.5V Com’l Ambient Temperature[11] 0°C to +70°C DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.5V VDD VDDQ 3.3V + 5%/ –5% 2.375(Min.) VDD(Max.) Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VDD Power Supply Voltage 3.135 3.465 V VDDQ I/O Supply Voltage 2.375 VDD V VOH Output HIGH Voltage[13] VDD = Min., IOH = –4.0 mA VDDQ = 3.3V 2.4 V VDD = Min., IOH = –1.0 mA VDDQ = 2.5V 2.0 V VOL Output LOW Voltage[13] VDD = Min., IOL = 8.0 mA VDDQ = 3.3V 0.4 V VDD = Min., IOL = 1.0 mA VDDQ = 2.5V 0.4 V VIH Input HIGH Voltage VDDQ = 3.3V 2.0 V VDDQ = 2.5V 1.7 V VIL Input LOW Voltage VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V 5 µA 30 µA IX Input Load Current GND ≤ VI ≤ VDDQ Input Current of MODE IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC ISB2 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ − 0.3V, f = 0 ISB3 Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN < 0.3V or VIN > VDDQ – 0.3V, f = fMAX = 1/tCYC Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 ISB4 5 µA 150 MHz TBD mA 133 MHz TBD mA 117 MHz TBD mA 150 MHz TBD mA 133 MHz TBD mA 117 MHz TBD mA All speed grades TBD mA 150 MHz TBD mA 133 MHz TBD mA 117 MHz TBD mA All speed grades TBD mA Notes: 12. TA is the case temperature. 13. Minimum voltage equals −2.0V for pulse durations of less than 20 ns. 14. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads. Document #: 38-05193 Rev. *B Page 17 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Capacitance[16] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = VDDQ = 2.5V Max. Unit TBD pF TBD pF TBD pF AC Test Loads and Waveforms R = 317Ω VDDQ OUTPUT ALL INPUT PULSES OUTPUT Z0 = 50Ω VDD 5 pF R = 351Ω VL = 1.25V INCLUDING JIG AND SCOPE (a) 90% 10% 90% 10% RL = 50Ω [15] GND Rise: 2V/ns Fall: 2V/ns (c) (b) Thermal Resistance[16] Parameter QJA QJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 × 1.125 inch, four-layer printed circuit board BGA Typ. TBD TQFP Typ. TBD Unit °C/W TBD TBD °C/W Switching Characteristics (over the operating range) 150 Parameter Clock tCYC FMAX tCH tCL Output Times tCDV tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-up Times tAS tDS tCENS tWES Description Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW Data Output Valid After CLK Rise OE LOW to Output Valid[16, 18, 20] Data Output Hold After CLK Rise Clock to High-Z[16, 17, 18, 19, 20] Clock to Low-Z[16, 17, 18, 19, 20] OE HIGH to Output High-Z[17, 18, 20] OE LOW to Output Low-Z[17, 18, 20] Address Set-up Before CLK Rise Data Input Set-up Before CLK Rise CEN Set-Up Before CLK Rise WE, BWSx Set-up Before CLK Rise Min. 133 Max. 6.7 Min. 117 Max. 7.5 150 2.5 2.5 Min. 8.5 133 2.5 2.5 5.5 3.0 Max. 117 3.0 3.0 0 0 0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns 2.5 5.0 2.5 7.5 3.5 ns MHz ns ns ns ns ns ns ns ns ns 2.5 6.5 3.0 Unit 2.5 5.0 2.5 4.0 5.0 2.5 4.0 4.0 Notes: 15. Input waveform should have a slew rate of > 1 V/ns. 16. Tested initially and after any design or process change that may affect these parameters. 17. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b), and (c) of AC Test Loads. 18. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 20. This parameter is sampled and not 100% tested. Document #: 38-05193 Rev. *B Page 18 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Switching Characteristics (over the operating range) (continued) 150 Parameter tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Description ADV/LD Set-up Before CLK Rise Chip Select Set-up Min. 1.5 1.5 Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 133 Max. Min. 1.5 1.5 117 Max. Min. 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max. Unit ns ns 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns DESELECT DESELECT Suspend Read Write Read DESELECT Read Read Write Read/Write/Deselect Sequence Read Switching Waveforms CLK tCENH tCENS tCH tCL tCENH tCENS tCYC CEN tAS ADDRESS RA1 WA2 RA3 RA4 WA5 RA6 RA7 Q4 Out D5 In Q6 Out tAH WE tWES tCES tWEH tCEH CE tCLZ Data In/Out tCHZ tDOH Q1 Out tCHZ D2 In Q3 Out Q7 Out Device tCDV originally tDOH deselected WE is the combination of WE and BWSx(x = a, b, c, d) to define a Write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON’T CARE Document #: 38-05193 Rev. *B = UNDEFINED Page 19 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Switching Waveforms (continued) Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Read Burst Read Begin Read Burst Sequences CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWEH tWES tWS tWH BWSx tCES tCEH CE tCLZ Data In/Out tCHZ tDOH Q11a Out Q1+1 Out Q1+2 Out Q1+3 Out tCDV t DeviceCDV originally deselected tCLZ tDH D2 In D2+1 In D2+2 In D2+3 In Q3 Out Q3+1 Out tDS The combination of WE and BWSx(x = a, b, c, d) define a Write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON’T CARE Document #: 38-05193 Rev. *B = UNDEFINED Page 20 of 26 CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/Os tEOLZ Ordering Information Speed (MHz) 150 Ordering Code CY7C1461V33-150AC CY7C1463V33-150AC CY7C1461V33-150BGC CY7C1463V33-150BGC CY7C1465V33-150BX CY7C1461V33-150BZC CY7C1463V33-150BZC 133 CY7C1461V33-133AC CY7C1463V33-133AC Package Type Operating Range A101 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack Commercial BG119 119-ball PBGA (14 × 22 × 2.4 mm) BG209 209-ball PBGA (14 × 22 × 2.2 mm) BB165C A101 165-ball BGA (15 × 17 mm) 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack CY7C1461V33-133BGC CY7C1463V33-133BGC BG119 119-ball PBGA (14 × 22 × 2.4 mm) CY7C1465V33-133BX BG209 209-ball PBGA (14 × 22 × 2.2 mm) CY7C1461V33-133BZC CY7C1463V33-133BZC 117 Package Name CY7C1461V33-117AC CY7C1463V33-117AC CY7C1461V33-117BGC CY7C1463V33-117BGC CY7C1465V33-117BX CY7C1461V33-117BZC CY7C1463V33-117BZC BB165C A101 165-ball BGA (15 × 17 mm) 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack BG119 119-ball PBGA (14 × 22 × 2.4 mm) BG209 209-ball PBGA (14 × 22 × 2.2 mm) BB165C 165-ball BGA (15 × 17 mm) Shaded areas contain advance information. Document #: 38-05193 Rev. *B Page 21 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Package Diagrams 100-lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 51-85050-*A Document #: 38-05193 Rev. *B Page 22 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05193 Rev. *B Page 23 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.20 mm) BB165C 51-85165-** Document #: 38-05193 Rev. *B Page 24 of 26 PRELIMINARY CY7C1461V33 CY7C1463V33 CY7C1465V33 Package Diagrams (continued) 209-Lead PBGA (14 x 22 x 2.20 mm) BG209 51-85143-*B Zero Bus Latency, No Bus Latency, and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a registered trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05193 Rev. *B Page 25 of 26 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1461V33 CY7C1463V33 CY7C1465V33 PRELIMINARY Document History Page Document Title: CY7C1461V33/CY7C1463V33/CY7C1465V33 1M x 36/2M x 18/512K x 72 Flow-Thru SRAM with NoBL™ Architecture Document Number: 38-05193 REV. ECN No. Issue Date Orig. of Change Description of Change ** 113768 04/17/02 PKS Changed Spec from: 38-01072 to 38-05193 *A 116925 08/07/02 FLX TDSH increased to 2.5 ns Shaded 150-MHz device information. *B 121528 11/19/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85143 (BG209) to rev. *B Document #: 38-05193 Rev. *B Page 26 of 26