EVALUATION KIT AVAILABLE MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs General Description The MAX14920/MAX14921 battery measurement analog front-end devices accurately sample cell voltages and provide level shifting for primary/secondary battery packs up to 16 cells/+65V (max). The MAX14920 monitors up to 12 cells, while the MAX14921 monitors up to 16 cells. Both devices simultaneously sample all cell voltages, allowing accurate state-of-charge and source-resistance determination. All cell voltages are level shifted to ground reference with unity gain, simplifying external ADC data conversion. The devices have a low-noise, low-offset amplifier that buffers differential voltages of up to +5V, allowing monitoring of all common lithium-ion (Li+) cell technologies. The resulting cell voltage error is Q0.5mV. The devices’ high accuracy make them ideal for monitoring cell chemistries with very flat discharge curves, such as lithium-metal phosphate. Passive-cell balancing is supported by external FET drivers. Integrated diagnostics in the devices allow open-wire detection and undervoltage/overvoltage alarms. The devices are controlled by a daisy-chainable SPI interface. The MAX14920 is available in a 64-pin (10mm x 10mm) TQFP package with an exposed pad. The MAX14921 is available in an 80-pin (12mm x 12mm) TQFP package. Both devices are specified over the -40°C to +85°C extended temperature range. Applications Benefits and Features SHigh Accuracy ±0.5mV (max) Cell Voltage Simultaneous Cell Voltage Sampling Self-Calibration SIntegrated Diagnostics Open-Wire and Short Fault Detection Undervoltage/Overvoltage Warning Thermal Shutdown SHigh Flexibility SPI Interface 12-Cell and 16-Cell Versions +6V Minimum (3 Cells) Operation +0.5V to +4.5V Cell Voltage Range Integrated Cell-Balancing FET Drivers Integrated 5V LDO SLow Power 1µA Shutdown Mode 1µA/10µA Cell Current Draw Ordering Information appears at end of data sheet. Functional Diagram appears at end of data sheet. For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14920.related. Industrial Battery Backup Systems Telecom Battery Backup Systems Energy Storage Packs e-Transportation Energy Packs For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6496; Rev 0; 10/12 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs ABSOLUTE MAXIMUM RATINGS (All voltages referenced to AGND.) VP to AGND ...........................................................-0.3V to +70V LDOIN to AGND ................................ (VA - 0.3V) to (VP + 0.3V) VA to AGND ............................................................-0.3V to +6V CV0, DGND to AGND...........................................-0.3V to +0.3V SCLK, SDI, CS, EN...................................................-0.3V to +6V SDO, SAMPL................................................ -0.3V to (VL + 0.3V) CV1 to AGND...........................................................-0.3V to +6V CV2–CV12 to AGND...............(VCV(n* - 1) - 0.3V) to (VP + 0.3V) CT1–CT12 to AGND..................... -0.3V to (VCV1–VCV12 + 0.3V) CB2–CB12 to AGND........................ -0.3V to (VCV(n* - 1) + 0.3V) CV2–CV16 to AGND (MAX14921 only)............... (VCV(m** - 1) - 0.3V) to (VP + 0.3V) CT1–CT16 to AGND (MAX14921 only).......................-0.3V to (VCV1–VCV16 + 0.3V) CB2–CB16 to AGND (MAX14921 only)........................-0.3V to (VCV(m** - 1) + 0.3V) BA1 to AGND.......................................... -0.3V to (VCV1 + 0.3V) BA2–BA12 to AGND.........(VCV(n* - 1) - 0.3V) to min((VCVn* + 0.3V) or +6V) BA2–BA16 to AGND (MAX14921 only)............................(VCV(m** - 1) - 0.3V) to min .((VCVm** + 0.3V) or +6V) AOUT, T1, T2, T3 to AGND.......................... -0.3V to (VA + 0.3V) Continuous Power Dissipation (TA = +70°C) 64-Pin TQFP-EP (derate 31.3mW/°C above +70°C)...2508mW 80-Pin TQFP (derate 23.3mW/°C above +70°C).........1860mW Operating Temperature Range........................... -40NC to +85°C Maximum Junction Temperature......................................+150°C Storage Temperature Range............................. -65NC to +150°C Lead Temperature (soldering, 10s).................................+300°C Soldering Temperature (reflow).......................................+260°C *n = 2–12 **m = 2–16 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) Junction-to-Ambient Thermal Resistance (qJA) 64-Pin TQFP-EP..........................................................31.9°C/W 80-Pin TQFP...................................................................43°C/W Junction-to-Case Thermal Resistance (qJC) 64-Pin TQFP-EP...............................................................1°C/W 80-Pin TQFP.....................................................................8°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. DC ELECTRICAL CHARACTERISTICS (VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS +65 V POWER SUPPLIES VP Supply Voltage VP Supply Current LDOIN Supply Voltage LDOIN Supply Current VA Analog Supply Voltage VA Analog Supply Current VP IP_OFF EN = low or LOPW = 1 IP_ON EN = high VLDOIN 1 65 +6 150 +65 ILDOIN_OFF EN = low, IA = 0A 75 125 ILDOIN_ON EN = high, IA = 0A 350 500 +5 +5.25 VA VA supply externally, VA = VLDOIN +4.75 IA_OFF EN = low, VA = VLDOIN 50 75 IA_ON EN = high, VA = VLDOIN 350 450 VL Supply Voltage VL VL Supply Current IL Maxim Integrated +6 +1.62 All logic inputs static, held at logic-low or logic-high 2.5 FA V FA V FA +5.5 V 5 FA 2 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs DC ELECTRICAL CHARACTERISTICS (continued) (VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER VP UVLO UVLO Hysteresis LDOIN UVLO SYMBOL UV_VPVTH CONDITIONS MIN VP rising UV_VPHYST UV_LDOINVT TYP MAX UNITS +6 V 200 VLDOIN rising +5.25 mV +6 V VA UVLO UV_VAVTH VA rising +4.7 V VL UVLO UV_VLVTH VL rising +1.6 V +5.25 V VA V 200 I LDO Output Voltage VA_LDO_OUT 0 < ILOAD < 10mA +4.75 +5 ANALOG INPUTS (T1, T2, T3) Input Signal Range On-Resistance VT Reference to AGND 0 RONA T_ route to buffer amplifier -1 +1 T_ route to AOUT -1 +1 ILT_ Hold phase, SAMPL = low -1 +1 FA Differential Input Signal Range for Guaranteed Accuracy VDn VCVn – VCVn-1 (Note 3) +0.5 +4.5 V CV1 Input Voltage Range VCV1 0 +5 V CV2–CV12 Input Voltage Range (MAX14920) VCVn n ≥ 2, VCVn ≥ VCVn-1 (Note 3) +1.5 +65 V CV2–CV16 Input Voltage Range (MAX14921) VCVm m ≥ 2, VCVm ≥ VCVm-1 (Note 3) +1.5 +65 V Input Leakage Current IT_LEAK FA CAPACITOR INPUTS (CT_) Capacitor Discharge Current ANALOG INPUTS (CV_) Input Leakage Current Balancing Input Current Sample Switch On-Resistance ILS_ During sampling phase -1 +1 ILH_ During holding phase -1 +10 ILC_ During calibration -1 +10 ILD_ During diagnostics, DIAG = 1 10 ILB_ BA_ active, VCVn - VCVn-1 = +4.5V (Note 3) 6.5 12 VCVn > +2V, ISINK = 2mA (Note 3) 80 150 VCVn > +1.5V, ISINK = 1mA (Note 3) 90 VCVn > +2V, ISINK = 2mA (Note 3) 800 16,000 +1.5 +1.6 RSAMPLE RSWCAL Cell Undervoltage Threshold UV_VCVTH Cell Overvoltage Threshold OV_VCVTH Maxim Integrated An undervoltage sets the associated SPI Cn bit An overvoltage sets the associated SPI Cn bit +1.4 VA FA mA I V V 3 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs DC ELECTRICAL CHARACTERISTICS (continued) (VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VA - 0.3 V Q100 FV ANALOG OUTPUT (AOUT) Output Signal Range Amplifier Offset Voltage VAOUT VOFFSET Temperature Offset Drift Gain Output Error A_V VO_ERR Reference to AGND +0.3 VAOUT = +3.3V, after self-calibration (Note 5) Q50 If not recalibrated Q1.5 FV/°C Gain = VAOUT/VD 1 V/V (Note 4) -0.5 +0.5 mV ROUT = 100kI, VD = 2V to 4.5V (Note 6) -0.2 +0.2 mV Amplifier Gain Error VGAIN_ERR VP Monitor Voltage VPMON [SC0, SC1, SC2, SC3] = [0, 0, 1, 1] VP Monitor Accuracy VPMONA [SC0, SC1, SC2, SC3] = [0, 0, 1, 1] MAX14920 VP/12 MAX14921 VP/16 -0.25 0 V +2.5 % CHARGE-BALANCE DRIVERS (BA_) Output Low VBAL IBA_ = 1mA, VCV(n) - VCV(n - 1) = +3.3V (Note 3) VCV(n - 1) Output High VBAH IBA_ = -1mA, VCV(n) - VCV(n - 1) = +3.3V (Note 3) VCV(n) - 1.5 Pulldown Resistance RPDWN 0.65 VCV(n - 1) + 0.9 V VCV(n) V 0.9 kI +0.9 V LOGIC OUTPUT (SDO) Output Low Voltage VOL ISINK = 10mA Output High Voltage VOH ISOURCE = 0.5mA Output Leakage Current IL VCS = VL VL - 0.25 V -1 +1 FA LOGIC INPUTS (SDI, SCLK, EN, SAMPL) Input Low Voltage VIL Input High Voltage VHL Input Leakage Current VL < +2.3V 0.2 x VL +2.3V < VL < +5.5V 0.3 x VL VL < +2.3V 0.8 x VL +2.3V < VL < +5.5V 0.7 x VL IL V V -1 +1 FA DYNAMIC CHARACTERISTICS AOUT Settling Time Sampling Time Holding Delay Time Maxim Integrated tSET tSAMPL tHD Measured between channels with +4V signal change. Settling to Q1mV accuracy, CLOAD = 100pF (Figure 1) 5 CSAMPLE = 1FF 4 CSAMPLE = 1FF, error calibration 40 Delay from SMPLB set to 1 or SAMPL falling edge to holding of all cell voltages Fs ms 0.5 Fs 4 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs DC ELECTRICAL CHARACTERISTICS (continued) (VP = +65V, DGND = AGND, VL = VEN = +3.3V, VA = +5V, CSAMPLE = 1FF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER Level-Shifting Delay Time AOUT Voltage-Droop Time SYMBOL CONDITIONS tLS_DELAY Delay from SMPLB set to 1 or SAMPL falling edge to shifting of all cell voltages to ground and available for reading tDROOP T_ Settling Time tTS T_ Turn-On Delay Time tTD VP Settling Time tVPS Droop to -1mV (Figure 2) MIN TYP MAX UNITS 25 50 Fs 1 Measured between T_ input selection and AOUT settling to +1mV accuracy, CLOAD = 100pF, SC2 = 1 ms 5 Measured between VP/12 (MAX14920), VP/16 (MAX14921) input selection and AOUT, settling to 2.5%, CLOAD = 100pF, SC3 = 1 25 Self-Calibration Time Fs 0.2 Fs 60 Fs 8 ms THERMAL DETECTION Thermal Shutdown Thermal-Shutdown Hysteresis +140 °C 15 °C SPI TIMINGS (Figure 3) SDI to SCLK Setup tDS 50 ns SDI to SCLK Hold tDH 12 ns SCLK to SDO Valid tDO 100 ns CS Fall to SDO Enable tDV 100 ns CS Rise to SDO Disable tTR 80 ns tCSW 50 CS Fall to SCLK Rise Setup tCSS 100 CS Rise to SCLK Rise Hold tCSH SCLK High Pulse Width tCH 65 ns SCLK Low Pulse Width tCL 65 ns SCLK Period tCP 208 ns CS Pulse Width ns ns 0 ns Note 2: All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design. Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Note 4: Output error VO_ERR is the difference between the input cell difference voltage (VD = VCV(n) - VCV(n - 1)) and the output voltage VAOUT. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer amplifier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the Measurement Accuracy section for a detailed explanation). Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after power-up phase, it is suggested to run self-calibration on a regular basis to get best performance (see the Buffer Amplifier Offset Calibration section for a detailed explanation). Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error. Maxim Integrated 5 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Timing Diagrams tSET CS SCLK SDI C1 C2 C3 C4 C16 T1 T2 T3 OT AOUT 0V *n = 1–12 (MAX14920) AND n = 1–16 (MAX14921) Figure 1. AOUT Delay from SPI Select tDROOP tSAMPL SAMPL VCVn* 1mV AOUT *n = 1–12 (MAX14920) and n = 1–16 (MAX14921) Figure 2. AOUT Voltage-Droop Time CS tCH tCSS tCSH tCL SCLK tDS tDH SDI tDV tDO tTR SDO Figure 3. SPI Timing Maxim Integrated 6 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Typical Operating Characteristics (VCVn - VCV(n - 1) = +3.3V (where n = 1–12 (MAX14920) and n = 1–16 (MAX14921)), TA = +25°C, unless otherwise noted.) 40 TA = +25°C 30 IP (µA) TA = +85°C TA = -40°C VP = 65V 30 20 20 10 10 0 0 VP = 24V VP = 6V 0.5 VP = 10V 0.4 CHANGE IN OUTPUT VOLTAGE (%) SAMPLE MODE LDO DISABLED 50 40 IP (µA) MAX14920 toc02 SAMPLE MODE LDO DISABLED 50 60 MAX14920 toc01 60 LDO OUTPUT VOLTAGE CHANGE vs. LOAD CURRENT IP vs. TEMPERATURE MAX14920 toc03 IP vs. VP 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 25 45 65 60 0 2 4 6 8 VAOUT DROOP TIME vs. TEMPERATURE 0 VCVn-1 = 0V -0.2 4 3 2 tSAMPLE = 4ms VCVn - VCVn-1 = 1.5V VP = 24V SETTLE TO 1mV 1 -0.3 tSAMPLE = 4ms 0 -0.4 0.5 1.5 2.5 3.5 -40 4.5 -15 10 35 60 MAX14920 toc06 MAX14920 toc05 5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 tSAMPLE = 4ms VCVn - VCVn-1 = 1.5V VP = 24V 0.5 0 85 -40 -15 10 35 TA (°C) TA (°C) T_ ON-RESISTANCE vs. VT_ VBAn - VCVn-1 vs. IBAn VL SUPPLY CURRENT vs. TEMPERATURE VBAn - VCVn-1 (V) 140 3.0 120 100 80 60 VOH 2.5 2.0 1.5 1.0 40 0 1 2 3 VT_ (V) Maxim Integrated 4 5 4.0 VL = 5V 3.5 3.0 2.5 VL = 3.3V 2.0 1.5 VL = 1.8V 0.5 VCVn - VCVn-1 = 3.3V IT_ = 0.1mA 0 SAMPL = VL 4.5 1.0 0.5 20 5.0 VL SUPPLY CURRENT (µA) 160 MAX14920 toc08 3.5 MAX14920 toc07 180 85 60 CELL VOLTAGE (V) 200 10 5.0 VAOUT DROOP TIME (ms) VCVn-1 = 20V 6 VAOUT SETTLING TIME (µs) MAX14920 toc04 VAOUT SETTLING TIME vs. TEMPERATURE VCVn-1 = 60V 0 -0.5 85 VOLTAGE ERROR vs. CELL VOLTAGE 0.2 ERROR (mV) 35 IOUT (mA) 0.3 RON (I) 10 TA (°C) VCVn-1 = 40V -0.1 -15 VP (V) 0.4 0.1 -40 MAX14920 toc09 5 0 0 1 2 3 IBAn (mA) 4 5 -40 -15 10 35 60 85 TA (°C) 7 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Configurations CT8 CB8 CV7 CT7 BA7 CB7 CV6 BA6 CT6 CB6 CV5 BA5 CT5 CB5 BA4 CV4 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CT4 49 32 BA8 CB4 50 31 CV8 CV3 51 30 CB9 BA3 52 29 CT9 CT3 53 28 BA9 CB3 54 27 CV9 CV2 55 26 CB10 BA2 56 25 CT10 MAX14920 CT2 57 24 BA10 CB2 58 23 CV10 CV1 59 22 CB11 BA1 60 21 CT11 20 BA11 CT1 61 *EP CV0 62 EN 63 19 CV11 18 CB12 + BA12 VP CV12 LDOIN 10 11 12 13 14 15 16 VA 9 AGND 8 AOUT 7 T1 VL 6 T2 5 T3 4 DGND 3 SDO 2 SAMPL 1 SDI 17 CT12 SCLK CS 64 64 TQFP-EP (10mm x 10mm) *CONNECT EP TO GND Maxim Integrated 8 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Configurations (continued) CT10 CB10 CV9 BA9 CT9 CB9 CV8 BA8 CT8 CB8 CV7 BA7 CT7 CB7 CV6 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BA6 CV5 60 CT6 BA5 CB6 TOP VIEW CT5 61 40 BA10 CB5 62 39 CV10 CV4 63 38 CB11 BA4 64 37 CT11 CT4 65 36 BA11 CB4 66 35 CV11 CV3 67 34 CB12 BA3 68 33 CT12 CT3 69 CB3 70 32 BA12 31 CV12 MAX14921 CV2 71 30 CB13 BA2 72 29 CT13 CT2 73 28 BA13 CB2 74 27 CV13 CV1 75 26 CB14 BA1 76 25 CT14 77 24 BA14 CV0 78 23 CV14 EN 79 22 CB15 CT1 CS 80 21 CT15 SAMPL VL DGND T3 T2 T1 BA15 SDO CV15 SDI 10 11 12 13 14 15 16 17 18 19 20 CB16 9 CT16 8 BA16 7 CV16 6 VP 5 LDOIN 4 VA 3 AGND 2 AOUT 1 SCLK + 80 TQFP (12mm x 12mm) Maxim Integrated 9 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Description PIN MAX14920 (64 TQFP-EP) MAX14921 (80 TQFP) NAME 1 1 SCLK 2 2 SDI SPI Data Line Input 3 3 SDO SPI Data Line Output 4 4 SAMPL 5 5 VL 6 6 DGND 7 7 T3 Single-Ended Voltage Input. T3 can be connected to a temperature sensor or other analog voltage. 8 8 T2 Single-Ended Voltage Input. T2 can be connected to a temperature sensor or other analog voltage. 9 9 T1 Single-Ended Voltage Input. T1 can be connected to a temperature sensor or other analog voltage. 10 10 AOUT Buffered Amplifier Output 11 11 AGND Analog Ground. AGND is a low-noise ground. Connect CV0 to AGND. Connect DGND to AGND. 12 12 VA +5V LDO Output. Bypass VA to AGND with a 1FF capacitor as close as possible to the device. 13 13 LDOIN +5V LDO Power Supply. Connect LDOIN to VP to enable the LDO. Connect LDOIN to VA to disable the LDO and use an external +5V supply. 14 14 VP Power Supply. Connect to the highest voltage of the battery cell stack. Bypass VP to AGND with a 0.1FF capacitor as close as possible to the device. 15 31 CV12 Cell Voltage Input 12. Connect CV12 to cell anode/cathode. Connect CV12 to the highest voltage of the battery cell stack if not used. 16 32 BA12 Cell-Balancing Gate Driver Output 12. Connect BA12 to the gate of the external n-channel FET. Leave BA12 unconnected if not used. 17 33 CT12 Sampling Capacitor 12 High Terminal. CT12 internally connects to CV12 when SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave CT12 unconnected if not used. 18 34 CB12 Sampling Capacitor 12 Low Terminal. CB12 internally connects to CV11 when SAMPL is logic-high. Connect a 1FF capacitor between CT12 and CB12. Leave CB12 unconnected if not used. 19 35 CV11 Cell Voltage Input 11. Connect CV11 to cell anode/cathode. Connect CV12 to the highest voltage of the battery cell stack if not used. 20 36 BA11 Cell-Balancing Gate Driver Output 11. Connect BA11 to the gate of the external n-channel FET. Leave BA11 unconnected if not used. Maxim Integrated FUNCTION SPI Clock Input Sample Control Input. Voltages at CV_ inputs are tracked when SAMPL is logichigh. When SAMPL transitions from high to low, the differential voltages on CV_ are held internally and made ready for readout at the AOUT output. Logic Supply Input. Bypass VL to DGND with a 0.1FF capacitor as close as possible to the device. Digital Ground 10 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Description (continued) PIN MAX14920 (64 TQFP-EP) MAX14921 (80 TQFP) NAME 21 37 CT11 Sampling Capacitor 11 High Terminal. CT11 internally connects to CV11 when SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave CT11 unconnected if not used. 22 38 CB11 Sampling Capacitor 11 Low Terminal. CB11 internally connects to CV10 when SAMPL is logic-high. Connect a 1FF capacitor between CT11 and CB11. Leave CB11 unconnected if not used. 23 39 CV10 Cell Voltage Input 10. Connect CV10 to cell anode/cathode. Connect CV10 to the highest voltage of the battery cell stack if not used. 24 40 BA10 Cell-Balancing Gate Driver Output 10. Connect BA10 to the gate of the external n-channel FET. Leave BA10 unconnected if not used. 25 41 CT10 Sampling Capacitor 10 High Terminal. CT10 internally connects to CV10 when SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave CT10 unconnected if not used. 26 42 CB10 Sampling Capacitor 10 Low Terminal. CB10 internally connects to CV9 when SAMPL is logic-high. Connect a 1FF capacitor between CT10 and CB10. Leave CB10 unconnected if not used. 27 43 CV9 Cell Voltage Input 9. Connect CV9 to cell anode/cathode. Connect CV9 to the highest voltage of the battery cell stack if not used. 28 44 BA9 Cell-Balancing Gate Driver Output 9. Connect BA9 to the gate of the external n-channel FET. Leave BA9 unconnected if not used. 29 45 CT9 Sampling Capacitor 9 High Terminal. CT9 internally connects to CV9 when SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CT9 unconnected if not used. 30 46 CB9 Sampling Capacitor 9 Low Terminal. CB9 internally connects to CV8 when SAMPL is logic-high. Connect a 1FF capacitor between CT9 and CB9. Leave CB9 unconnected if not used. 31 47 CV8 Cell Voltage Input 8. Connect CV8 to cell anode/cathode. Connect CV8 to the highest voltage of the battery cell stack if not used. 32 48 BA8 Cell-Balancing Gate Driver Output 8. Connect BA8 to the gate of the external n-channel FET. Leave BA8 unconnected if not used. 33 49 CT8 Sampling Capacitor 8 High Terminal. CT8 internally connects to CV8 when SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CT8 unconnected if not used. 34 50 CB8 Sampling Capacitor 8 Low Terminal. CB8 internally connects to CV7 when SAMPL is logic-high. Connect a 1FF capacitor between CT8 and CB8. Leave CB8 unconnected if not used. 35 51 CV7 Cell Voltage Input 7. Connect CV7 to cell anode/cathode. Connect CV7 to the highest voltage of the battery cell stack if not used. Maxim Integrated FUNCTION 11 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Description (continued) PIN MAX14920 (64 TQFP-EP) MAX14921 (80 TQFP) NAME 36 52 BA7 Cell-Balancing Gate Driver Output 7. Connect BA7 to the gate of the external n-channel FET. Leave BA7 unconnected if not used. 37 53 CT7 Sampling Capacitor 7 High Terminal. CT7 internally connects to CV7 when SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CT7 unconnected if not used. 38 54 CB7 Sampling Capacitor 7 Low Terminal. CB7 internally connects to CV6 when SAMPL is logic-high. Connect a 1FF capacitor between CT7 and CB7. Leave CB7 unconnected if not used. 39 55 CV6 Cell Voltage Input 6. Connect CV6 to cell anode/cathode. Connect CV6 to the highest voltage of the battery cell stack if not used. 40 56 BA6 Cell-Balancing Gate Driver Output 6. Connect BA6 to the gate of the external n-channel FET. Leave BA6 unconnected if not used. 41 57 CT6 Sampling Capacitor 6 High Terminal. CT6 internally connects to CV6 when SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CT6 unconnected if not used. 42 58 CB6 Sampling Capacitor 6 Low Terminal. CB6 internally connects to CV7 when SAMPL is logic-high. Connect a 1FF capacitor between CT6 and CB6. Leave CB6 unconnected if not used. 43 59 CV5 Cell Voltage Input 5. Connect CV5 to cell anode/cathode. Connect CV5 to the highest voltage of the battery cell stack if not used. 44 60 BA5 Cell-Balancing Gate Driver Output 5. Connect BA5 to the gate of the external n-channel FET. Leave BA5 unconnected if not used. 45 61 CT5 Sampling Capacitor 5 High Terminal. CT5 internally connects to CV5 when SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CT5 unconnected if not used. 46 62 CB5 Sampling Capacitor 5 Low Terminal. CB5 internally connects to CV4 when SAMPL is logic-high. Connect a 1FF capacitor between CT5 and CB5. Leave CB5 unconnected if not used. 47 63 CV4 Cell Voltage Input 4. Connect CV4 to cell anode/cathode. Connect CV4 to the highest voltage of the battery cell stack if not used. 48 64 BA4 Cell-Balancing Gate Driver Output 4. Connect BA4 to the gate of the external n-channel FET. Leave BA4 unconnected if not used. 49 65 CT4 Sampling Capacitor 4 High Terminal. CT4 internally connects to CV4 when SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CT4 unconnected if not used. 50 66 CB4 Sampling Capacitor 4 Low Terminal. CB4 internally connects to CV3 when SAMPL is logic-high. Connect a 1FF capacitor between CT4 and CB4. Leave CB4 unconnected if not used. Maxim Integrated FUNCTION 12 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Description (continued) PIN MAX14920 (64 TQFP-EP) MAX14921 (80 TQFP) NAME 51 67 CV3 Cell Voltage Input 3. Connect CV3 to cell anode/cathode. Connect CV3 to the highest voltage of the battery cell stack if not used. 52 68 BA3 Cell-Balancing Gate Driver Output 3. Connect BA3 to the gate of the external n-channel FET. Leave BA3 unconnected if not used. 53 69 CT3 Sampling Capacitor 3 High Terminal. CT3 internally connects to CV3 when SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CT3 unconnected if not used. 54 70 CB3 Sampling Capacitor 3 Low Terminal. CB3 internally connects to CV2 when SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CB3 unconnected if not used. 55 71 CV2 Cell Voltage Input 2. Connect CV2 to cell anode/cathode. Connect CV2 to the highest voltage of the battery cell stack if not used. 56 72 BA2 Cell-Balancing Gate Driver Output 2. Connect BA2 to the gate of the external n-channel FET. Leave BA2 unconnected if not used. 57 73 CT2 Sampling Capacitor 2 High Terminal. CT2 internally connects to CV2 when SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CT2 unconnected if not used. 58 74 CB2 Sampling Capacitor 2 Low Terminal. CB2 internally connects to CV1 when SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CB2 unconnected if not used. 59 75 CV1 Cell Voltage Input 1. Connect CV1 to cell anode/cathode. 60 76 BA1 Cell-Balancing Gate Driver Output 1. Connect BA1 to the gate of the external n-channel FET. Leave BA1 unconnected if not used. 61 77 CT1 Sampling Capacitor Connection 1 High Terminal. CT1 internally connects to CV1 when SAMPL is logic-high. Connect a 1FF capacitor between CT1 and CV0. Leave CT1 unconnected if not used. 62 78 CV0 Cell Voltage Input 0. Connect CV0 to AGND. 63 79 EN Enable Input. Drive EN low to put the device into shutdown mode and reset the SPI registers. The +5V LDO remains active in the shutdown mode. Drive EN high for normal operation. 64 80 CS SPI Chip-Select Input. Active low. — 15 CV16 Cell Voltage Input 16. Connect CV16 to cell anode/cathode. Connect CV16 to the highest voltage of the battery cell stack if not used. — 16 BA16 Cell-Balancing Gate Driver Output 16. Connect BA16 to the gate of the external n-channel FET. Leave BA16 unconnected if not used. — 17 CT16 Sampling Capacitor Connection 16 High Terminal. CT16 internally connects to CV16 when SAMPL is logic-high. Connect a1FF capacitor between CT16 and CB16. Leave CT16 unconnected if not used. Maxim Integrated FUNCTION 13 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Pin Description (continued) PIN MAX14920 (64 TQFP-EP) MAX14921 (80 TQFP) NAME FUNCTION — 18 CB16 Sampling Capacitor Connection 16 Low Terminal. CB16 internally connects to CV15 when SAMPL is logic-high. Connect a 1FF capacitor between CT16 and CB16. Leave CB16 unconnected if not used. — 19 CV15 Cell Voltage Input 15. Connect CV15 to cell anode/cathode. Connect CV15 to the highest voltage of the battery cell stack if not used. — 20 BA15 Cell-Balancing Gate Driver Output 15. Connect BA15 to the gate of the external n-channel FET. Leave BA15 unconnected if not used. — 21 CT15 Sampling Capacitor Connection 15 High Terminal. CT15 internally connects to CV15 when SAMPL is logic-high. Connect a 1FF capacitor between CT15 and CB15. Leave CT15 unconnected if not used. — 22 CB15 Sampling Capacitor Connection 15 Low Terminal. CB15 internally connects to CV14 when SAMPL is logic-high. Connect a 1FF capacitor between CT15 and CB15. Leave CB15 unconnected if not used. — 23 CV14 Cell Voltage Input 14. Connect CV14 to cell anode/cathode. Connect CV14 to the highest voltage of the battery cell stack if not used. — 24 BA14 Cell-Balancing Gate Driver Output 14. Connect BA14 to the gate of the external n-channel FET. Leave BA14 unconnected if not used. — 25 CT14 Sampling Capacitor Connection 14 High Terminal. CT14 internally connects to CV14 when SAMPL is logic-high. Connect a 1FF capacitor between CT14 and CB14. Leave CT14 unconnected if not used. — 26 CB14 Sampling Capacitor Connection 14 Low Terminal. CB14 internally connects to CV13 when SAMPL is logic-high. Connect a 1FF capacitor between CT14 and CB14. Leave CB14 unconnected if not used. — 27 CV13 Cell Voltage Input 13. Connect CV13 to cell anode/cathode. Connect CV13 to the highest voltage of the battery cell stack if not used. — 28 BA13 Cell-Balancing Gate Driver Output 13. Connect BA13 to the gate of the external n-channel FET. Leave BA13 unconnected if not used. — 29 CT13 Sampling Capacitor Connection 13 High Terminal. CT13 internally connects to CV13 when SAMPL is logic-high. Connect a 1FF capacitor between CT13 and CB13. Leave CT13 unconnected if not used. — 30 CB13 Sampling Capacitor Connection 13 Low Terminal. CB13 internally connects to CV12 when SAMPL is logic-high. Connect a 1FF capacitor between CT13 and CB13. Leave CB13 unconnected if not used. — — EP Maxim Integrated Exposed Pad (MAX14920 Only). Connect EP to AGND. 14 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Detailed Description The MAX14920/MAX14921 analog front-end devices are used in multicell battery measurement systems to monitor primary/secondary battery packs up to 16 cells/+65V (max). The devices perform the signal conditioning required for enabling accurate cell voltage measurement. Both devices simultaneously sample all cell voltages, allowing accurate state-of-charge and source-resistance determination, even under transient load current conditions. The cell voltage measurements are shifted down to ground reference with unity gain, simplifying external ADC data conversion. The devices enable passive cell balancing through drivers that control external discharge FETs. A high-accuracy, low-offset amplifier buffers differential voltages up to +5V for monitoring of the common rechargeable cell technologies such as lithium-ion (Li+). The resulting cell measurement errors from the devices are below Q0.5mV (max). The devices’ high accuracy make them ideal for monitoring cell chemistries with very flat discharge curves, such as a lithium-metal phosphate cell. Diagnostics detect open-wire and short conditions, and warn about overvoltage/undervoltage. The SPI interface is used for control and monitoring through a host controller. The SPI interface is daisychainable. Both devices can operate with a minimum of +6V total stack voltage (typically equating to 3 cells). the filter and settling times. In the holding phase, each capacitor’s voltage can be independently routed to the analog AOUT output under SPI control. Voltage Readout When the SMPLB bit is set high, or when the SAMPL input is driven low, the sampling switches are opened after 0.5Fs (typ) and the cell voltages are held on the external sampling capacitors. Within the time of tLS_DELAY < 50Fs (max), the capacitors’ voltages are all shifted to ground reference. Then the undervoltage/overvoltage monitoring of all cells is valid and the cell voltage is available for sequential readout under SPI control. The SPI control can select the readout of any cell voltages, in any order (Figure 5). With the ECS bit set to 1, a selected cell’s voltage appears at the AOUT output according to the cell selection (as defined by the SC_ cell select bits). A low-leakage, lownoise, low-offset amplifier buffers the capacitor charge and provides the high-accuracy AOUT analog output. After a settling time of tSET, from the rising edge of the CS signal, the voltage is available at AOUT with specified accuracy. An ADC can then sample and convert the AOUT voltage. The AOUT output voltage droops over time due to capacitor discharge. The droop time for 1mV of change is larger than tDROOP (> CSAMPLE/ICT_LEAK). CSAMPLE Voltage Sampling The voltages of all cells are tracked by the sampling capacitors connected between the CTn and CBn pins (where n = 1–12 (MAX14920) and n = 1–16 (MAX14921)), while the SMPLB bit is set to 0 and the SAMPL input is driven high (Figure 4). When the SMPLB bit is set to 1, and the SAMPL input transitions low, all cell voltages are simultaneously sampled on their associated capacitors. The voltages are held by the capacitors while the SMPLB bit is 1, or the SAMPL pin is held low. When sample and holding is controlled by the SAMPL input, set the SMPLB bit to 0. When sample and hold is controlled by the SMPLB bit, keep the SAMPL input high. CTn* CBn* CVn* CVn* - 1 MAX14920 MAX14921 SAMPL SMPLB In sample phase selecting any cell voltage (ECS = 1), AOUT equals VP/12 (MAX14920) or VP/16 (MAX14921). Resistors can be placed in series with the CV_ inputs to filter transients and/or for protection. Consider the switches’ on-resistance of 150I (max) when calculating Maxim Integrated *n = 1–12 (MAX14920) and n = 1–16 (MAX14921) Figure 4. Voltage Sampling 15 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs SAMPLE PHASE HOLD PHASE tSAMPL HOLD DELAY LEVEL SHIFT tD_H tD_LS SETTLING SELECT CELL a tSET CONVERT SELECT CELL a CELL b tSET CONVERT SELECT CELL b CELL c CONVERT SELECT CELL m CELL n tSET CONVERT CELL n = VOLTAGE READY = SPI ACTIVITY = ADC CONVERSION Figure 5. SPI Control Cells Voltage Readout Measurement Accuracy The accuracy of cell voltage monitoring (i.e., the difference of the AOUT voltage relative to the cell voltages) is determined by three factors: 1) Held voltage droop due to leakage on the CT_ pins 2) Internal buffer amplifier’s voltage errors 3) Capacitive level-shifting circuit error The CT_ leakage (1FA, max) is a current that mainly comes from the CV_ pin and increases with temperature. Neglecting the PCB leakage across the sampling capacitance, the voltage drift error is given by: VERR_LEAK = I CT_LEAK C SAMPLE x t READOUT The buffer amplifier errors are nondeterministic in nature, and vary from chip to chip. They are also affected by temperature. The buffer amplifier offset error can be calibrated out through an internal offset-calibration function. This calibration is automatically performed at power-up. The calibration can also be initiated under SPI control. Due to temperature drifts over time, it is best done on a regular basis. Once the buffer amplifier offset is calibrated out, the total error of the buffer is below 0.3mV. After power-up, if the devices do not calibrate regularly, a temperature offset drift of Q1.5FV/NC can occur. The level shifting is subject to deterministic errors due to charge injection by parasitic PCB-related capacitance on the CT_ pins. The charge-injected sampling error can be calculated as follows: where: CSAMPLE is the sampling capacitance ICT_LEAK is the leakage current on the CT_ pin tREADOUT is the delay between hold starts and readout of the cell voltage For example, with 1FF sampling capacitors and an ADC conversion rate > 20kHz, VERR_LEAK is less than 1mV. Cells with a higher common-mode voltage have a higher leakage. To reduce the voltage drift over time, start sequential voltage readout from the highest cell in the stack first. Maxim Integrated VERR_CHARGE_INJECTION = C PAR 1 x VCTn x t /(2R x C ) − SW SAMPLE C SAMPLE 1 − e SAMPL where: CPAR is the parasitic capacitance of the CTn pin, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921) CSAMPLE is the sampling capacitor RSW is the sampling switch resistance VCTn is the voltage of the CTn pin with respect to AGND, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921) tSAMPL is the sampling time 16 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs each of the 12/16 cells at AOUT, multiplied by 128. If VERR__CHARGE_INJECTION is large enough to affect the required 1mV accuracy, this calibration method provides a measurement of the parasitic capacitance on each CT_ pin so the microcontroller can use this to correct VERR_INJECTION in its readings. OUTPUT ERROR vs. SAMPLING TIME OUTPUT ERROR (mV) 100.0 VCn = 65V VC = 4.5V CSAMPL = 1µF CPAR = 1pF 10.0 Different correction algorithms are possible for the microcontroller using the calibration readout voltages. A simple way to correct cell voltages is to store the ADC data of each cell obtained during calibration (i.e., error values), divided by 128, and subtract these from the subsequently measured cell voltages. 1.0 0.1 0 1 2 3 4 5 6 7 8 9 10 tSAMPL (ms) Figure 6. Charge Injection Sampling Error Voltage for 1pF Parasitic Capacitance Figure 6 shows the charge-injected sampling error for 1pF of parasitic capacitance in worst-case conditions for a 1FF sampling capacitor. Minimizing the parasitic capacitance on the CT_ pins to a few picofarads, with a sampling capacitor of 1FF, is enough to achieve output error below 1mV target. This error can be further reduced by increasing the sampling capacitor value and consequently increasing the sampling time. Alternatively, if a sampling capacitor lower than 1FF or a parasitic capacitance of more than 15pF are present, these errors can be calibrated out to achieve a < 1mV accuracy level through a calibration procedure for each cell. These per-cell errors are simply subtracted from every cell voltage measurement (see the Parasitic Capacitance Charge Injection Error Calibration section). Parasitic Capacitance Charge Injection Error Calibration This calibration is performed with all cells connected to the CV_ terminals. Setting the [ECS, SC0, SC1, SC2, SC3] bits to [0, 0, 0, 0, 0] configure the devices for parasitic capacitance charge-injection error calibration. During the sampling phase, every capacitor’s terminals are shorted by an internal calibration sampling switch (RSWCAL = 800I typ), so that only the parasitic capacitance is charged to the cell’s common-mode voltage VCTn, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). The subsequent cell voltage readout sequence then shows the value of VERR_CHARGE_INJECTION for Maxim Integrated Buffer Amplifier Offset Calibration On power-up, the devices automatically go through a self-calibration phase to minimize the internal buffer’s offset voltage. In addition, the offset voltage can be calibrated out at any time under host control. Offset calibration is configurable by setting the [ECS, SC0, SC1, SC2, SC3] bits to [0, 1, 0, 0] and is initiated on the low to high CS transition in sampling phase. This offset-calibration procedure takes 8ms to complete. The AOUT output is high impedance during this period. No regular cell voltage measurement can be taken during this time period. However, the SPI operates normally when communicating with other devices (e.g., in daisy-chain mode). So as not to affect calibration, do not take measurement and keep the devices in sample mode (ECS = 0, SC2 = 0, SMPLB = 0). After power-up, if the devices do not calibrate regularly, a temperature offset drift of Q1.5FV/°C can occur. Monitoring Less Than 12/16 Cells The devices can monitor from 3 (VP > +6V) to 12/16 cells (VP < +65V). When monitoring less than the maximum number of possible cells per device, connect the most negative cell stack voltage to the bottom of the voltage input string (CV0). The unused CV_ inputs at the top of the string should be shorted together and connected to VP. Leave the unused BA_, CT_ , and CB_ pins unconnected. Reading Total Cell Stack Voltage Besides monitoring the individual cell voltages, the devices can monitor the total voltage of the cell stack. An internal resistive voltage-divider between VP and AGND divides the stack voltage by 12 (MAX14920) or 16 (MAX14921). This provides a way to quickly determine the state of the total battery pack, as well as the average voltage of all cells. The settling time of AOUT is 60Fs. To 17 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs read out the total cell stack voltage, set the [ECS, SC0, SC1, SC2, SC3] bits to [0, 0, 0, 1, 1]. The total cell stack voltage can be read during the sample or hold phase. SPI Serial Interface Control of the devices is done through a 24-bit SPI interface. The controller sends the serial data to the devices through the SDI input. The devices simultaneously send out monitoring data at the SDO output. This scheme allows daisy-chained operation with other daisy-chainable devices, such as ADC converters. Figure 7 shows the serial bit sequence. CB1 is the first bit expected from the controller and C1 is the first bit that the devices sent to the controller. The SDO data changes on the falling edge of the SCLK signals. The devices sample the SDI data on the rising edge of SCLK. SPI Configuration/Control Bits The configuration/control bits allow enabling of the charge-balance switches, sampling and holding of all the cell voltages, selecting the cell for voltage output, selecting the T_ input channels, and enabling diagnostics mode. Table 1 describes the bits that the devices receive from the host controller for configuration and control through SDI. CS SCLK SDI X SDO CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 CB9 CB10 CB11 CB12 CB13 CB14 CB15 CB16 ECS SC0 SC1 SC2 SC3 SMPLB DIAG LOPW X C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 OP 0 OP 1 REV 0 REV 1 UV_VA UV_VP RDY OT X Figure 7. SPI Serial Interface Bits Table 1. SPI Configuration/Control Bits NAME BITS ACCESS RESET CB1 0 W 0 CB2 1 W 0 CB3 2 W 0 CB4 3 W 0 CB5 4 W 0 CB6 5 W 0 CB7 6 W 0 CB8 7 W 0 Maxim Integrated DESCRIPTION 0: Set BA1 output low 1: Set BA1 output high 0: Set BA2 output low 1: Set BA2 output high 0: Set BA3 output low 1: Set BA3 output high 0: Set BA4 output low 1: Set BA4 output high 0: Set BA5 output low 1: Set BA5 output high 0: Set BA6 output low 1: Set BA6 output high 0: Set BA7 output low 1: Set BA7 output high 0: Set BA8 output low 1: Set BA8 output high 18 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Table 1. SPI Configuration/Control Bits (continued) NAME BITS ACCESS RESET CB9 8 R/W 0 CB10 9 R/W 0 CB11 10 R/W 0 CB12* 11 R/W 0 CB13* 12 R/W 0 CB14* 13 R/W 0 CB15* 14 R/W 0 CB16* 15 R/W 0 ECS 16 R/W 0 SC0 17 R/W 0 SC1 18 R/W 0 SC2 19 R/W 0 SC3 20 R/W 0 SMPLB 21 R/W 0 DIAG 22 R/W 0 DESCRIPTION 0: Set BA9 output low 1: Set BA9 output high 0: Set BA10 output low 1: Set BA10 output high 0: Set BA11 output low 1: Set BA11 output high 0: Set BA12 output low 1: Set BA12 output high 0: Set BA13 output low 1: Set BA13 output high 0: Set BA14 output low 1: Set BA14 output high 0: Set BA15 output low 1: Set BA15 output high 0: Set BA16 output low 1: Set BA16 output high 0: Cell selection is disabled 1: Cell selection is enabled [ECS, SC0, SC1, SC2, SC3] 1 – SC0, SC1, SC2, SC3: Selects the cell for voltage readout during hold phase.** The selected cell voltage is routed to AOUT after the rising CS edge. See Table 2. 0 – 0, 0, 0, 0: AOUT is three-stated and sampling switches are configured for parasitic capacitance error calibration. 0 – 1, 0, 0, 0: AOUT is three-statedand self-calibration of buffer amplifier offset voltage is initiated after the following rising CS. 0 – SC0, SC1, 0, 1: Switches the T1, T2. T2 analog inputs directly to AOUT. See Table 3. 0 – 0, 0, 1, 1: VP/12 (MAX14920) or VP/16 (MAX14921) voltage is routed to AOUT on the next rising CS 0 – SC0, SC1, 1, 1: Routes and buffers the T1, T2. T3 to AOUT. See Table 3. 0: Device in sample phase if SAMPL input is logic-high 1: Device in hold phase 0: Normal operation 1: Diagnostic enable, 10FA leakage is sunk on all CV_ inputs (CV0–CV16). 0: Normal operation LOPW 23 R/W 0 1: Low-power mode enabled. Current into LDOIN is reduced to 125FA. Current into VP is reduced to 1FA. *Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920. **For the MAX14920, if n > 12, VAOUT = 0V. Maxim Integrated 19 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Table 2. Cell Selection CELL SC0 SC1 SC2 SC3 1 0 0 0 0 2 1 0 0 0 3 0 1 0 0 4 1 1 0 0 5 0 0 1 0 6 1 0 1 0 7 0 1 1 0 8 1 1 1 0 9 0 0 0 1 10 1 0 0 1 11 0 1 0 1 12 1 1 0 1 13* 0 0 1 1 14* 1 0 1 1 15* 0 1 1 1 16* 1 1 1 1 *For MAX14921 only. Table 3. Analog Input Selection Maxim Integrated T_ SC0 SC1 T1 1 0 T2 0 1 T3 1 1 20 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs SPI Monitoring Bits The monitoring bits provide feedback of undervoltage conditions and thermal shutdown, as well as indication when the devices are ready for operation after power-up. Table 4 describes the diagnostics/monitoring bits that the devices send back to the host controller through the SDO output. Flexible Logic Interface The serial/parallel logic control interface logic levels can be defined to be in a range between +1.62V (min) and +5.5V (max). The voltage applied to the VL pin defines the logic levels. Choose the VL voltage to match the controller and ADC’s I/O logic levels. Table 4. SPI Monitoring Bits NAME BITS ACCESS C1 0 R 1: During hold phase if cell 1 voltage is below UV_VCVTH or above VA DESCRIPTION C2 1 R 1: During hold phase if cell 2 voltage is below UV_VCVTH or above VA C3 2 R 1: During hold phase if cell 3 voltage is below UV_VCVTH or above VA C4 3 R 1: During hold phase if cell 4 voltage is below UV_VCVTH or above VA C5 4 R 1: During hold phase if cell 5 voltage is below UV_VCVTH or above VA C6 5 R 1: During hold phase if cell 6 voltage is below UV_VCVTH or above VA C7 6 R 1: During hold phase if cell 7 voltage is below UV_VCVTH or above VA C8 7 R 1: During hold phase if cell 8 voltage is below UV_VCVTH or above VA C9 8 R 1: During hold phase if cell 9 voltage is below UV_VCVTH or above VA C10 9 R 1: During hold phase if cell 10 voltage is below UV_VCVTH or above VA C11 10 R 1: During hold phase if cell 11 voltage is below UV_VCVTH or above VA C12* 11 R 1: During hold phase if cell 12 voltage is below UV_VCVTH or above VA C13* 12 R 1: During hold phase if cell 13 voltage is below UV_VCVTH or above VA C14* 13 R 1: During hold phase if cell 14 voltage is below UV_VCVTH or above VA C15* 14 R 1: During hold phase if cell 15 voltage is below UV_VCVTH or above VA C16* 15 R 1: During hold phase if cell 16 voltage is below UV_VCVTH or above VA OP0 16 R OP1 17 R Product identifying bits MAX14921 (OP0 = 0, OP1 = 0) MAX14920 (OP0 = 1, OP1 = 0) REV0 18 R REV1 19 R Die version MAX14920/MAX14921 version bits UV_VA 20 R 1: VA is below UV_VAVTH UV_VP 21 R 1: VP is below UV_VPVTH. If LOPW = 1, VP UVLO circuit is disabled and this bit is always set to 1 RDY 22 R 1: Device is not ready to operate (power-up phase or buffer amplifier is in self-calibration procedure) OT 23 R 1: Device is in thermal shutdown *Not available on the MAX14920. Setting the bit to 0 or 1 does not affect the operating of the MAX14920. Maxim Integrated 21 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Linear Regulator The internal linear regulator has LDOIN as its input voltage and regulates this down to +5V Q5% at the VA output with a load current of 10mA (max). The LDO is automatically enabled when LDOIN is above +5.5V. The internal LDO is short-circuit protected with a current limit higher than 14mA (22mA, typ). An external +5V regulator can be used instead of the internal one. When using an external +5V regular, LDOIN must be connected to VA. Thermal Protection The devices have thermal shutdown to protect them against thermal overheating. In thermal shutdown, the LDO, amplifier, and charge-balance circuitry stop operation. The SPI interface is functional in thermal shutdown. Shutdown Mode The devices can be placed into low standby-power shutdown mode through the LOPW bit. The internal LDO remains on and the amplifier disabled, bringing the VP supply current down to 1FA (max). Analog/Temperature Inputs The T1, T2, and T3 inputs are single-ended, CV0referenced, general-purpose analog inputs that are multiplexed to AOUT or to AOUT through a buffer (Figure 8). These inputs can be used for connection of temperature sensors or for a current monitor. The total mux and switch series resistance is less than 200I. In applications where the load current flowing to the AOUT output is so high that significant errors are introduced due to series resistance in the voltage source and/or the signal path, use the buffer amplifier to improve accuracy. Route the T_ inputs through the buffer to AOUT by setting the SPI bits [ECS, SC0, SC1, SC2, SC3] = [0, b, a, 1, 1]. Route the T_ inputs directly to the AOUT output by setting the bits [ECS, SC0, SC1, SC2, SC3 = [0, b, a, 0, 1]. Bits a and b select one of the three T_ inputs or three-state the AOUT output. Three-Stating the AOUT Output The AOUT output can be three-stated to share this pin with other external signal sources, such as additional temperature sensors. Use the ECS and SC_ bits to threestate the AOUT output. Charge Balancing Low-voltage enhancement-mode n-channel FETs can be connected for passive balancing of cells. Select low onresistance FETs with a VT less than VBAH. Connect the FETs between each cell’s anode and cathode through a current-limiting resistor in the drain (Figure 9). The charge-balancing FETs can be enabled through SPI control. An internal 600I (typ)/900I (max) pulldown resistor assures that the FET is normally switched off. When balancing is active, a leakage current of 5FA is sunk from CV_. In addition, an internal balancing current flowing from CVn to CVn - 1 of 10mA (max) is present, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). The power dissipation created by the internal current during balancing should be considered for total package power management. Diagnostics The devices’ integrated diagnostics allow detection of shorts between wires, as well as open-wire conditions of the CV_ pins. CVn* T1 T2 T3 RBAL AOUT BAL BUFFER CELLn* MAX14920 MAX14921 BAn* 600I SPI CONTROL CVn* - 1 *n = 1–12 (MAX14920) and n = 1–16 (MAX14921) Figure 8. Analog/ Temperature Measurement Maxim Integrated Figure 9. Charge Balancing 22 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Shorts between cell connections can be detected during normal operation. The cell readout voltage results in ~0V or ~VA depending on where the short happens. In the case of shorts, the maximum currents flowing in/out of the pins must be limited and overvoltages avoided, including the external components (balancing FETs and sampling capacitors). Open-wire conditions between the CV_ inputs and the cells can be detected in two different ways: The first method of open-wire detection: Set the DIAG bit to 1 while in the sampling phase. This applies a leakage current of 10FA to the CVn inputs. If CVn is unconnected, the leakage current starts discharging the sampling capacitor with a slew rate of ILEAK/ CSAMLPE (~10FA/1FF = 100mV/10ms) down to CVn - 1. Two successive readouts show considerable cell voltage change in case of an open wire. Alternatively, waiting for a sampling time of ~300ms to 500ms reduces the cell voltage to below the UV_VCVTH threshold voltage. First open-wire detection procedure: • Set DIAG bit to 1 • Wait > 0.5s before hold phase • Read out the Cn bit or the CVn voltage under SPI control, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921) The second method of open-wire detection: To check for a single open-wire connection, it is faster to enable the balancing FET only on the selected cell during the sampling phase and then reading out the selected cell voltage. If CVn is unconnected, the balancing FET rapidly (time depends on the balancing resistance used) shorts CVn to CVn - 1 and the readout phase shows ~0V or CVn and a voltage higher than VA on CVn + 1. Second open-wire detection procedure: • Set the BAn bit to 1 • Wait for a time of RBAL x CSAMPLE before switching to the hold phase • Route the CVn voltage to AOUT • Repeat this procedure for all cells During this procedure, the capacitors and external FETs need to withstand a voltage equal to VCVn - VCVn-1, where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Input-Voltage Clamping The devices have internal ESD-protection diodes that can clamp input voltage lower than AGND or higher than VP (CVn where n is > 1) or 6 volts for (CV1) during a fault condition. Connect series resistors (RLIM) to the inputs to limit the currents flowing through the forward-biased diodes during fault conditions (Figure 10). Choose current-limiting resistors so the input currents are limited to ICV_ (max) = 10mA. The additional power dissipation due to the fault currents needs to be calculated when a voltage-clamping condition occurs on another channel that is not being measured. Sampling capacitors and balancing FETs must be chosen appropriately or protected with external voltage clamps to survive such events. Power Sequencing The VA and VL supplies can be applied at any sequence with respect to each other and also independently of the VP and supplies CV_ inputs. The VP voltage has to connect to the highest voltage of the cell stack. MAX14920 MAX14921 VP RLIM CTn* CVn* RBAL BAn* RLIM CSAMPLE CBn* CVn*- 1 CV1 BA1 CV0 AGND *n = 1–12 (MAX14920) AND n = 1–16 (MAX14921) Figure 10. Input-Voltage Clamp Maxim Integrated 23 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Applications Information Sampling Speed and CapacitorSelection Considerations Capacitor values of 1FF are recommended for achieving low errors and at high sampling rates, with sample and hold times in the order of 5ms. With 1FF capacitors and good PCB layout, charge injection-error correction is normally not required. If higher/lower sampling speeds are required, the sampling capacitors and/or the series resistors at the cell connections can be reduced and/or increased. The cell sampling capacitors connected to the CT_ and CB_ terminals affect: • Speed of operation • Cell readout accuracy The smaller the sampling capacitor values, the lower their RC time constant and hence the faster their charging time. Therefore, for higher-speed operation, smaller capacitor values can be selected. One application case can be when the cell voltages are known to only vary by small amounts from one sample to the next. In this case, the sampling capacitors can be made smaller, as the sampling phases only need to charge the capacitors by the charge lost during the previous level shift and hold phase, including the small change in cell voltage. See the Measurement Accuracy section for details on how to calculate the voltage drop due to these two factors. For example, sampling capacitors of approximately 100nF can be adequate, thereby reducing the sampling phase by a factor of 10. If this technique is used, the initial sampling times, after initial power-up, either have to be made longer to allow the initially discharged sampling capacitors to charge up to the cell voltages, or the initial samples are disregarded until the monitored voltages stabilize to their final cell value. The accuracy dependence on the capacitor values is determined by the discharge during the hold phase and by the errors introduced during level shifting (both were previously described). By speeding up the readout of the cell voltages during the hold phase, discharging is reduced. Note that the last cell voltage being read out Maxim Integrated is most affected by discharging, due to its longer hold delay until being read out. Smaller capacitor values are prone to higher charge injection errors caused by level shifting. Both low-capacitance layout and level-shift compensation reduce these errors. Typical Application Circuit Figure 11 shows a high-accuracy measurement application based on an accurate 16-bit ADC, together with a high-quality voltage reference. The internal linear regulator is used for supplying VA (+5V), and uses the SAMPL input for controlling the cell voltage sample and hold times. Thermistors are connected to the T1, T2, and T3 inputs to monitor three temperatures. If less absolute measurement accuracy is acceptable, an ADC with internal reference, such as the MAX11163, can be used. In applications where accuracy is not a critical factor, a microcontroller’s internal ADC may be adequate. Multipack Applications In applications that require more than 12/16 cells to achieve higher voltages, multiple cell packs can be stacked. Each pack in the stack does not have to have the same number of cells. A minimum of +6V or 3 cells can be monitored by the devices. In stacked packs, the sample signal can either be centrally controlled by a common signal for simultaneous sampling, or the sample/hold can be initiated through SPI. Two cell packs stacked on one another can be interconnected through an SPI or other communication interface. The packs can either have internal controllers or multiple packs can be controlled by one common controller. Internal controllers perform autonomous calibration and measurements, and allow an external controller to collect the data on demand. This scheme is shown in Figure 12. To translate the interpack communication signals between the differing common-mode pack voltages, use opto-isolators, digital isolators, or digital ground level shifters (Figure 12). Layout Considerations Keep the PCB traces to the sampling capacitors as short as possible and minimize parasitic capacitance between the capacitor pins and the ground plane. 24 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs 1µF CT16 1µF CB16 CT15 1µF CB15 CT14 CB14 LDOIN T_ VP CV16 POWERSUPPLY UNIT VA BA16 1µF CV15 VA VL MAX14920 MAX14921 1µF BA15 AOUT CV14 MAX11163 16-BIT ADC MAX6126 EXTERNAL REFERENCE SAMPL CV1 SCLK SDO SDI BA1 CS CV0 DGND µC EN AGND CT1 CB2 1µF CT2 1µF CB3 CT3 1µF Figure 11. Typical Application Circuit Maxim Integrated 25 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs COMn SDO CS CLK SDI VCCn GND MAX17501 VP VA SPI2 MAX14920 MAX14921 ADC SDO SPI1 CONTROLLER GND SDI MAX14850 COMn-1 VCCn-1 VCC1 COM1 GND MAX17501 VP VA SPI2 MAX14920 MAX14921 ADC SDO SPI1 CONTROLLER GND SDI MAX14850 MOSI CS CLK MISO CONTROLLER GND VCC Figure 12. Stacked Battery Pack Application Diagram Based on Daisy-Chained SPI Maxim Integrated 26 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs CB16* CT16* CB15* CT15* CB14* CT14* CB13* CT13* CB12 CT12 CB11 CT11 CB10 CT10 CB9 CT9 VP Functional Diagram CV16* BA16* MAX14920 MAX14921 CV15* BA15* CV14* T1 BA14* CV13* T2 BA13* CV12 T3 BA12 CV11 +5V LDO BA11 LDOIN VA CV10 BA10 AOUT CV9 BA9 CV8 EN SOURCE SELECT/ CALIBRATION BA8 CV7 BA7 VL CV6 BA6 CV5 SAMPL BA5 CV4 CS BA4 CV3 SPI BA3 SCLK SDI CV2 BA2 SDO CV1 BA1 DGND CB8 CT8 CB7 CT7 CB6 CT6 CB5 CT5 CB4 CT4 CB3 CT3 CB2 CT2 CB1 CT1 AGND CV0 *MAX14921 ONLY. Maxim Integrated 27 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Package Information Ordering Information TEMP RANGE PINPACKAGE PART CELLS MAX14920ECB+ 12 -40NC to +85NC 64 TQFP-EP* MAX14921ECS+ 16 -40NC to +85NC 80 TQFP +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Chip Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 64 TQFP-EP C64E+10 21-0084 90-0329 80 TQFP C80+1 21-0072 — PROCESS: BiCMOS Maxim Integrated 28 MAX14920/MAX14921 High-Accuracy 12-/16-Cell Measurement AFEs Revision History REVISION NUMBER REVISION DATE 0 10/12 Initial release — 1 2/13 Removed future products asterisks from the MAX14920 28 DESCRIPTION PAGES CHANGED Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. 29 Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.