MAXIM MAX5825AAUP+

19-6185; Rev 0; 2/12
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
General Description
The MAX5823/MAX5824/MAX5825 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5823/MAX5824/MAX5825 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
The MAX5823/MAX5824/MAX5825 have an I2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low supply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5823/
MAX5824/MAX5825 reset the DAC outputs to zero or midscale based on the status of M/Z logic input, providing
flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5823/MAX5824/MAX5825
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
The MAX5823/MAX5824/MAX5825 feature a watchdog
function which can be enabled to monitor the I/O interface for activity and integrity.
Benefits and Features
SEight High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment

±1 LSB INL Buffered Voltage Output

Guaranteed Monotonic Over All Operating
Conditions

Independent Mode Settings for Each DAC
SThree Precision Selectable Internal References

2.048V, 2.500V, or 4.096V
SInternal Output Buffer

Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
SSmall 6.5mm x 4.4mm 20-Pin TSSOP or UltraSmall 2.5mm x 2.3mm 20-Bump WLP Package
SWide 2.7V to 5.5V Supply Range
SSeparate 1.8V to 5.5V VDDIO Power-Supply Input
SFast 400kHz I2C-Compatible, 2-Wire Serial
Interface
SPin-Selectable Power-On-Reset to Zero-Scale or
Midscale DAC Output
SLDAC and CLR For Asynchronous DAC Control
SThree Software-Selectable Power-Down Output
Impedances

1kI, 100kI, or High Impedance
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the programmable default value. The MAX5823/MAX5824/MAX5825
are available in a 20-pin TSSOP and an ultra-small,
20-bump WLP package and are specified over the -40NC
to +125NC temperature range.
Applications
Functional Diagram
VDDIO
Gain and Offset Adjustment
Automatic Tuning and Optical Control
Portable Instrumentation
MAX5823
MAX5824
MAX5825
SCL
SDA
ADDR1
1 OF 8 DAC CHANNELS
CODE
REGISTER
I2C SERIAL
INTERFACE
DAC
LATCH
8 -/10-/12-BIT
DAC
OUT0
BUFFER
OUT1
CLR
OUT2
LDAC
CODE
IRQ
Power Amplifier Control and Biasing
Process Control and Servo Loops
REF
INTERNAL REFERENCE/
EXTERNAL BUFFER
ADDR0
Programmable Voltage and Current Sources
VDD
CLEAR/
RESET
LOAD
(GATE/
CLEAR/
RESET)
OUT3
OUT4
100kI
WATCHDOG
TIMER
DAC CONTROL LOGIC
POWER-DOWN
1kI
OUT5
OUT6
OUT7
M/Z
POR
GND
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX5823.related
�� Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ABSOLUTE MAXIMUM RATINGS
VDD, VDDIO to GND.................................................-0.3V to +6V
OUT_, REF to GND.....0.3V to the lower of (VDD + 0.3V) and +6V
SCL, SDA, IRQ, M/Z, LDAC, CLR to GND..............-0.3V to +6V
ADDR_ to GND.............................................-0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TSSOP (derate at 13.6mW/NC above 70NC)...............1084mW
WLP (derate at 21.3mW/NC above 70NC)...................1700mW
Maximum Continuous Current into Any Pin..................... Q50mA
Operating Temperature..................................... -40NC to +125NC
Storage Temperature........................................ -65NC to +150NC
Lead Temperature (TSSOP only)(soldering, 10s)............+300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) .......73.8NC/W
Junction-to-Case Thermal Resistance (θJC) ...............20NC/W
WLP
Junction-to-Ambient Thermal Resistance (θJA)
(Note 2)....................................................................47NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 2:Visit www.maxim-ic.com/app-notes/index.mvp/id/1891 for information about the thermal performance of WLP packaging.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 4)
Resolution and Monotonicity
Integral Nonlinearity (Note 5)
Differential Nonlinearity (Note 5)
Offset Error (Note 6)
MAX5823
8
MAX5824
10
MAX5825
12
MAX5823
-0.25
Q0.05
+0.25
MAX5824
-0.5
Q0.2
+0.5
MAX5825
-1
Q0.5
+1
MAX5823
-0.25
Q0.05
+0.25
MAX5824
-0.5
Q0.1
+0.5
MAX5825
-1
Q0.2
+1
OE
-5
Q0.5
+5
GE
-1.0
Q0.1
N
INL
DNL
Offset Error Drift
Q10
Gain Error (Note 6)
Gain Temperature Coefficient
With respect to VREF
Zero-Scale Error
Full-Scale Error
Bits
With respect to VREF
LSB
LSB
mV
FV/NC
+1.0
%FS
ppm of
FS/NC
Q3.0
0
+10
mV
-0.5
+0.5
%FS
�� Maxim Integrated Products 2
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
Output Voltage Range (Note 7)
Load Regulation
No load
0
VDD
2kI load to GND
0
VDD 0.2
2kI load to VDD
0.2
VDD
VOUT = VFS/2
DC Output Impedance
VOUT = VFS/2
Maximum Capacitive Load
Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
FV/mA
I
500
2
VDD = 5.5V
DC Power-Supply Rejection
VDD = 3V Q10%,
|IOUT| P 5mA
V
pF
kI
Sourcing (output
shorted to GND)
30
Sinking (output shorted
to VDD)
50
mA
VDD = 3V Q10% or 5V Q10%
100
FV/V
Positive and negative
1.0
V/Fs
¼ scale to ¾ scale, to P 1 LSB, MAX5823
2.2
¼ scale to ¾ scale, to P 1 LSB, MAX5824
2.6
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
Fs
¼ scale to ¾ scale, to P 1 LSB, MAX5825
4.5
DAC Glitch Impulse
Major code transition (code x7FF to x800)
2
Channel-to-Channel Feedthrough
(Note 8)
Internal reference
3.3
External reference
4.07
Midscale code, all digital inputs from 0V to
VDDIO
0.2
nV*s
Startup calibration time (Note 9)
200
Fs
From power-down
50
Fs
Digital Feedthrough
Power-Up Time
nV*s
nV*s
�� Maxim Integrated Products 3
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
Output Voltage-Noise Density
(DAC Output at Midscale)
Integrated Output Noise
(DAC Output at Midscale)
Output Voltage-Noise Density
(DAC Output at Full Scale)
Integrated Output Noise
(DAC Output at Full Scale)
SYMBOL
CONDITIONS
f = 1kHz
External reference
f = 10kHz
f = 1kHz
2.048V internal
reference
f = 10kHz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to
External reference
f = 0.1Hz to
f = 0.1Hz to
f = 0.1Hz to
2.048V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
2.5V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
4.096V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 1kHz
External reference
f = 10kHz
f = 1kHz
2.048V internal
reference
f = 10kHz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to
External reference
f = 0.1Hz to
f = 0.1Hz to
f = 0.1Hz to
2.048V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
2.5V internal
f = 0.1Hz to
reference
f = 0.1Hz to
f = 0.1Hz to
4.096V internal
f = 0.1Hz to
reference
f = 0.1Hz to
MIN
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
TYP
90
82
112
102
125
110
160
145
12
76
385
14
91
450
15
99
470
16
124
490
114
99
175
153
200
174
295
255
13
94
540
19
143
685
21
159
705
26
10kHz
213
300kHz
750
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
10Hz
10kHz
300kHz
MAX
UNITS
nV/√Hz
FVP-P
nV/√Hz
FVP-P
�� Maxim Integrated Products 4
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
55
VDD
V
74
FA
75
100
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
2.494
2.5
2.506
VREF = 4.096V, TA = +25NC
MAX5825A
4.086
4.096
4.106
Q3
Q10
Q10
Q25
kI
REFERENCE OUTPUT
Reference Output Voltage
VREF
Reference Temperature
Coefficient (Note 10)
MAX5823/MAX5824/MAX5825B
Reference Drive Capacity
External load
Reference Capacitive Load
Handling
Reference Load Regulation
ISOURCE = 0 to 500FA
Reference Line Regulation
V
ppm/NC
25
kI
200
pF
2
mV/mA
0.05
mV/V
POWER REQUIREMENTS
Supply Voltage
VDD
I/O Supply Voltage
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
VDDIO
1.8
Internal reference
Supply Current (Note 11)
IDD
External reference
Power-Down Mode Supply
Current
Digital Supply Current
IPD
IDDIO
5.5
VREF = 2.048V
1.6
2
VREF = 2.5V
1.7
2.1
VREF = 4.096V
2.0
2.5
VREF = 3V
1.6
2.0
1.9
2.5
VREF = 5V
All DACs off, internal reference ON
140
All DACs off, internal reference OFF,
TA = -40NC to +85NC
0.7
2
All DACs off, internal reference OFF,
TA = +125NC
2
4
Static logic inputs, all outputs unloaded
1
V
V
mA
FA
FA
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR0, ADDR1, LDAC, CLR, M/Z)
Input High Voltage (Note 11)
VIH
(All inputs except
M/Z)
2.2V < VDDIO < 5.5V
0.7 x
VDDIO
1.8V < VDDIO < 2.2V
0.8 x
VDDIO
2.7V < VDD < 5.5V (for M/Z)
0.7 x
VDD
V
V
�� Maxim Integrated Products 5
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
Input Low Voltage (Note 11)
SYMBOL
VIL
CONDITIONS
(All inputs except
M/Z)
MIN
TYP
MAX
UNITS
2.2V < VDDIO < 5.5V
0.3 x
VDDIO
V
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
0.3 x
VDD
2.7V < VDD < 5.5V (for M/Z)
Input Leakage Current
IIN
VIN = 0V or VDDIO, all inputs except M/Z
(Note 11)
Q0.1
V
Q1
FA
10
pF
VIN = 0V or VDD, for M/Z (Note 11)
Input Capacitance (Note 10)
CIN
Hysteresis Voltage
VH
ADDR_ Pullup/Pulldown Strength
RPU, RPD
0.15
(Note 12)
30
50
V
90
kI
0.2
V
Q1
FA
10
pF
1.05
ms
DIGITAL OUTPUT (SDA, IRQ)
Output Low Voltage
VOL
ISINK = 3mA
Output Inactive Leakage
IOFF
IRQ only, see IIN for SDA
Output Inactive Capacitance
COFF
IRQ only, see CIN for SDA
Q0.1
WATCHDOG TIMER CHARACTERISTICS
Watchdog Timer Period
tWDOSC
VDD = 3V, TA = +25°C
Watchdog Timer Period Supply
Drift
VDD = 2.7V to 5.5V, TA = +25°C
Watchdog Timer Period
Temperature Drift
VDD = 3V
0.95
1
0.6
%/V
0.0375
%/°C
I2C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
Fs
Hold Time Repeated for a START
Condition
tHD;STA
0.6
Fs
SCL Pulse Width Low
tLOW
1.3
Fs
SCL Pulse Width High
tHIGH
0.6
Fs
Setup Time for Repeated START
Condition
tSU;STA
0.6
Fs
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
100
tR
20 +
CB/10
SDA and SCL Receiving
Rise Time
400
900
kHz
ns
ns
300
ns
�� Maxim Integrated Products 6
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA and SCL Receiving Fall
Time
tF
20 +
CB/10
300
ns
SDA Transmitting Fall Time
tF
20 +
CB/10
250
ns
tSU;STO
0.6
Setup Time for STOP Condition
Bus Capacitance Allowed
CB
Pulse Width of Suppressed Spike
tSP
CLR Removal Time Prior to a
Recognized START
VDD = 2.7V to 5.5V
Fs
10
400
50
pF
ns
tCLRSTA
100
ns
CLR Pulse Width Low
tCLPW
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
tLDH
400
ns
LDAC Fall to SCLK Rise Hold
Note 3: Limits are 100% production tested at TA = +25NC and/or TA = +125NC. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25NC and are
not guaranteed.
Note 4: DC performance is tested without load, VREF = VDD.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Gain and offset calculated from measurements made at code 30 and 4065 with VREF = VDD.
Note 7: Subject to zero- and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10:Guaranteed by design.
Note 11:All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO for all inputs .
Note 12:Unconnected conditions on the ADDR_ inputs are sensed through a resistive pullup and pulldown operation; for proper
operation, ADDR_ inputs must be connected to VDDIO, GND, or left unconnected with minimal capacitance.
SDA
tLOW
tF
tF
tSU;DAT
tHD;STA
tF
tSP
tBUF
tR
SCL
tHD;STA
tCLPW
S
tHIGH
tHD;DAT
CLR
tCLRSTA
tSU;STA
tSU;STO
Sr
P
tLDH
S
tLDPW
LDAC
Figure 1. I2C Serial Interface Timing Diagram
�� Maxim Integrated Products 7
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
INL vs. CODE
VDD = VREF = 5V
NO LOAD
0.8
0.6
0.2
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
512 1024 1536 2048 2560 3072 3584 4096
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DNL vs. CODE
VDD = VREF
0.8
0.6
0.4
MAX INL
0.2
0
-0.2
0
-0.4
-0.6
-0.8
-0.8
-1.0
-1.0
0
-0.2
-0.8
-1.0
3.1
3.5
3.9
4.3
4.7
5.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
ZERO-SCALE ERROR
0.8
0.6
0.4
VREF = 2.5V (EXTERNAL)
NO LOAD
ZERO-SCALE ERROR
0.020
0.016
0.012
0
-0.2
OFFSET ERROR
-0.4
0.2
OFFSET ERROR (VDD = 5V)
0
-0.2
-0.4
OFFSET ERROR (VDD = 3V)
0.004
0
-0.004
-0.6
-0.012
-0.8
-0.8
-0.016
-1.0
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
5.1
5.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FULL-SCALE ERROR
-0.008
-0.6
-1.0
GAIN ERROR
0.008
ERROR (%fs)
ERROR (mV)
0.4
0.2
MAX5823 toc09
1.0
MAX5823 toc08
0.6
2.7
MIN DNL
MIN INL
-0.6
CODE (LSB)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.8
MAX DNL
0.2
-0.4
MIN DNL
MIN INL
2.7
MAX5823 toc07
1.0
512 1024 1536 2048 2560 3072 3584 4096
MAX INL
0.4
-0.2
-0.6
0.6
MAX DNL
0.2
-0.4
VDD = VREF = 3V
0.8
ERROR (LSB)
ERROR (LSB)
0.4
0
INL AND DNL vs. TEMPERATURE
1.0
MAX5823 toc05
1.0
MAX5823 toc04
VDD = VREF = 5V
NO LOAD
0.6
CODE (LSB)
INL AND DNL vs. SUPPLY VOLTAGE
1.0
0.8
512 1024 1536 2048 2560 3072 3584 4096
0
CODE (LSB)
MAX5823 toc06
-0.2
DNL (LSB)
0.2
INL (LSB)
0.4
0.2
CODE (LSB)
DNL (LSB)
0.6
0.4
0
VDD = VREF = 3V
NO LOAD
0.8
0.4
0
ERROR (mV)
1.0
MAX5823 toc02
0.6
INL (LSB)
MAX5823 toc01
VDD = VREF = 3V
NO LOAD
0.8
DNL vs. CODE
1.0
MAX5823 toc03
INL vs. CODE
1.0
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.020
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
�� Maxim Integrated Products 8
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
GAIN ERROR (VDD = 3V)
-0.05
VREF (INTERNAL) =
2.5V, VDD = 5V
1.2
-0.10
0.8
TA = +85°C
TA = +25°C
TA = -40°C
0.4
3.1
3.5
3.9
4.3
0.6
0.2
0
2.7
3.1
3.5
VDD = VREF = 5V
VDD = 5V,
VREF = 2.5V
VDD = 5V,
VREF = 2.048V
0.8
4.7
5.1
5.5
3.9
4.3
4.7
5.1
5.5
IREF (EXTERNAL) vs. CODE
VDD = 5V, VREF = 4.096V
1.2
MAX5823 toc12
VDD = VDDIO
VDAC_ = FULL SCALE
ALL DACS ENABLED
NO LOAD
0.4
VDD = VREF = 3V
0.4
0
2.7
0.8
SUPPLY VOLTAGE (V)
1.6
SUPPLY CURRENT (mA)
TA = +125°C
VREF = 2.5V (EXTERNAL)
VREF (INTERNAL) =
2.048V
1.0
IVDD vs. CODE
2.0
MAX5823 toc13
POWER-DOWN SUPPLY CURRENT (µA)
VDD = VDDIO
VREF = 2.5V (EXTERNAL)
POWER-DOWN MODE WITH HI-Z
NO LOAD
1.2
1.2
TEMPERATURE (°C)
POWER-DOWN MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.6
1.4
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.0
VREF (INTERNAL) =
2.048V, VDD = 5V
VREF (EXTERNAL) = VDD = 3V
1.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX5823 toc11
1.4
VREF (INTERNAL) = 2.5V
1.6
60
VDD = VREF
NO LOAD
50
REFERENCE CURRENT (µA)
FULL-SCALE ERROR
VREF (EXTERNAL) = VDD = 5V
1.6
VREF (INTERNAL) = 4.096V
1.8
SUPPLY CURRENT (mA)
0
VREF (INTERNAL) =
4.096V, VDD = 5V
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.0
MAX5823 toc14
ERROR (%fsr)
GAIN ERROR (VDD = 5V)
VDD = VDDIO
VDAC_ = FULL SCALE
ALL DACS ENABLED
NO LOAD
1.8
SUPPLY CURRENT (mA)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.05
SUPPLY CURRENT vs. TEMPERATURE
2.0
MAX5823 toc10
0.10
MAX5823 toc15
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
40
VREF = 5V
30
VREF = 3V
20
10
NO LOAD
0
0
0
512 1024 1536 2048 2560 3072 3584 4096
SUPPLY VOLTAGE (V)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5823 toc16
MAX5823 toc17
VOUT
0.5V/div
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4 SCALE
4.3µs
ZOOMED VOUT
1 LSB/div
ZOOMED VOUT
1 LSB/div
3.75µs
VOUT
0.5V/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
4µs/div
�� Maxim Integrated Products 9
MAX5823/MAX5824/MAX5825
Ultra-Small, Quad Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAX5823 toc18
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GLITCH IMPULSE = 2nV*s
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GLITCH IMPULSE = 2nV*s
ZOOMED VOUT
1.25mV/div
ZOOMED VOUT
1.25mV/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
2µs/div
MAX5823 toc19
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
2µs/div
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5823 toc21
MAX5823 toc20
VSCL
5V/div
0V
VDD = VREF = 5V
10kI LOAD TO VDD
VDD
2V/div
0V
36TH EDGE
DAC OUTPUT
500mV/div
VOUT
2V/div
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
0V
10µs/div
20µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V, TA = +25NC, NO LOAD)
MAX5823 toc23
MAX5823 toc22
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 2.6nV*s
VDAC4
0.585 LSB/div
NO LOAD
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
4µs/div
VDAC0
5V/div
NO LOAD
VDAC4
0.585 LSB/div
NO LOAD
VDAC0
5V/div
NO LOAD
4µs/div
�� Maxim Integrated Products 10
MAX5823/MAX5824/MAX5825
Ultra-Small, Quad Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
MAX5823 toc24
MAX5813 toc25
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 4.07nV*s
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*S
VDAC4
0.585 LSB/div
NO LOAD
VDAC4
0.585 LSB/div
NO LOAD
VDAC0
5V/div
LOADED
VDAC0
5V/div
LOADED
4µs/div
4µs/div
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 10kI)
OUTPUT LOAD REGULATION
MAX5823 toc26
DIGITAL CROSSTALK = 0.2nV*s
STATIC DAC MIDSCALE
VDD = VREF
8
6
VDD = 5V
DVOUT (mV)
4
VDAC_
2mV/div
MAX5823 toc27
10
2
0
VDD = 3V
-2
-4
-6
-8
-10
-30 -20 -10
20ns/div
0
10
20
30
40
50
60
IOUT (mA)
300
4.50
3.50
VDD = 5V
100
VOUT (V)
DVOUT (mV)
VDD = 5V, SOURCING
4.00
200
0
-100
VDD = 3V
3.00
2.50
-200
1.50
-300
1.00
-400
0.50
-500
-30 -20 -10 0
10 20 30 40 50 60 70
IOUT (mA)
VDD = 3V, SOURCING
2.00
VDD = 3V AND 5V
SINKING
VDD = VREF
DAC = FULL SCALE
350
VDD = 5V, VREF = 4.096V
INTERNAL
300
VDD = 5V, VREF = 2.5V
INTERNAL
250
200
VDD = 5V, VREF = 2.048V
INTERNAL
150
100
50
VDD = 5V, VREF = 3.5V
(EXTERNAL)
0
0
0
1
2
3
4
5
6
IOUT (mA)
7
8
9
10
MAX5823 toc30
5.00
NOISE-VOLTAGE DENSITY (nV/√Hz)
VDD = VREF
MAX5823 toc29
400
MAX5823 toc28
500
NOISE-VOLTAGE DENSITY vs. FREQUENCY
(DAC AT MIDSCALE)
HEADROOM AT RAILS
vs. OUTPUT CURRENT
OUTPUT CURRENT LIMITING
100
1k
10k
100k
FREQUENCY (Hz)
�� Maxim Integrated Products 11
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5823 toc31
MAX5823 toc32
MIDSCALE UNLOADED
VP-P = 12µV
MIDSCALE UNLOADED
VP-P = 13µV
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5823 toc33
MAX5823 toc34
MIDSCALE UNLOADED
VP-P = 16µV
MIDSCALE UNLOADED
VP-P = 15µV
2µV/div
2µV/div
4s/div
4s/div
VDD = 5V
INTERNAL REFERENCE
-0.2
DVREF (mV)
20
15
-0.4
-0.6
10
VREF = 2.048V, 2.5V, AND 4.096V
-0.8
5
2000
SDA , SCL, CLR, AND LDAC SWEPT FROM
0V TO VDDIO AND
VDDIO TO 0V
1800
1600
SUPPLY CURRENT (µA)
25
0
MAX5823 toc36
VDD = 2.7V
VREF = 2.5V (INTERNAL)
BOX METHOD
MAX5823 toc35
PERCENT OF POPULATION (%)
30
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
(VDD = 3V)
REFERENCE LOAD REGULATION
1400
1200
VDDIO = 5V
1000
800
600
VDDIO = 3V
400
200
-1.0
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE DRIFT (ppm /°C)
MAX5823 toc37
VREF DRIFT vs. TEMPERATURE
0
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
VDDIO = 1.8V
0
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
�� Maxim Integrated Products 12
MAX5823/MAX5824/MAX5825
Ultra-Small, Quad Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5825, 12-bit performance, TA = +25°C, unless otherwise noted.)
WATCHDOG TIMER FREQUENCY
vs. SUPPLY VOLTAGE
10
8
6
4
1000
995
990
985
980
975
1012
1010
1008
1006
1004
1002
998
1000
996
994
0
992
2
MAX5823 toc39
12
1005
WATCHDOG TIMER FREQUENCY (Hz)
VDD = 3V
990
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
1010
VDD = 3V
1000
990
MAX5823 toc40
WATCHDOG TIMER FREQUENCY
vs. TEMPERATURE
WATCHDOG TIMER FREQUENCY (Hz)
PERCENT OF POPULATION (%)
14
MAX5823 toc38
WATCHDOG TIMER PERIOD HISTOGRAM
980
970
960
950
940
930
920
910
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
�� Maxim Integrated Products 13
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Pin Configurations
TOP VIEW
TOP VIEW
REF
1
+
20
M/Z
DAC0
2
19
GND
DAC1
3
18
LDAC
DAC2
4
17
CLR
DAC3
5
DAC4
6
MAX5823
MAX5824
MAX5825
16
IRQ
15
SDA
DAC5
7
14
SCL
DAC6
8
13
ADDR0
DAC7
9
12
ADDR1
VDD
10
11
VDDIO
MAX5823/MAX5824/MAX5825
1
2
3
4
5
+ DAC6
DAC7
VDDIO
ADDR1
ADDR0
DAC5
DAC4
VDD
SDA
SCL
DAC2
DAC3
M/Z
CLR
IRQ
DAC1
DAC0
REF
GND
LDAC
A
B
C
D
WLP
TSSOP
Pin Description
PIN
NAME
FUNCTION
TSSOP
WLP
1
D3
REF
Reference Voltage Input/Output
2
D2
DAC0
DAC Channel 0 Voltage Output
3
D1
DAC1
DAC Channel 1 Voltage Output
4
C1
DAC2
DAC Channel 2 Voltage Output
5
C2
DAC3
DAC Channel 3 Voltage Output
6
B2
DAC4
DAC Channel 4 Voltage Output
7
B1
DAC5
DAC Channel 5 Voltage Output
8
A1
DAC6
DAC Channel 6 Voltage Output
9
A2
DAC7
DAC Channel 7 Voltage Output
10
B3
VDD
Analog Supply Voltage
11
A3
VDDIO
Digital Supply Voltage
12
A4
ADDR1
I2C Address Selection Input Bit 1
13
A5
ADDR0
I2C Address Selection Input Bit 0
14
B5
SCL
I2C Serial Data Clock Input
15
B4
SDA
I2C Serial Data Bus Input/Output
16
C5
IRQ
17
C4
CLR
Active-Low Open Drain Interrupt Output. IRQ low indicates watchdog timeout.
Active-Low Asynchronous DAC Clear Input
18
D5
19
D4
LDAC
GND
20
C3
M/Z
Active-Low Asynchronous DAC Load Input
Ground
DAC Output Reset Selection. Connect M/Z to GND for zero-scale and connect M/Z to
VDD for midscale.
�� Maxim Integrated Products 14
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Description
The MAX5823/MAX5824/MAX5825 are 8-channel, lowpower, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and lowvoltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a fast 400kHz I2Ccompatible interface. The MAX5823/MAX5824/MAX5825
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) circuit
to initialize the DAC outputs to zero scale (M/Z = 0) or
midscale (M/Z = 1), and control logic.
CLR is available to asynchronously clear the DAC outputs to a user-programmable default value, independent
of the serial interface. LDAC is available to simultaneously update selected DACs on one or more devices.
The MAX5823/MAX5824/MAX5825 also feature userconfigurable interface watchdog, with status indicated
by the IRQ output.
DAC Outputs (OUT_)
The MAX5823/MAX5824/MAX5825 include internal buffers on all DAC outputs, which provide improved load
regulation for the DAC outputs. The output buffers slew
at 1V/Fs (typ) and drive as low as 2kI in parallel with
500pF. The analog supply voltage (VDD) determines the
maximum output voltage range of the devices since it
powers the output buffers. Under no-load conditions, the
output buffers drive from GND to VDD, subject to offset
and gain errors. With a 2kω load to GND, the output buffers drive from GND to within 200mV of VDD. With a 2kω
load to VDD, the output buffers drive to within 200mV of
GND and VDD.
The DAC ideal output voltage is defined by:
VOUT
= VREF ×
D
2N
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user commands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
logic input.
The contents of both CODE and DAC registers are maintained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents.
Once the device is powered up, each DAC channel can
be independently programmed with a desired RETURN
value using the RETURN command. This becomes the
value the CODE and DAC registers will use in the event
of any watchdog, clear or gate activity, as selected by
the DEFAULT command.
Hardware CLR operations and SW_CLEAR commands
return the contents of all CODE and DAC registers to their
user-selected defaults. SW_RESET commands will reset
CODE and DAC register contents to their M/Z selected
initial codes. A SW_GATE state can be used to momentarily hold selected DAC outputs in their DEFAULT positions. The contents of CODE and DAC registers can
be manipulated by watchdog timer activity, enabling a
variety of safety features.
Internal Reference
The MAX5823/MAX5824/MAX5825 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF output
for other external circuitry (see the Typical Operating
Circuits) and can drive loads down to 25kI.
�� Maxim Integrated Products 15
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
External Reference
The external reference input has a typical input impedance
of 100kI and accepts an input voltage from +1.24V to VDD.
Apply an external voltage between REF and GND to use
an external reference. The MAX5823/MAX5824/MAX5825
power up and reset to external reference mode. Visit
www.maxim-ic.com/products/references for a list of
available external voltage-reference devices.
S
Sr
P
SCL
SDA
M/Z Input
The MAX5823/MAX5824/MAX5825 feature a pin selectable DAC reset state using the M/Z input. Upon a poweron reset, all CODE and DAC data registers are reset to
zero scale (M/Z = GND) or midscale (M/Z = VDD). M/Z is
referenced to VDD (not VDDIO). In addition, M/Z must be
valid at the time the device is powered up—connect M/Z
directly to VDD or GND.
VALID START, REPEATED START, AND STOP PULSES
P
S
S
P
P
S
P
Load DAC (LDAC) Input
The MAX5823/MAX5824/MAX5825 feature an active-low
asynchronous LDAC logic input that allows DAC outputs
to update simultaneously. Connect LDAC to VDDIO or
keep LDAC high during normal operation when the
device is controlled only through the serial interface.
Drive LDAC low to update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updating the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
Clear (CLR) Input
The MAX5823/MAX5824/MAX5825 feature an asynchronous active-low CLR logic input that simultaneously
sets all selected DAC outputs to their programmable
DEFAULT states. Driving CLR low clears the contents of
both the CODE and DAC registers and also ignores any
on-going I2C command which modifies registers associated with a DAC configured to accept clear operations.
To allow a new I2C command, drive CLR high, satisfying the tCLRSTA timing requirement. A software CONFIG
command can be used to configure the clear operation of
each DAC independently.
Watchdog Feature
The MAX5823/MAX5824/MAX5825 feature an interface
watchdog timer with programmable timeout duration. This
monitors the I/O interface for activity and integrity. If the
INVALID START/STOP PULSE PAIRINGS-ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
watchdog is enabled, the host processor must write a valid
command to the device within the timeout period to prevent
a timeout. If the watchdog is allowed to timeout, selected
DAC outputs are returned to the programmable DEFAULT
state, protecting the system against control faults.
By default, all watchdog features are disabled; users
wishing to activate any watchdog feature must configure
the device accordingly. Individual DAC channels can
be configured using the CONFIG command to accept
the watchdog alarm and to gate, clear, or hold their outputs in response to an alarm. A watchdog refresh event
and watchdog behavior upon timeout is defined by a
programmable safety level using the WDOG_CONFIG
command.
IRQ Output
The MAX5823/MAX5824/MAX5825 feature an active-low
open-drain interrupt output indicating to the host when a
watchdog timeout has occurred.
�� Maxim Integrated Products 16
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Interface Power Supply (VDDIO)
The MAX5823/MAX5824/MAX5825 feature a separate
supply input (VDDIO) for the digital interface (1.8V to
5.5V). Connect VDDIO to the I/O supply of the host processor.
I2C
Serial Interface
I2C-/
The MAX5823/MAX5824/MAX5825 feature an
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5823/
MAX5824/MAX5825 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5823/MAX5824/MAX5825 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5823/
MAX5824/MAX5825 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5823/MAX5824/MAX5825 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5823/
MAX5824/MAX5825 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5823/
MAX5824/MAX5825 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
signals. The MAX5823/MAX5824/MAX5825 can accommodate bus voltages higher than VDDIO up to a limit
of 5.5V; bus voltages lower than VDDIO are not recommended and may result in significantly increased interface currents. The MAX5823/MAX5824/MAX5825 digital
inputs are double buffered. Depending on the command
Table 1. I2C Slave Address LSBs
ADDR1
ADDR0
A3
A2
A1
A0
VDDIO
VDDIO
1
1
1
1
VDDIO
N.C.
1
1
1
0
VDDIO
GND
1
1
0
0
N.C.
VDD
1
0
1
1
N.C.
N.C.
1
0
1
0
N.C.
GND
1
0
0
0
GND
VDDIO
0
0
1
1
GND
N.C.
0
0
1
0
GND
GND
0
0
0
0
issued through the serial interface, the CODE register(s)
can be loaded without affecting the DAC register(s)
using the write command. To update the DAC registers,
either drive the LDAC input low to simultaneously update
all DAC outputs, or use the software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5823/MAX5824/MAX5825. The master terminates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
The MAX5823/MAX5824/MAX5825 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse
as a START condition. Transmissions ending in an
early STOP condition will not impact the internal device
settings. If the STOP occurs during a readback byte,
the transmission is terminated and a later read mode
request will begin transfer of the requested register data
from the beginning (this applies to combined format I2C
read mode transfers only), interface verification mode
transfers will be corrupted. See Figure 2.
SMBus is a trademark of Intel Corp.
�� Maxim Integrated Products 17
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
I2C Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit. See
Figure 4. The three most significant bits are 001 with the
4 LSBs determined by ADDR1 and ADDR0 as shown in
Table 1. Setting the R/W bit to 1 configures the MAX5823/
MAX5824/MAX5825 for read mode. Setting the R/W bit to
0 configures the MAX5823/MAX5824/MAX5825 for write
mode. The slave address is the first byte of information sent to the MAX5823/MAX5824/MAX5825 after the
START condition.
The MAX5823/MAX5824/MAX5825 has the ability to
detect an unconnected (N.C.) state on the ADDR_ inputs
for additional address flexibility; if disconnecting the
ADDR_ inputs, be certain to minimize all loading on the
ADDR_ inputs (i.e. provide a landing for ADDR_, but do
not allow any board traces).
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5823/MAX5824/MAX5825
devices on a given I2C bus. All MAX5823/MAX5824/
CLOCK PULSE
FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 3. I2C Acknowledge
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
MAX5825 devices acknowledge and respond to the
broadcast device address 00101000, regardless of the
state of the address pins. The broadcast mode is intended for use in write mode only (as indicated by R/W = 0 in
the address given).
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5823/MAX5824/MAX5825 use to handshake receipt of each byte of data as shown in Figure 3.
The MAX5823/MAX5824/MAX5825 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5823/MAX5824/MAX5825. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5823/MAX5824/
MAX5825, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitching or digital feedthrough to the DACs while the interface
is active.
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
SDA
SCL
STOP
0
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
COMMAND EXECUTED
A ACK. GENERATED BY MAX5823/MAX5824/MAX5825
Figure 4. I2C Single Register Write Sequence
�� Maxim Integrated Products 18
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
I2C Write Operations
Combined Format I2C Readback Operations
A master device communicates with the MAX5823/
MAX5824/MAX5825 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the address
of the MAX5823/MAX5824/MAX5825 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I2C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5823/MAX5824/
MAX5825 support this capability for all user-accessible
write mode commands.
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5823/MAX5824/MAX5825 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5823/
MAX5824/MAX5825 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are provided, the MAX5823/MAX5824/MAX5825 will continue to
readback ones.
Readback of the WDOG command (B[23:20] = 0001)
is directly supported, confirming the current watchdog
timeout selection, mask status, and safety level.
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SDA
SCL
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4
STOP
3 2 1 0 A
COMMANDn
EXECUTED
A ACK. GENERATED BY MAX5823/MAX5824/MAX5825
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
START
SDA
SCL
0
0
WRITE COMMAND1
BYTE #2: COMMAND1
BYTE
1 A3 A2 A1 A0 W A 0 0 N N N N N N A
READ ADDRESS
BYTE #3: I2C SLAVE
ADDRESS
REPEATED
START
0
0
READ DATA
BYTE #4: DATA1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA1 LOW
BYTE (B[15:8])
STOP
1 A3 A2 A1 A0 R A D D D D D D D D A D D D D D D D D ~A
A ACK. GENERATED BY MAX5823/MAX5824/ MAX5825
A ACK. GENERATED BY I2C MASTER
Figure 6. Standard I2C Register Read Sequence
�� Maxim Integrated Products 19
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Readback of individual RETURN registers is supported
for RETURN commands (B[23:20] = 0111). For this command, which supports a DAC address, the requested
channel RETURN register content will be returned,
along with the selected DAC address. If all DACs are
selected, readback will begin with RETURN0 content
and will progress through the remaining DAC channels.
The RETURN_ALL (B[23:16] = 11000011) command
behaves identically to the RETURN command with all
DACs selected.
11000001 and 11000010, respectively) behave identically to the LOAD command with all DACs selected.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[7:0], with a
1 indicating the DAC is powered down and a zero indicating the DAC is operational (see Table 2).
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s current watchdog timer status (WD:0 = normal, 1 = timed out), reference setting (REF[2:0]), and CLR
condition, along with the device revision (B[10:8] = 001)
and part ID (B[7:0]) in the format as shown in Table 2.
Readback of individual CODE registers is supported for
the CODE commands (B[23:20] = 1000). For this command, which supports a DAC address, the requested
channel CODE register content will be returned, along
with the selected DAC address. If all DACs are selected, readback will begin with CODE0 content and will
progress through the remaining DAC channels. The
CODE_ALL (B[23:16] = 11000000) command behaves
identically to the CODE command with all DACs selected.
Interface Verification I2C
Readback Operations
While the MAX5823/MAX5824/MAX5825 support standard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 1001, 1010, 1011). For
these commands, which support a DAC address, the
requested DAC register content will be returned, along
with the selected DAC address. If all DACs are selected,
readback will begin with DAC0 content and will progress
through the remaining DAC channels. The LOAD_ALL
and CODE_ALL_LOAD_ALL commands (B[23:16] =
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
Table 2. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
0
1
X
X
X
X
X
X
X
X
READBACK DATA LOW BYTE
B8
WDOG Timeout Selection[11:4]
0
0
0
0
0
B5
B4
B3
B2
Timeout Selection[3:0] WDM
1
0
0
1
1
1
DAC SELECTION
RETURNn[11:4]
RETURNn[3:0]
ADDRESSn[3:0]
1
0
0
0
DAC SELECTION
CODEn[11:4]
CODEn[3:0]
ADDRESSn[3:0]
1
0
0
1
DAC SELECTION
DACn[11:4]
DACn[3:0]
ADDRESSn[3:0]
1
0
1
0
DAC SELECTION
DACn[11:4]
DACn[3:0]
ADDRESSn[3:0]
1
0
1
1
DAC SELECTION
DACn[11:4]
DACn[3:0]
ADDRESSn[3:0]
1
1
0
0
0
0
0
0
CODE0[11:4]
CODE0[3:0]
ADDRESS0[3:0]
1
1
0
0
0
0
0
1
DAC0[11:4]
DAC0[3:0]
ADDRESS0[3:0]
1
1
0
0
0
0
1
0
DAC0[11:4]
DAC0[3:0]
ADDRESS0[3:0]
1
1
0
0
0
0
1
1
RETURN0[11:4]
RETURN0[03:0]
All Other Commands (MAX5823)
WD
REF[2:0]
CLR
REV_ID
[2:0]
(001)
0
B1
WL[1:0]
0
All Other Commands (MAX5824)
0
B6
0
All Other Commands (MAX5825)
0
B7
B0
0
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
ADDRESS0[3:0]
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
�� Maxim Integrated Products 20
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Table 3. Format DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
MAX5823
D7
D6
D5
D4
D3
D2
D1
D0
MAX5824
D9
D8
D7
D6
D5
D4
D3
D2
MAX5825
D11
D10
D9
D8
D7
D6
D5
D4
D3
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
SDA
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
D1
D0
X
X
X
X
X
X
D2
D1
D0
X
X
X
X
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
START
SDA
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
6
5
4
3
2 1
STOP
0 ~A
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
REPEATED
START
0
A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
A ACK. GENERATED BY MAX5823/MAX5824/MAX5825
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 ~A
A ACK. GENERATED BY I2C MASTER
Figure 7. Interface Verification I2C Register Read Sequences
�� Maxim Integrated Products 21
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to readback the
requested data are provided, the MAX5823/MAX5824/
MAX5825 will continue to readback ones.
µC
SDA
SCL
MAX5823
MAX5824
MAX5825
SCL
SDA
ADDR0
ADDR1
MAX5823
MAX5824
MAX5825
+5V
SCL
SDA
ADDR0
ADDR1
Figure 8. Typical I2C Application Circuit
START pair or Repeated START condition required, followed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5823/
MAX5824/MAX5825. The master still has control of the
SCL line but the MAX5823/MAX5824/MAX5825 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involving other devices do not impact the MAX5823/MAX5824/
MAX5825 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands written using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
I2C Compatibility
The MAX5823/MAX5824/MAX5825 are fully compatible
with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses. Figure 8 shows a
typical I2C application.
I2C User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5823/MAX5824/MAX5825.
Table 4 provides detailed information about the Command
Registers.
�� Maxim Integrated Products 22
0
0
0
0
0
0
0
0
0
REF
SW_GATE_CLR
SW_GATE_SET
WD_REFRESH
WD_RESET
SW_CLEAR
SW_RESET
POWER
CONFIG
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
X
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
REF
Pow- REF Mode
00 = EXT
er
0 = 01 = 2.5V
DAC 10 = 2.0V
1=
11 = 4.1V
ON
X
1
1
1
1
1
1
X
0
0
0
0
0
0
X
0
0
0
0
0
0
X
1
1
1
1
1
1
0
0
0
0
0
0
X
1
1
1
1
1
1
X
TIMEOUT SELECTION[11:4]
1
1
1
1
1
1
X
DAC 7
DAC 7
X
DAC 6
DAC 6
1
DAC 5
DAC 5
0
DAC 4
DAC 4
0
DAC 3
DAC 3
0
DAC 2
DAC 2
WDOG
B9
DAC 1
DAC 1
X`
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
B6
B5
X
1
X
0
0
0
0
0
0
0
0
0
Power
Mode
00 =
Normal
01 = PD
1kW
10 = PD
100kW
11 = PD
Hi-Z
WDOG
Configuration
00: DIS
01: GATE
10: CLR
11: HOLD
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
X
X
X
B4
TIMEOUT
SELECTION[3:0]
B7
X
X
B8
DAC 0
DAC 0
COMMAND
GATE_ENB
CONFIGURATION AND SOFTWARE COMMANDS
LDAC_ENB
0
0
0
0
0
X
0
0
0
0
0
X
X
X
0
0
0
0
0
X
0
0
0
X
X
X
X
0
0
0
0
0
0
X
X
Safety
Level
00: Low
01: Med
10: High
11: Max
X
B0
B1
B2
B3
WD_MASK
CLEAR_ENB
Table 4. I2C Commands Summary
Configures selected DAC
watchdog, GATE, LOAD, and
CLEAR operations.
DACs selected with a 1 in the
corresponding DACn bit are
updated, DACs with a 0 in
the corresponding DACn bit
are not impacted)
Sets the Power mode of
the selected DACs (DACs
selected with a 1 in the
corresponding DACn bit are
updated, DACs with a 0 in the
corresponding DACn bit are
not impacted)
Executes a software reset
(all CODE, DAC, and Control
registers returned to their
power-on reset values)
Executes a software clear
(all CODE and DAC registers
cleared to their default
values)
Resets the watchdog timeout
alarm status and refreshes
the watchdog timer
Refreshes the watchdog timer
Initiates a GATE condition
Removes any existing GATE
condition
Sets the reference operating
mode. REF Power (B18):
0 = Internal reference is only
powered if at least one DAC
is powered.
1 = Internal reference is
always powered.
Updates watchdog settings
and safety levels
DESCRIPTION
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
�� Maxim Integrated Products 23
1
1
1
1
1
1
1
1
CODEn
LOADn
CODEn_
LOAD_ALL
CODEn_LOADn
CODE_ALL
LOAD_ALL
CODE_ALL
LOAD_ALL
RETURN_ALL
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
X
X
X
1
1
0
0
X
X
X
1
0
1
0
DAC SELECTION
DAC SELECTION
DAC SELECTION
DAC SELECTION
DAC SELECTION
0
DAC 7
X
X
X
X
X
DAC 6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RETURNREGISTER
DATA[3:0]
X
RETURN REGISTER
DATA[11:4]
X
CODE REGISTER
DATA[3:0]
X
X
X
CODE REGISTER
DATA[11:4]
X
X
X
CODE REGISTER
DATA[3:0]
X
CODE REGISTER
DATA[11:4]
X
CODE REGISTER
DATA[3:0]
X
CODE REGISTER
DATA[11:4]
X
CODE REGISTER
DATA[3:0]
X
CODE REGISTER
DATA[11:4]
X
CODE REGISTER
DATA[3:0]
CODE REGISTER
DATA[11:4]
B4
RETURN REGISTER
DATA[3:0]
DAC 5
RETURN REGISTER
DATA[11:4]
DAC 4
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
No Operation
1
NO OPERATION COMMANDS
0
RETURNn
0
DAC 2
DAC COMMANDS
DEFAULT
Default
Values:
000: M/Z
001: ZERO
010: MID
011: FULL
100: RETURN
101+: No Effect
B5
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
B6
B7
B8
B9
DAC 1
DAC 3
COMMAND
DAC 0
Table 4. I2C Commands Summary (continued)
X
X
X
X
X
X
X
X
X
X
X
X
B3
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
X
X
X
X
X
B0
These commands will have no
effect on the device, but will
refresh the watchdog timer if
safety level is set to Low
Writes data to all RETURN
registers
Simultaneously writes data to
the all CODE registers while
updating all DAC registers
Updates all DAC latches with
current CODE register data
Writes data to all CODE
registers
Simultaneously writes data to
the selected CODE register(s)
while updating selected DAC
register(s)
Simultaneously writes data to
the selected CODE register(s)
while updating all DAC
registers
Transfers data from the
selected CODE registers to
the selected DAC register(s)
Writes data to the selected
CODE register(s)
Writes data to the selected
RETURN register(s)
Sets the default code settings
for selected DACs. Note:
DACs in RETURN mode
programmable RETURN
codes.
(DACs selected with a 1 in the
corresponding DACn bit are
updated, DACs with a 0 in the
corresponding DACn bit are
not impacted)
DESCRIPTION
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
�� Maxim Integrated Products 24
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
RETURNn Command
The RETURN command (B[23:20] = 0111) sets the programmable default RETURN value. This value is used
for all future watchdog, clear, and gate operations when
RET is selected for the DAC using the DEFAULT command. Issuing this command with DAC_ADDRESS set to
all DACs will program the value for all RETURN registers
and is equivalent to RETURN_ALL. Note: This command is
inaccessible when a watchdog timeout has occurred if the
watchdog timer is configured for safety level = high or max.
CODEn Command
The CODEn command (B[23:20] = 1000) updates
the CODE register contents for the selected DAC(s).
Changes to the CODE register content based on this
command will not affect DAC outputs directly unless the
LDAC input is in a low state or the DAC latch has been
configured as transparent using the CONFIG command.
Issuing this command with DAC_ADDRESS set to all
DACs will program the value for all CODE registers and
is equivalent to CODE_ALL.
LOADn Command
The LOADn command (B[23:20] = 1001) updates the
DAC register content for the selected DAC(s) by uploading the current contents of the selected CODE register(s)
into the selected DAC register(s). Channels for which
CODE content has not been modified since the last LOAD
or LDAC operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC_ADDRESS set
to all DACs will update the contents of all DAC registers
and is equivalent to LOAD_ALL.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 1011)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of the selected DAC(s). Channels for which CODE content has not
been modified since the last LOAD or LDAC operation
will not be updated to reduce digital crosstalk. Issuing
this command with DAC_ADDRESS set to all DACs is
equivalent to the CODE_ALL_LOAD_ALL command.
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 1010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which CODE content has not been modified
since the last LOAD or LDAC operation will not be updated to reduce digital crosstalk. Issuing this command with
DAC_ADDRESS set to all DACs will update the CODE
Table 5. DAC Selection
B19
B18
B17
B16
DAC SELECTED
0
0
0
0
DAC0
0
0
0
1
DAC1
0
0
1
0
DAC2
0
0
1
1
DAC3
0
1
0
0
DAC4
0
1
0
1
DAC5
0
1
1
0
DAC6
0
1
1
1
DAC7
1
X
X
X
ALL DACs
and DAC register contents of all DACs and is equivalent
to CODE_ALL_LOAD_ALL. Note this command by definition will modify at least one CODE register; to avoid this
use the LOAD command with DAC_ADDRESS set to all
DACs or the LOAD_ALL command.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 1100_0000)
updates the CODE register contents for all DACs.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 1100_0001)
updates the DAC register content for all DACs by uploading the current contents of the CODE registers to the
DAC registers.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1100_0010) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
RETURN_ALL Command
The RETURN_ALL command (B[23:16] = 1100_0011)
updates the RETURN register contents for all DACs.
NO_OP Commands Command
All unused commands in the space (B[23:16] = 1100_
X1XX or 1100_1XXX) have no effect on the device, but
will refresh the watchdog timer (if active) with the safety
level set to low.
�� Maxim Integrated Products 25
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
any register. LDAC and CLR inputs still function after a
watchdog timeout event.
WDOG Command
The WDOG command (B[23:20] = 0001) updates the
watchdog timeout settings and safety levels for the
device. Timeout thresholds are selected in 1ms increments (1ms to 4095ms are available). The WD_MASK bit
can be used to mask the IRQ operation in response to the
watchdog status, if WD_MASK = 1, watchdog alarms will
not assert IRQ. The watchdog alarm status (WD bit) can
be polled using the available I2C status readback commands regardless of WD_MASK settings. A write to this
register will not reset a previously triggered watchdog
alarm (use the WD_RESET command for this purpose).
The watchdog timer refresh and timeout behavior is
defined by the programmable safety level below.
Medium (01): A WD_REFRESH command must be executed in order to refresh the watchdog timer. Other commands
as well as LDAC or CLR activity do not refresh the watchdog timer. A triggered watchdog alarm does not prevent
writes to any register. LDAC and CLR inputs still function
after a watchdog timeout event.
Available safety levels (WL[1:0]):
High (10): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands as well
as LDAC or CLR activity do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution
of all POWER, REF, CONFIG, DEFAULT, and RETURN
commands. LDAC and CLR inputs still function after a
watchdog timeout event.
Low (00): Watchdog timer will refresh with the execution
of any valid user mode command or no-op. Any successful slave address acknowledge qualifies to restart the
watchdog timer (run to the ninth SCL edge), regardless
of the command which follows. Issuing hardware CLR or
LDAC falling edge will also refresh the watchdog timer.
A triggered watchdog alarm does not prevent writes to
Max (11): A WD_REFRESH command must be executed
to refresh the watchdog timer. Other commands, as well
as LDAC or CLR activity, do not refresh the watchdog
timer. A triggered watchdog alarm prevents execution of
all POWER, REF, CONFIG, DEFAULT, and RETURN commands. LDAC and CLR are gated and do not function
after a watchdog timeout event.
Table 6. WDOG Command Format
0
0
1
X
WDOG Command
X
X
X
C11 C10 C9
Don’t Care
C8
C7
C6
C5
B8
B7
B6
B5
B4
C4
C3
C2
C1
C0 WDM WL1 WL0
TIMEOUT
SELECTION[3:0]
TIMEOUT SELECTION[11:4]
Default Value →
0
0
Command Byte
0
0
0
0
0
0
0
0
0
Data High Byte
0
B3
B2
B1
WDOG
Safety
Level:
00: Low
01:
Med
10:
High
11: Max
0
0
0
B0
X
Don’t Care
0
WD_MASK
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
X
Data Low Byte
Table 7. Watchdog Safety Level Protection
WATCHDOG ANY COMMAND
SAFETY
REFRESHES
LEVEL
WDT
CLR/LDAC
REFRESHES
WDT
SW_RESET
PLUS WD_RFRS
REFRESHES WDT
ALL REGISTERS
ACCESSIBLE AFTER
WDT TIMEOUT*
CLR/LDAC AFFECT
DAC REGISTERS
AFTER WDT TIMEOUT*
00 (Low)
X
X
X
X
X
01 (Med)
—
—
X
X
X
10 (High)
—
—
X
—
X
11 (Max)
—
—
X
—
—
*Unless otherwise affected by Watchdog HOLD or CLR configurations as set by the CONFIG command. See the CONFIG register
definition for details.
�� Maxim Integrated Products 26
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
REF Command
The REF command (B[23:20] = 0010) updates the global
reference setting used for all DAC channels. If an internal
reference mode is selected, bit RF2 (B18) defines the
reference power mode. If RF2 is set to zero (default), the
reference will be powered down any time all DAC channels are powered down (i.e. the device is in STANDBY
mode). If RF2 is set to one, the reference will remain powered even if all DAC channels are powered down, allowing continued operation of external circuitry (note in this
mode the low current shutdown state is not available).
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
SW_GATE_CLR Command
The SW_GATE_CLR command (B[23:0] = 0011_0000_
1001_0110_0011_0000) will remove any existing GATE
condition initiated by a previous SW_GATE_SET comand.
SW_GATE_SET Command
The SW_GATE_SET command (B[23:0] = 0011_0001_
1001_0110_0011_0000) will initiate a GATE condition.
Any DACs configured with GTB = 0 (see the CONFIG
Command section) will have their outputs held at the
selected DEFAULT value until the GATE condition is later
removed by a subsequent SW_GATE_CLR command.
While in gate mode, the CODE and DAC registers con-
tinue to function normally and are not reset (unless reset
by a watchdog timeout).
WD_REFRESH Command
The WD_REFRESH command (B[23:0] = 0011_0010_
1001_0110_0011_0000) will refresh the watchdog timer.
This is the only command which will refresh the watchdog timer if the device is configured with a safety level of
medium, high, or max. Use this command to prevent the
watchdog timer from timing out.
WD_RESET Command
A WD_RESET command (B[23:0] = 0011_0011_
1001_0110_0011_0000) will reset the watchdog interrupt
(timeout) status and refresh the watchdog timer. Use this
command to reset the IRQ timeout condition after the
watchdog timer has timed out. Any DACs impacted by an
existing timeout condition will return to normal operation.
SW_CLEAR Command
A software clear command (B[23:0] = 0011_0100_
001_0110_0011_0000) will clear the contents of the CODE
and DAC registers to the DEFAULT state for all channels
configured with CLB = 0 (see CONFIG command).
SW_RESET Command
A software reset command (B[23:0] = 0011_0101_
1001_0110_0011_0000) will reset all CODE, DAC,
and configuration registers to their defaults (including
POWER, DEFAULT, CONFIG, WDOG, and REF registers), simulating a power-on reset.
0
1
0
REF Command
Default Value →
B17
B16
0
RF2
RF1
RF0
0 = DAC Controlled
1 = Always ON
B23 B22 B21 B20 B19
0
B18
Reserved
Table 8. REF Command Format
0
Command Byte
B15 B14 B13 B12 B11 B10 B9
X
X
X
REF Mode:
00: EXT
01: 2.5V
10: 2.0V
11: 4.0V
0
0
X
X
X
X
B8
X
B7 B6 B5 B4 B3 B2 B1 B0
X
X
X
Don’t Care
X
X
X
X
X
Data High Byte
X
X
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
X
X
X
Data Low Byte
�� Maxim Integrated Products 27
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
POWER Command
The POWER command (B[23:20] = 0100) updates the
power mode settings of the selected DACs. DACs that
are not selected do not update their power settings in
response to the command. The new power setting is
determined by bits PD[1:0] (B[7:6]) while the affected
DAC(s) are selected using B[15:8]). If all DACs are powered down and the RF2 bit is not set, the device enters
a STANDBY mode (all analog circuitry is disabled). This
command is inaccessible when a watchdog timeout has
occurred and the watchdog timer is configured with a
safety level of high or max.
Available power modes (PD[1:0]):
Normal (00): DAC channel is active (default),
PD 1kω (01): Power down with 1kω termination to GND,
PD 100kω (10): Power down with 100kω termination to
GND,
PD Hi-Z (11): Power down with high-impedance output.
Table 9. POWER Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
0
0
POWER Command
0
0
0
7
6
5
Reserved
Default Value →
4
3
2
1
B8
0
1
1
1
1
1
Data High Byte
CONFIG Command
The CONFIG command (B[23:16] = 0101) updates the
watchdog, gate, load, and clear mode settings of the
selected DACs. DACs which are not selected do not
update their settings in response to the command. The
new mode settings to be written are determined by bits
B[7:3] while the affected DAC(s) are selected by B[15:8].
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max.
Watchdog Configuration:
WDOG Config settings are written by WC[1:0] (B[7:6]):
DISABLE (WC = 00): Watchdog timeout does not affect
the operation of the selected DAC.
GATE (WC = 01): DAC code is gated to DEFAULT value
in response to watchdog timeouts. Unless otherwise
prohibited by the watchdog safety level, LDAC, CLR,
B6
B5 B4 B3
X
X
Power
Mode:
00 =
Normal
01 = 1kW
10 =
100kW
11 = Hi-Z
DAC Selection
Command Byte
B7
PD1 PD0
1
1
1
0
0
X
B2 B1 B0
X
X
X
X
X
Don’t Care
X
X
X
X
Data Low Byte
and write operations to the CODE and DAC registers are
accepted but will not be reflected on the DAC output until
the watchdog timeout status is reset.
CLR (WC = 10): CODE and DAC register contents are
cleared to DEFAULT value in response to watchdog timeouts. All writes to CODE and DAC registers are ignored
and LDAC or CLR input activity has no effect until the
watchdog timeout status is reset, regardless of watchdog
safety level.
HOLD (WC = 11): DAC code is held at its previously
programmed value in response to watchdog time-out.
All writes to DAC and CODE registers are ignored and
LDAC or CLR input activity has no effect until the watchdog timeout status is reset, regardless of watchdog
safety level.
Note: For the watchdog to timeout and have an impact,
the function must first be enabled and configured using
the WDOG command.
�� Maxim Integrated Products 28
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Gate Configuration:
LDB = 1: DAC latch is transparent, the CODE register
content controls the DAC output directly.
The DAC GATE setting is written by GTB (B5); GATE
operation is as follows:
Clear Configuration:
GTB = 0: Enables software gating function (default), DAC
outputs are gated to their DEFAULT settings as long as
the device remains in GATE mode (set by SW_GATE_
SET and removed by SW_GATE_CLR).
CLEAR_ENB setting is written by CLB (B3); CLEAR_ENB
operation is as follows:
CLB = 0: Clear input and command functions impact the
DAC (default), clearing CODE and DAC registers to their
DEFAULT value.
GTB = 1: Disable software gating function, DAC outputs
are not impacted by GATE mode.
CLB = 1: Clear input and command functions have no
effect on the DAC.
Load Configuration:
The LDAC_ENB setting is written by LDB (B4);
LDAC_ENB operation is as follows:
LDB = 0: DAC latch is operational, enabling LDAC and
LOAD functions (default).
Table 10. CONFIG Command Format
0
1
0
CONFIG Command
0
0
0
7
6
5
Reserved
Default Value →
Command Byte
4
3
2
1
B8
0
1
1
1
1
B6
WDOG
Config:
00:
DISABLE
01: GATE
10: CLR
11: HOLD
DAC Selection
1
B7
1
Data High Byte
1
1
B5
B4
B3
WC1 WC0 GTB LDB CLB
0
0
0
CLEAR_ENB
1
LDAC_ENB
0
GATE_ENB
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
0
B2
B1
B0
X
X
X
Don’t Care
X
X
X
Data Low Byte
�� Maxim Integrated Products 29
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
DEFAULT Command
The DEFAULT command (B[23:20] = 0110) selects the
default value for selected DACs. DACs which are not
selected do not update their default settings in response
to the command. These default values are used for all
future watchdog, clear, and gate operations. The new
default setting is determined by bits DF[2:0] (B[7:5])
while the affected DAC(s) are selected using B[15:8].
This command is inaccessible when a watchdog timeout
has occurred and the watchdog timer is configured with
a safety level of high or max. Note the selected default
values do not apply to resets initiated by SW_RESET
commands or supply cycling, both of which return all
DACs to the values determined by the M/Z input and
reset this register to M/Z mode.
Available default values (DF[2:0]):
M/Z (000): DAC channel defaults to value as selected by
the M/Z input (default).
ZERO (001): DAC channel defaults to zero scale.
MID (010): DAC channel defaults to midscale.
FULL (011): DAC channel defaults to full scale.
RETURN (100): DAC channel defaults to the value programmed by the RETURN command.
No Effect (101, 110, 111): DAC channel default behavior
is unchanged.
Table 11. DEFAULT Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
0
0
DEFAULT Command
0
0
0
7
6
5
Reserved
Default Value →
Command Byte
4
3
2
1
B8
0
1
1
1
1
Data High Byte
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
Default Values:
000: M/Z
001: ZERO
010: MID
011: FULL
100: RETURN
101+: No Effect
DAC Selection
1
B7
DF2 DF1 DF0
1
1
1
0
0
0
Don’t Care
X
X
X
X
X
Data Low Byte
�� Maxim Integrated Products 30
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Applications Information
Offset Error
Power-On Reset (POR)
Offset error indicates how well the actual transfer function matches the ideal transfer function at a single point.
Typically, the point at which the offset error is specified
is at or near the zero-scale point of the transfer function.
Power Supplies and
Bypassing Considerations
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Layout Considerations
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
When power is applied to VDD and VDDIO, the DAC output is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Bypass VDD and VDDIO with high-quality ceramic capacitors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead inductance. Connect the GND to the analog ground plane.
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5823/MAX5824/MAX5825
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise
immunity. Do not run analog and digital signals parallel to
one another, especially clock signals. Avoid routing digital lines underneath the MAX5823/MAX5824/MAX5825
package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Gain Error
Settling Time
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse. Although all bits change,
larger steps may lead to larger glitch energy.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
�� Maxim Integrated Products 31
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Functional Diagram
VDD
REF
RIN 100kI
INTERNAL/EXTERNAL
REFERENCE
(USER OPTION)
CODE
REGISTER
0
DAC
LATCH
0
8-/10-/12-BIT
DAC0
OUT0
BUFFER 0
VDDIO
CODE
CLEAR /
RESET
GATE/
CLEAR /
RESET
LOAD
CHANNEL 0
DAC CONTROL LOGIC
CONTROL LOGIC
SCL
100kI
1kI
POWER-DOWN
DAC CHANNEL 0
DAC CHANNEL 1
OUT1
DAC CHANNEL 2
OUT2
DAC CHANNEL 3
OUT3
DAC CHANNEL 4
OUT4
DAC CHANNEL 5
OUT5
DAC CHANNEL 6
OUT6
SDA
ADDR0
ADDR1
I2C
SERIAL
INTERFACE
CLR
LDAC
IRQ
WATCHDOG
TIMER
M/Z
POR
CODE
REGISTER
7
CODE
MAX5823
MAX5824
MAX5825
CLEAR /
RESET
DAC
LATCH
7
LOAD
CHANNEL 7
DAC CONTROL LOGIC
8-/10-/12-BIT
DAC7
OUT7
BUFFER 7
GATE/
CLEAR /
RESET
100kI
1kI
POWER-DOWN
DAC CHANNEL 7
GND
�� Maxim Integrated Products 32
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Circuits
100nF
RPU =
5kI
RPU =
5kI
100nF
4.7µF
RPU =
5kI
VDDIO
VDD
LDAC
SDA
OUT
DAC
SCL
ADDR0
µC
ADDR1
MAX5823
MAX5824
MAX5825
R1
REF
R2
CLR
R1 = R2
IRQ
M/Z
GND
NOTE: BIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
100nF
RPU =
5kI
RPU =
5kI
4.7µF
RPU =
5kI
VDDIO
VDD
LDAC
SDA
100nF
DAC
OUT
SCL
µC
ADDR0
ADDR1
MAX5823
MAX5824
MAX5825
REF
CLR
IRQ
M/Z
GND
NOTE: UNIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
�� Maxim Integrated Products 33
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
RESOLUTION (BIT)
MAX5823AUP+*
-40°C to +125°C
20 TSSOP
8
MAX5824AUP+*
-40°C to +125°C
20 TSSOP
10
MAX5825AAUP+
-40°C to +125°C
20 TSSOP
12
MAX5825AWP+T*
-40°C to +125°C
20 WLP
12
MAX5825BAUP+*
-40°C to +125°C
20 TSSOP
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)–free/RoHS-compliant package.
*Future product—Contact factory for availability.
T = Tape and reel.
Chip Information
PROCESS: BiCMOS
12
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
20 TSSOP
U20+1
21-0066
90-0116
20 WLP
W202C2+1
21-0059
Refer to
Application
Note 1891
�� Maxim Integrated Products 34
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012
Maxim Integrated Products 35
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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