19-3945; Rev 1; 7/06 IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs The MAX5953A/MAX5953B/MAX5953C/MAX5953D integrate a complete power IC solution for Powered Devices (PD) in a Power-Over-Ethernet (PoE) system, in compliance with the IEEE 802.3af standard. The MAX5953A/MAX5953B/MAX5953C/MAX5953D provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. These devices also integrate a voltage-mode PWM controller with two power MOSFETs connected in a two-switch voltageclamped DC-DC converter configuration. An integrated MOSFET provides PD isolation during detection and classification. All devices guarantee a leakage current offset of less than 10µA during the detection phase. A programmable current limit prevents high inrush current during power-on. The devices feature power-mode undervoltage lockout (UVLO) with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5953A/MAX5953C have an adjustable UVLO threshold with the default value compliant to the 802.3af standard, while the MAX5953B/MAX5953D have a lower and fixed UVLO threshold compatible with some legacy pre-802.3af power-sourcing equipment (PSE) devices. The DC-DC converters are operable in either forward or flyback configurations with a wide input voltage range from 11V to 76V and up to 15W of output power. The voltage-clamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. When using the high-side MOSFET, the controller can be configured as a buck converter. A look-ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. A wide array of protection features include UVLO, over-temperature shutdown, and shortcircuit protection with hiccup current limit for enhanced performance and reliability. Operation up to 500kHz allows for smaller external magnetics and capacitors. The MAX5953A/MAX5953B/MAX5953C/MAX5953D are available in a high-power (2.22W), 7mm x 7mm thermally enhanced thin QFN package. Applications IEEE 802.3af Powered Devices IP Phones Wireless Access Nodes Internet Appliances Security Cameras Computer Telephony Features ♦ Powered Device Interface Fully Integrated IEEE 802.3af-Compliant PD Interface PD Detection and Programmable Classification Signatures Less than 10µA Leakage Current Offset During Detection Integrated MOSFET for Isolation and Inrush Current Limiting Gate Output Allows External Control of the Internal Isolation MOSFET Programmable Inrush Current Control Programmable Undervoltage Lockout (MAX5953A/MAX5953C) ♦ DC-DC Converter Clamped, Two-Switch Power IC for High Efficiency Integrated High-Voltage 0.4Ω Power MOSFETs Up to 15W Output Power Bias Voltage Regulator with Automatic HighVoltage Supply Turn-Off 11V to 76V Wide Input Voltage Range Feed-Forward Voltage-Mode Control for Fast Input Transient Rejection Programmable Undervoltage Lockout Overtemperature Shutdown Indefinite Short-Circuit Protection with Programmable Fault Integration Integrated Look-Ahead Signal for SecondarySide Synchronous Rectification > 90% Efficiency with Synchronous Rectification Up to 500kHz Switching Frequency ♦ High-Power (2.22W), 7mm x 7mm Thermally Enhanced Lead-Free Thin QFN Package Ordering Information PIN-PACKAGE PKG CODE MAX5953AUTM+ PART 48 TQFN T4877-6 MAX5953BUTM+ 48 TQFN T4877-6 MAX5953CUTM+ 48 TQFN T4877-6 MAX5953DUTM+ 48 TQFN T4877-6 Operating junction temperature range is 0°C to +125°C. +Denotes lead-free package. Pin Configuration and Typical Operating Circuit appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5953A/MAX5953B/MAX5953C/MAX5953D General Description MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs ABSOLUTE MAXIMUM RATINGS V+ to VEE ................................................................-0.3V to +90V OUT, PGOOD, PGOOD to VEE .....................-0.3V to (V+ + 0.3V) RCLASS, GATE to VEE ...........................................-0.3V to +12V UVLO to VEE ............................................................ -0.3V to +8V PGOOD to OUT ........................................... -0.3V to (V+ + 0.3V) HVIN, INBIAS, DRNH, XFRMRH, XFRMRL to GND.................................................-0.3V to +80V BST to GND ........................................................... -0.3V to +95V BST to XFRMRH .................................................... -0.3V to +12V PGND to GND .......................................................-0.3V to +0.3V DCUVLO, RAMP, CSS, OPTO, FLTINT, RCFF, RTCT to GND..................................................... -0.3V to +12V SRC, CS to GND...................................................... -0.3V to +6V REGOUT, DRVIN to GND .......................................-0.3V to +12V REGOUT to HVIN .................................................. -80V to +0.3V REGOUT to INBIAS ............................................... -80V to +0.3V PPWM to GND....................................-0.3V to (VREGOUT + 0.3V) Maximum Input/Output Current (Continuous) OUT to VEE ....................................................................500mA V+, RCLASS to VEE .........................................................70mA UVLO, PGOOD, PGOOD to VEE .....................................20mA GATE to VEE ....................................................................80mA REGOUT to GND ............................................................50mA DRNH, XFRMRH, XFRMRL, SRC to GND (Average), TJ = +125°C..................................................................0.9A PPWM to GND ..............................................................±20mA Continuous Power Dissipation* (TA = +70°C) 48-Pin TQFN 7mm X 7mm (derate 27.8mW/°C above +70°C) .............................2222mW θJA ................................................................................36°C/W Operating Ambient Temperature Range ................0°C to +85°C Operating Junction Temperature Range ..............0°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C *As per JEDEC 51 standard. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 µA POWERED DEVICE (PD) INTERFACE DETECTION MODE Input Offset Current Effective Differential Input Resistance (Note 3) IOFFSET dR VIN = 1.4V to 10.1V (Note 2) VIN = 1.4V, up to 10.1V with 1V step 550 VIN rising (Note 4) 20.8 kΩ CLASSIFICATION MODE Classification Current Turn-Off Threshold Classification Current VTH,CLASS ICLASS VIN = 12.6V to 20V, RDISC = 25.5kΩ (Notes 5, 6) 21.8 22.5 Class 0, RRCLASS = 10kΩ 0 2 Class 1, RRCLASS = 732Ω 9.17 11.83 Class 2, RRCLASS = 392Ω 17.29 19.71 Class 3, RRCLASS = 255Ω 26.45 29.55 Class 4, RRCLASS = 178Ω 36.6 41.4 V mA POWER MODE Operating Supply Voltage VIN VIN = (V+ - VEE) Operating Supply Current IIN Measure at V+, not including RDISC, GATE = VEE, HVIN = GND = OUT V 0.4 1 mA MAX5953A/MAX5953C 37.4 38.6 40.2 MAX5953B/MAX5953D 34.3 35.4 36.9 Default Power Turn-On Voltage VUVLO, ON VIN increasing Default Power Turn-Off Voltage VUVLO,OFF VIN decreasing, MAX5953A/MAX5953C 2 67 30 _______________________________________________________________________________________ V V IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs (VIN = (V+ - VEE) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = VEE, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1) PARAMETER Default Power Turn-On/Off Hysteresis Voltage External UVLO Programming Range SYMBOL VHYST,UVLO VIN,EX CONDITIONS MIN MAX5953A/MAX5953C 7.1 MAX5953B/MAX5953D 4 MAX5953A/MAX5953C only (Note 7) 12 TYP MAX UNITS V 67 V UVLO External Reference Voltage VREF,UVLO VUVLO increasing 2.400 2.460 2.522 V UVLO External Reference Voltage Hysteresis VHYST,UVLO Ratio to VREF, UVLO 19.2 20 20.9 % VUVLO = 2.460V -1.5 +1.5 µA 50 440 mV UVLO Bias Current IIN,UVLO UVLO Input Ground-Sense Threshold VTH,G,UVLO (Note 8) UVLO Input Ground-Sense Glitch Rejection 7 Power Turn-Off Voltage, Undervoltage Lockout Deglitch Time tOFF_DLY VIN, VUVLO falling (Note 9) Isolation Switch n-Channel MOSFET On-Resistance RON,ISO Output current = 300mA, VGATE = 5.6V, measured between OUT and VEE Isolation Switch n-Channel MOSFET Off-Threshold Voltage GATE Pulldown Switch Resistance VGSTH RG VGATE - VEE, OUT = V+, output current < 1µA µs 0.32 ms 0.6 1.5 0.5 Power-off mode, VIN = +12V Ω V 38 80 Ω GATE Charging Current IGATE VGATE = 2V 4.5 10 16.5 µA GATE High Voltage VGATE IGATE = 1µA 5.59 5.76 5.93 V VOUT - VEE decreasing, VGATE = 5.75V 1.16 1.23 1.31 V 4.62 4.76 PGOOD Assertion VOUT Threshold (Note 10) PGOOD, PGOOD Assertion VGATE Threshold PGOOD, PGOOD Output Low Voltage VOUTEN VGSEN Hysteresis VGATE - VEE increasing Hysteresis 70 mV 4.91 80 V mV ISINK = 2mA, VOUT ≤ (V+ - 5V) (Note 11) 0.2 V PGOOD Leakage Current GATE = high, V+ - VOUT = 67V (Note 11) 1 µA PGOOD Leakage Current GATE = VEE, PGOOD - VEE = 67V (Note 11) 1 µA VOL,PGOOD _______________________________________________________________________________________ 3 MAX5953A/MAX5953B/MAX5953C/MAX5953D ELECTRICAL CHARACTERISTICS (continued) MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs ELECTRICAL CHARACTERISTICS (DC-DC Controller) (All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER Input Supply Range SYMBOL CONDITIONS VHVIN MIN TYP MAX UNITS 76 V 11 OSCILLATOR (RTCT) PWM Frequency fS 250 kHz Maximum PWM Duty Cycle DMAX Maximum RTCT Frequency fRTCTMAX RTCT Peak Trip Level VTH,RTCT RTCT Valley Trip Level VTL,RTCT 1 V RTCT Input Bias Current IIN,RTCT ±1 µA RTCT Discharge MOSFET RDS(ON) RDIS,RTCT 47 % 1 MHz 0.51 x VREGOUT V (Note 12) Sinking 50mA 35 RTCT Discharge Pulse Width 85 Ω 50 ns 110 ns LOOK-AHEAD LOGIC (PPWM) PPWM to Output Propagation Delay tPPWM VPPWM rising to VXFRMRL falling PPWM Output High VOH,PPWM Sourcing 2mA PPWM Output Low VOL,PPWM Sinking 2mA 7.0 11.0 V 0.2 V 5.5 V PWM COMPARATOR (OPTO, RAMP, RCFF) Common-Mode Input Range VCM_PWM 0 Input Offset Voltage 10 Input Bias Current RAMP to XFRMRL Propagation Delay -2 mV +2 µA From VRAMP (50mV overdrive) rising to VXFRMRL rising 100 ns Minimum OPTO Voltage VCSS = 0V, OPTO sinking 2mA 1.47 V Minimum RCFF Voltage RCFF sinking 2mA 2.18 V tCOMPARATOR REGOUT LDO (REGOUT) REGOUT Voltage Set Point REGOUT Load Regulation REGOUT Dropout Voltage VREGOUT INBIAS unconnected, VHVIN = 11V to 76V 8.3 8.75 9.2 VINBIAS = VHVIN = 11V to 76V 9.5 10.6 11.0 INBIAS unconnected, VHVIN = 15V, IREGOUT = 0 to 30mA 0.25 VINBIAS = VHVIN = 15V, IREGOUT = 0 to 30mA 0.25 INBIAS unconnected, IREGOUT = 30mA 1.25 VINBIAS = VHVIN, IREGOUT = 30mA 1.25 REGOUT Undervoltage Lockout Threshold REGOUT rising REGOUT Undervoltage Lockout Threshold Hysteresis REGOUT falling 4 V V 6.6 7.0 0.7 _______________________________________________________________________________________ 7.4 V V V IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs (All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SOFT-START (CSS) Soft-Start Current ICSS VCSS = 0V 33 µA 80 µA 2.7 V 0.75 V INTEGRATING FAULT PROTECTION FLTINT Source Current IFLTINT FLTINT Trip Point VFLTINT rising FLTINT Hysteresis INTERNAL POWER FETs On-Resistance RON,POWER VDRVIN = VBST = 9V, VXFRMRH = VSRC = 0V, IDS = 50mA Off-State Leakage Current 0.4 -5 Total Gate Charge Per Power FET 0.8 Ω +10 µA 15 nC HIGH-SIDE DRIVER Low to High Latency tLH-HS Driver delay until FET VGS reaches 0.9 x (VBST - VXFRMRH) and is fully on 80 ns High to Low Latency tHL-HS Driver delay until FET VGS reaches 0.1 x (VBST - VXFRMRH) and is fully off 40 ns Output Drive Voltage VBST BST to XFRMRH with high side on 8 V Low to High Latency tLH-LS Driver delay until FET VGS reaches 0.9 x VDRVIN and is fully on 80 ns High to Low Latency tHL-LS Driver delay until FET VGS reaches 0.1 x VDRVIN and is fully off 40 ns LOW-SIDE DRIVER CURRENT-LIMIT COMPARATOR (CS) Current-Limit Threshold Voltage VILIM Current-Limit Input Bias Current IBILIM 0 < VCS < 0.3V Propagation Delay to XFRMRL tdILIM From VCS rising (10mV overdrive) to VXFRMRL rising 140 156 -2 172 mV +2 µA 160 ns tPPWMD 200 ns tPWQB 300 ns BOOST VOLTAGE CIRCUIT (See Figure 9, QB) Driver Output Delay One-Shot Pulse Width QB RDSON Sinking 20mA 30 60 Ω THERMAL SHUTDOWN Shutdown Temperature TSH Thermal Hysteresis TH Temperature rising +160 °C 20 °C _______________________________________________________________________________________ 5 MAX5953A/MAX5953B/MAX5953C/MAX5953D ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued) MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued) (All voltages referenced to GND, unless otherwise noted. VHVIN = +48V, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, VCSS = VCS = 0V, VRAMP = VDCUVLO = 3V, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 1.14 1.26 1.38 UNITS UNDERVOLTAGE LOCKOUT (DCUVLO) Threshold Voltage VREF,DCUVLO Hysteresis VHYS,DCUVLO Input Bias Current IIN,DCUVLO VDCUVLO rising 140 VDCUVLO = 3V -100 V mV +100 nA SUPPLY CURRENT From VHVIN = 11V to 76V, VCSS = 0V, VINBIAS = 11V 0.7 1.5 Supply Current From VINBIAS = 11V to 76V, VCSS = 0V, VHVIN = 76V 4.4 6.4 Standby Supply Current VDCUVLO = 0V From VHVIN = 76V, VOPIO = 4V mA 7 1 Note 1: Note 2: Note 3: mA Limits at 0°C are guaranteed by design, unless otherwise noted. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between V+ and VEE without any external resistance. Note 4: Classification current is turned off whenever the IC is in power mode. Note 5: See Table 2 in the Classification Mode section. RDISC and RRCLASS must be 1%, 100ppm or better. ICLASS includes the IC bias current and the current drawn by RDISC. Note 6: See the Thermal Dissipation section. Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turnon threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO does not exceed its maximum rating of 8V when VIN is at the maximum voltage. Note 8: When VUVLO is below VTH,G,UVLO, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (VUVLO,ON). Note 9: An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V). Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D. Note 11: PGOOD references to OUT while PGOOD references to VEE. Note 12: Output switching frequency is 1/2 oscillator frequency. IIN dRi ≅ 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET ≅ IINi - VINi dRi IINi + 1 dRi IINi IOFFSET VINi 1V VINi + 1 VIN Figure 1. Effective Differential Input Resistance/Offset Current 6 _______________________________________________________________________________________ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs IIN + IRDISC 0.3 0.2 0.1 CLASS 4 40 35 CLASS 3 30 25 CLASS 2 20 15 CLASS 1 10 5 0 0 2 4 6 8 0 10 5 10 15 20 25 2.5 2.0 1.5 1.0 0.5 0 30 0 2 4 6 8 INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT OFFSET CURRENT vs. INPUT VOLTAGE NORMALIZED UVLO vs. TEMPERATURE PGOOD OUTPUT LOW VOLTAGE vs. CURRENT -1.5 -2.0 -2.5 -3.0 1.008 1.006 1.004 1.002 1.000 0.998 200 150 100 0.996 50 0.994 -3.5 10 MAX5953A/B/C/D toc06 -1.0 250 VPGOOD (mV) -0.5 1.010 MAX5953A/B/C/D toc05 MAX5953A/B/C/D toc04 0 0.992 -4.0 2 4 6 8 10 0 0.990 0 25 50 75 100 0 125 10 15 TEMPERATURE (°C) ISINK (mA) OUT LEAKAGE CURRENT vs. TEMPERATURE INRUSH CURRENT CONTROL (VIN = 48V) DCUVLO THRESHOLD vs. TEMPERATURE MAX5953A/B/C/D toc08 VOUT = 48V 100 DCUVLO RISING VGATE 5V/div 0V IINRUSH 100mA/div 1 PGOOD 50V/div 0.1 25 50 75 TEMPERATURE (°C) 100 125 1.2800 0V VOUT TO VEE 50V/div 10 1.2825 4ms/div VDCUVLO (V) MAX5953A/B/C/D toc07 1000 0 5 INPUT VOLTAGE (V) 20 MAX5953A/B/C/D toc09 0 OUT LEAKAGE CURRENT (nA) 3.0 INPUT VOLTAGE (V) NORMALIZED UVLO 0 INPUT OFFSET CURRENT (µA) CLASS 0 3.5 MAX5953A/B/C/D toc03 45 EFFECTIVE DIFFERENTIAL INPUT RESISTANCE (MΩ) 0.4 50 MAX5953A/B/C/D toc02 DETECTION CURRENT (mA) RDISC = 25.5kΩ CLASSIFICATION CURRENT (mA) MAX5953A/B/C/D toc01 0.5 1.2775 0A 1.2750 0V 1.2725 0 25 50 75 100 125 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX5953A/MAX5953B/MAX5953C/MAX5953D Typical Operating Characteristics (VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = V EE, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) CLASSIFICATION CURRENT EFFECTIVE DIFFERENTIAL INPUT DETECTION CURRENT vs. INPUT VOLTAGE RESISTANCE vs. INPUT CURRENT vs. INPUT VOLTAGE Typical Operating Characteristics (continued) (VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) HVIN AND INBIAS INPUT CURRENT HVIN STANDBY CURRENT HVIN INPUT CURRENT vs. TEMPERATURE vs. TEMPERATURE vs. TEMPERATURE 245 210 175 4.5 4.4 140 4.3 105 4.2 4.0 3.5 2.5 2.0 25 50 75 100 125 1.0 0 0 25 50 75 100 50 75 100 TEMPERATURE (°C) REGOUT VOLTAGE vs. INPUT VOLTAGE REGOUT VOLTAGE vs. TEMPERATURE REGOUT VOLTAGE vs. LOAD CURRENT 8.81 8.80 8.79 8.82 8.80 8.78 8.78 8.76 8.77 8.74 8.76 8.72 8.75 VHVIN = 15V INBIAS FLOATING GND = VEE 8.80 VREGOUT (V) 8.84 37 50 63 76 8.75 8.70 8.70 24 8.65 0 25 50 75 100 125 0 5 10 15 20 VHIN (V) TEMPERATURE (°C) IREGOUT (mA) REGOUT VOLTAGE vs. INPUT VOLTAGE REGOUT VOLTAGE vs. TEMPERATURE REGOUT VOLTAGE vs. LOAD CURRENT 10.72 10.66 10.64 10.71 10.70 10.69 25 30 25 30 10.75 MAX5953A/B/C/D toc18 10.73 VREGOUT (V) 10.68 VHVIN = VINBIAS = 48V 10.74 VHVIN = VINBIAS = 15V GND = VEE 10.70 VREGOUT (V) HVIN = INBIAS GND = VEE MAX5953A/B/C/D toc17 10.75 MAX5953A/B/C/D toc16 10.70 125 MAX5953A/B/C/D toc15 8.86 VREGOUT (V) 8.82 VHVIN = 48V INBIAS FLOATING 8.88 8.85 MAX5953A/B/C/D toc14 8.90 MAX5953A/B/C/D toc13 INBIAS FLOATING GND = VEE 11 25 0 125 TEMPERATURE (°C) 8.83 VREGOUT (V) 0.5 TEMPERATURE (°C) 8.85 8.84 IHVIN 1.5 4.0 0 IINBIAS 3.0 4.1 0 VHVIN = VINBIAS = 76V 4.5 70 35 MAX5953A/B/C/D toc12 4.6 5.0 INPUT CURRENT (mA) fHVIN VDCUVLO = 0V 280 INBIAS FLOATING VHVIN = 76V REGOUT = DRVIN 4.7 IHVIN (mA) STANDBY CURRENT (µA) 315 4.8 MAX5953A/B/C/D toc11 350 MAX5953A/B/C/D toc10 385 VREGOUT (V) MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs 10.65 10.60 10.68 10.62 10.55 10.67 10.66 10.60 24 37 50 VHIN (V) 8 10.50 10.65 11 63 76 0 25 50 75 TEMPERATURE (°C) 100 125 0 5 10 15 IREGOUT (mA) _______________________________________________________________________________________ 20 IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs 6.6 FALLING 6.4 6.2 450 400 350 RRTCT = 24.3kΩ CRTCT = 100pF 300 25 50 75 100 125 32.0 31.5 31.0 0 25 50 75 100 0 125 25 50 75 100 MINIMUM RCFF AND OPTO LEVELS vs. TEMPERATURE CURRENT-LIMIT COMPARATOR THRESHOLD vs. TEMPERATURE PPWM TO XFRMRL SKEW vs. TEMPERATURE 0.157 0.155 0.154 0.153 1.50 0.152 1.25 99 50 75 100 125 0 25 50 75 100 TEMPERATURE (°C) FLTINT CURRENT vs. TEMPERATURE FLTINT SHUTDOWN VOLTAGE vs. TEMPERATURE 2.8 2.7 2.6 VFLTINT (V) 82 81 80 79 RISING 2.4 2.3 2.2 77 2.1 76 2.0 25 50 75 TEMPERATURE (°C) 100 125 25 50 75 100 125 0.7 0.6 0.5 0.4 0.3 0.2 FALLING 0.1 1.9 75 92 POWER MOSFETS RDS(ON) vs. TEMPERATURE 2.5 78 93 0 RDS(ON) (Ω) 83 94 125 MAX5953A/B/C/D toc26 2.9 MAX5953A/B/C/D toc25 84 95 TEMPERATURE (°C) TEMPERATURE (°C) 85 96 90 0.150 25 97 91 0.151 1.00 98 MAX5953A/B/C/D toc27 OPTO 0.156 100 125 MAX5953A/B/C/D toc24 0.158 VREGOUT (V) 2.00 HVIN RISING 0.159 PPWM TO XFRMRL SKEW (ns) MAX5953A/B/C/D toc22 RCFF 1.75 0.160 MAX5953A/B/C/D toc23 TEMPERATURE (°C) 2.25 0 32.5 TEMPERATURE (°C) 2.50 0 33.0 TEMPERATURE (°C) 2.75 IFLTINT (µA) 33.5 200 0 MAX5953A/B/C/D toc21 500 250 6.0 VRCFF (V), VOPTO (V) RRTCT = 12kΩ CRTCT = 100pF 550 34.0 SOFT-START CURRENT (µA) 6.8 MAX5953A/B/C/D toc20 7.0 600 OPERATING FREQUENCY (kHz) RISING 7.2 REGOUT UVLO VOLTAGE (V) MAX5953A/B/C/D toc19 7.4 SOFT-START CURRENT vs. TEMPERATURE OPERATING FREQUENCY vs. TEMPERATURE REGOUT UVLO VOLTAGE vs. TEMPERATURE 0 0 25 50 75 TEMPERATURE (°C) 100 125 0 25 50 75 100 125 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX5953A/MAX5953B/MAX5953C/MAX5953D Typical Operating Characteristics (continued) (VIN = (V+ - VEE) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = VEE, CINBIAS = 1µF, CREGOUT = 2.2µF, RRTCT = 25kΩ, CRTCT = 100pF, CBST = 0.22µF, TJ = 0°C to +125°C, unless otherwise noted. Typical values are at TJ = +25°C. All voltages are referenced to VEE, unless otherwise noted.) MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Pin Description PIN NAME 1, 2, 3, 5, 7, 12, 13, 14, 17, 19, 35, 38, 46, 47, 48 N.C. 4 V+ FUNCTION No Connection. Not internally connected. Make no electrical connection to these pins. Positive Input Power. Referenced to VEE. Undervoltage Lockout Programming Input for PD Interface. UVLO is referenced to VEE. When UVLO is above its threshold, the device enters the power mode. Connect UVLO to VEE to use the default undervoltage lockout threshold. Connect UVLO to the center of an external resistor-divider between V+ and VEE to define a threshold externally. The series resistance value of the external resistors must add to 25.5kΩ (±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, drive UVLO between VTH,G,UVLO and VREF,UVLO. 6 (MAX5953A/MAX5953C) UVLO 6 (MAX5953B/MAX5953D) N.C. 8 RCLASS Classification Setting for PD Interface. RCLASS is referenced to VEE. Add a resistor from RCLASS to VEE to set a PD class (see Tables 1 and 2). 9 GATE Gate of Internal Isolation n-Channel Power MOSFET. GATE is referenced to VEE. GATE sources 10µA when the device enters power mode. Connect an external 100V ceramic capacitor from GATE to OUT to program the inrush current. Drive GATE to VEE to turn off the internal MOSFET. The detection and classification functions operate normally when GATE is driven to VEE. 10, 11 VEE Negative Input Power. Source of the integrated isolation n-channel power MOSFET. 15, 16 OUT Output Voltage. OUT is referenced to VEE. OUT is connected to the drain of the integrated isolation n-channel power MOSFET. Connect OUT to GND. No Connection. Not internally connected. Make no electrical connection to this pin. 18 (MAX5953A/MAX5953B) PGOOD Active-High, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is referenced to OUT. PGOOD goes high impedance when VOUT is within 1.2V of VEE and when VGATE is 5V above VEE. Otherwise, PGOOD is internally pulled to OUT (given that VOUT is at least 5V below V+). PGOOD can be connected directly to CSS or DCUVLO to enable/disable the DC-DC converter. 18 (MAX5953C/MAX5953D) PGOOD Active-Low, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is referenced to VEE. PGOOD is pulled to VEE when VOUT is within 1.2V of VEE and when VGATE is 5V above VEE. Otherwise, PGOOD goes high impedance. 20 CS Current-Sense Input for PWM Controller. CS is referenced to PGND. The current-limit threshold is internally set to 156mV relative to PGND. The device has an internal noise filter. If necessary, connect an external RC filter from CS to PGND for additional filtering. 21 PPWM PWM Pulse Output. Referenced to GND. PPWM leads the internal power MOSFET pulse by approximately 100ns. 10 22 GND 23 PGND 24 CSS Signal Ground of PWM Controller. Connect GND to PGND. Power Ground of the DC-DC Converter Power Stage. Connect PGND to GND. Soft-Start Timing Capacitor Connection for PWM Controller. CSS is referenced to GND. Connect a 0.01µF or greater ceramic capacitor from CSS to GND. Connect to PGOOD to automatically enable the PWM controller from the PD interface. ______________________________________________________________________________________ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs PIN NAME FUNCTION 25 OPTO PWM Comparator Inverting Input. OPTO is referenced to GND. Connect the collector of the optotransistor to OPTO and a pullup resistor to REGOUT. 26, 27 SRC Source Connection of Low-Side Power MOSFET in the Two-Switch Power Stage of the DCDC Converter. Connect SRC to PGND with a low-value resistor for current limiting. 28, 29 XFRMRL Low-Side Connection for the Isolation Transformer. Drain terminal of low-side power MOSFET in the two-switch power stage of the DC-DC converter. 30 DRVIN Supply Input for the Gate-Driver of Internal Power MOSFETs. DRVIN is referenced to PGND. Bypass DRVIN with at least 0.1µF to PGND. Connect DRVIN to REGOUT. 31, 32 XFRMRH 33, 34 DRNH 36 BST Boost Input for the DC-DC Converter. BST is the boost connection point for the high-side MOSFET driver. Connect a minimum 0.1µF capacitor from BST to XFRMRH with short and wide PC board traces. 37 DCUVLO DC-DC Converter Undervoltage Lockout Input. DCUVLO is referenced to GND. Connect a resistor-divider from HVIN to DCUVLO to GND to set the UVLO threshold. 39 HVIN DC-DC Converter Positive Input Power Supply. HVIN is referenced to GND. Connect HVIN to V+. 40 INBIAS 41 High-Side Connection for the Isolation Transformer. Source connection of high-side power MOSFET in the two-switch power stage of the DC-DC converter. Drain Connection of High-Side MOSFET in the Two-Switch Power Stage of the DC-DC Converter. Connect DRNH to the most positive rail of the input supply. Bypass DRNH appropriately to handle the heavy switching current through the transformer. Input from the Rectified Bias Winding to the DC-DC Converter. INBIAS is referenced to GND. INBIAS is the input to the internal linear voltage regulator (REGOUT). Internal Regulator Output. REGOUT is used for the DC-DC converter gate driver. REGOUT is referenced to GND. VREGOUT is always present as long as HVIN is powered with a REGOUT voltage above the DCUVLO threshold. Bypass REGOUT to GND with a minimum 2.2µF ceramic capacitor. RTCT Oscillator Frequency Set Input for the PWM Controller. RTCT is referenced to GND. Connect a resistor from RTCT to REGOUT and a ceramic capacitor from RTCT to GND to set the oscillator frequency. 43 FLTINT Fault Integration Input for PWM Controller. FLTINT is referenced to GND. During persistent current-limit faults, a capacitor connected to FLTINT is charged with an internal 80µA current source. Switching is terminated when VFLTINT reaches 2.7V. An external resistor connected in parallel discharges the capacitor. Switching resumes when VFLTINT drops to 1.9V. 44 RCFF Feed-Forward Input for PWM Controller. RCFF is referenced to GND. To generate the PWM ramp, connect a resistor from RCFF to HVIN and a capacitor from RCFF to GND. 45 RAMP Ramp Sense Input for PWM Controller. Connect RAMP to RCFF. — EP 42 Exposed Paddle. EP is internally unconnected and must be connected to VEE externally. To improve power dissipation, solder the exposed paddle to a copper pad on the PC board. ______________________________________________________________________________________ 11 MAX5953A/MAX5953B/MAX5953C/MAX5953D Pin Description (continued) MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Typical Application Circuit POWER-OVER SIGNAL PAIRS 3 VREG Rx 6 1 PHY 2 -48VRTN RJ-45 SGND Tx + + - - 4 5 7 8 POWER-OVER SPAIR PAIRS Figure 2. RJ-45 Connector, PoE Magnetic, and Input Diode Bridges 12 ______________________________________________________________________________________ -48V ______________________________________________________________________________________ -48V D1 60V C1 68nF C3 220pF R5 200kΩ R3 (RDISC) 25.5kΩ C4 4.7µF C2 22µF 63V OUT GATE DRVIN REGOUT RCFF RAMP VEE RCLASS UVLO C6 0.1µF R6 24.9kΩ 16 9 30 41 44 45 10 8 6 V+ R8 OPEN R9 1MΩ RTCT 42 FLTINT 43 CSS C7 100pF 24 C8 0.1µF 22 GND 25 OPTO MAX5953A CS 20 PGND C9 220pF PGND 23 21 BST PPWM SRC R12 604Ω C10 0.33µF R11 0.1Ω INBIAS XFRMRL XFRMRH 26, 27 R10 100Ω DRNH 33, 34 *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE R3, 25.5kΩ. R7 1.78kΩ C5 6800pF R4 (RRCLASS) 255Ω R2* OPEN R1* OPEN 4 HVIN 39 40 28, 29 31, 32 36 C15 1µF C E R13 15Ω 11T D3 25T GND COMP FB LED C16 0.15µF D6 D2 U2 FOD2712 C11 0.1µF C17 0.047µF 22T R16 562Ω C14 0.0047µF C12A 47µF D4 R15 16.2kΩ R14 143kΩ C12B 47µF SGND C13 0.1µF OUT MAX5953A/MAX5953B/MAX5953C/MAX5953D -48VRTN 37 DCUVLO 18 R16 316kΩ PGOOD R17 14.7kΩ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Figure 3. Typical Application Circuit 13 14 -48V D1 60V -48VRTN C1 68nF R3 (RDISC) 25.5kΩ ______________________________________________________________________________________ 16 9 30 41 44 45 10 8 6 OUT GATE DRVIN REGOUT RCFF RAMP VEE RCLASS UVLO V+ RTCT 42 FLTINT 43 CSS 24 22 GND 25 OPTO MAX5953A 23 20 CS DRNH 33, 34 PGND PGND HVIN *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE R3, 25.5kΩ. RRCLASS R2* R1* 4 37 DCUVLO 18 PGOOD 39 26, 27 SRC INBIAS XFRMRL XFRMRH BST PPWM 21 40 28, 29 31, 32 36 C E FB GND COMP U2 FOD2712 LED SGND VOUT MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Figure 4. For higher power applications, the MAX5953A/MAX5953B/MAX5953C/MAX5953D can be used in a two-switch forward converter configuration IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs PD Interface The MAX5953A/MAX5953B/MAX5953C/MAX5953D include complete interface function for a PD to comply with the IEEE 802.3af standard in a PoE system. They provide the PD with a detection signature, a classification signature, and an integrated isolation switch with programmable inrush current control. An integrated MOSFET provides PD isolation during detection and classification. All devices guarantee a leakage current offset of less than 10µA during the detection phase. A programmable current limit prevents high inrush current during power-on. The device features power-mode UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair-cable resistive drop and to assure glitch-free transition between detection, classification, and power-on/-off phases. The MAX5953A/ MAX5953C have an adjustable UVLO threshold with the default value compliant to the 802.3af standard, while the MAX5953B/MAX5953D have a lower and fixed UVLO threshold compatible with some legacy pre-802.3af PSE. Table 1. PD Power Classification/ RRCLASS Selection CLASS USAGE RRCLASS (Ω) MAXIMUM POWER USED BY PD (W) 0 Default 10k 0.44 to 12.95 1 Optional 732 0.44 to 3.84 2 Optional 392 3.84 to 6.49 3 Optional 255 6.49 to 12.95 4 Not Allowed 178 Reserved* *Class 4 reserved for future use. Operating Modes Depending on the input voltage (VIN = V+ - VEE), the PD front-end section of the MAX5953A/MAX5953B/ MAX5953C/MAX5953D operate in three different modes: PD detection signature, PD classification, and PD power. All voltage thresholds are designed to operate with or without the optional diode bridge while still complying with the IEEE 802.3af standard (see Figure 2). Detection Mode (1.4V ≤ VIN ≤ 10.1V) In detection mode, the power source equipment (PSE) applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum), and records the corresponding current measurements at those two points. The PSE then computes ∆V/∆I to ensure the presence of the 25.5kΩ signature resistor. In this mode, most interface circuitry of the MAX5953A/MAX5953B/MAX5953C/MAX5953D is off and the offset current is less than 10µA. Classification Mode (12.6V ≤ VIN ≤ 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. The IEEE 802.3af standard defines five different classes as shown in Table 1. An external resistor (RRCLASS) connected from RCLASS to VEE sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the IC exhibits a current characteristic with values indicated in Table 2. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by the 25.5kΩ detection signature resistor and the supply current of the IC so the total current drawn by the PD is within the IEEE 802.3af standard figures. The classification current is turned off whenever the device is in power mode. Table 2. Setting Classification Current CLASS RRCLASS (Ω) VIN* (V) CLASS CURRENT SEEN AT VIN (mA) MIN IEEE 802.3af PD CLASSIFICATION CURRENT SPECIFICATION (mA) MAX MIN MAX 0 10k 12.6 to 20 0 2.00 0 4 1 732 12.6 to 20 9.17 11.83 9 12 2 392 12.6 to 20 17.29 19.71 17 20 3 255 12.6 to 20 26.45 29.55 26 30 4 178 12.6 to 20 36.60 41.40 36 44 *VIN is measured across the MAX5953A/MAX5953B/MAX5953C/MAX5953D input pins (V+ - VEE), which do not include the diode bridge voltage drop. ______________________________________________________________________________________ 15 MAX5953A/MAX5953B/MAX5953C/MAX5953D Detailed Description MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Power Mode During power mode, when VIN rises above the undervoltage lockout threshold (VUVLO,ON), the IC gradually turns on the internal n-channel MOSFET Q1 (see Figure 8). The IC charges the gate of Q1 with a constant current source (10µA, typ). The drain-to-gate capacitance of Q1 limits the voltage rise rate at the drain of the MOSFET, thereby limiting the inrush current. To further reduce the inrush current, add external drain-to-gate capacitance (see the Inrush Current Limit section). When the drain of Q1 is within 1.2V of its source voltage and its gate-tosource voltage is above 5V, the MAX5953A/MAX5953B assert the PGOOD output (MAX5953C/MAX5953D assert the PGOOD output). The IC has a wide UVLO hysteresis and turn-off deglitch time to compensate for the high impedance of the twisted-pair cable. Undervoltage Lockout for PD Interface The IC operates up to a 67V supply voltage with a default UVLO turn-on (VUVLO,ON) set at 38.6V (MAX5953A/ MAX5953C) or 35.4V (MAX5953B/MAX5953D) and a UVLO turn-off (VUVLO,OFF) set at 30V. The MAX5953A/ MAX5953C have an adjustable UVLO threshold using a resistor-divider connected to UVLO (see Figure 3). When the input voltage goes below the UVLO threshold for more than tOFF_DLY, the MOSFET turns off. To adjust the UVLO threshold, connect an external resistor-divider from V+ to UVLO to VEE. Use the following equations to calculate R1 and R2 for a desired UVLO threshold: R2 = 25.5kΩ × VREF,UVLO VIN,EX R1 = 25.5kΩ − R2 where VIN,EX is the desired UVLO threshold. Since the resistor-divider replaces the 25.5kΩ PD detection resistor, ensure that the sum of R1 and R2 equals 25.5kΩ ±1%. When using the external resistor-divider, MAX5953A/ MAX5953C have an external reference voltage hysteresis of 20% (typ). In other words, when UVLO is programmed externally, the turn-off threshold is 80% (typ) of the new UVLO threshold. Inrush Current Limit The IC charges the gate of the internal MOSFET with a constant current source (10µA, typ). The drain-to-gate capacitance of the MOSFET limits the voltage rise rate at the drain, thereby limiting the inrush current. Add an external capacitor from GATE to OUT to further reduce the inrush current. Use the following equation to calculate the inrush current: 16 IINRUSH = IG × COUT CGATE The recommended typical inrush current for a PoE application is 100mA. PGOOD/PGOOD Output PGOOD is an open-drain, active-high logic output. PGOOD goes high impedance when V OUT is within 1.2V of V EE and when GATE is 5V above V EE . Otherwise, PGOOD is pulled to VOUT (given that VOUT is at least 5V below V+). Connect PGOOD directly to CSS to enable/disable the DC-DC converter. PGOOD is an open-drain, active-low logic output. PGOOD is pulled to V EE when V OUT is within 1.2V of V EE and when GATE is 5V above VEE. Otherwise, PGOOD goes high impedance. Connect a 100kΩ pullup resistor from PGOOD to V+ if needed. Thermal Dissipation Thermal shutdown limits total power dissipation in the IC. If the junction temperature exceeds +160°C, thermal shutdown is enabled to turn off the MAX5953A/ MAX5953B/MAX5953C/MAX5953D, allowing the IC to cool. The IC turns on after the junction temperature cools by 20°C. DC-DC Converter The MAX5953A/MAX5953B/MAX5953C/MAX5953D isolated PWM power ICs feature integrated switching power MOSFETs connected in a voltage-clamped, two-transistor, power-circuit configuration. These devices can be used in both forward and flyback configurations with a wide 11V to 76V input voltage range. The voltageclamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. A look-ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. A wide array of protection features include UVLO, overtemperature shutdown, and short-circuit protection with hiccup current-limit for enhanced performance and reliability. Operation up to 500kHz allows smaller external magnetics and capacitors. Power Topology The two-switch forward-converter topology offers outstanding robustness against faults and transformer saturation while affording efficient use of 0.4Ω power MOSFETs. Voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle similar to that of currentmode controlled topologies. ______________________________________________________________________________________ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs external resistive divider (R16 and R17) connected to DCUVLO (see Figure 3). Use the following equation to calculate R16 and R17: Voltage-Mode Control and the PWM Ramp where VDCUVLOIN is the desired input voltage lockout level and VDCUVLO is the undervoltage lockout threshold (1.25V, typ). Select the R17 resistance value between 100kΩ and 500kΩ. For voltage-mode control, the feed-forward PWM ramp is generated at RCFF. From RCFF, connect a capacitor to GND and a resistor to HVIN. The ramp generated is applied to the noninverting input of the PWM comparator at RAMP and has a minimum voltage of approximately 2V. The slope of the ramp is determined by the voltage at HVIN and affects the overall loop gain. The ramp peak must remain below the 5.5V dynamic range of RCFF. Assuming the maximum duty cycle approaches 50% at a minimum input voltage (PWM UVLO turnon threshold), use the following formula to calculate the minimum value of either the ramp capacitor or resistor: RRCFF × CRCFF ≥ VIN,EX 2 × fS × VR(P−P) where fS is the switching frequency, VR(P-P) is the peakto-peak ramp voltage (2V, typ). Select RRCFF resistance value between 200kΩ and 600kΩ. Maximize the signal-to-noise ratio by setting the ramp peak as high as possible. Calculate the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the PWM comparator to the output) using the following formula: GPS = NSP x RRCFF x CRCFF x fS where NSP is the secondary to primary power transformer turns ratio. Secondary-Side Synchronization The MAX5953A/MAX5953B/MAX5953C/MAX5953D provide convenient synchronization for optional secondary-side synchronous rectifiers. Figure 5 shows the connection diagram with a high-speed optocoupler. Choose an optocoupler with a propagation delay of less than 80ns. The synchronizing pulse is generated approximately 110ns ahead of the main pulse that drives the two power MOSFETs. ⎛ R16 ⎞ VDCUVLOIN = VDCUVLO × ⎜1 + ⎟ ⎝ R17 ⎠ Optocoupled Feedback Isolated voltage feedback is achieved by using an optocoupler as shown in Figure 3. Connect the collector of the optotransistor to OPTO and a pullup resistor between OPTO and REGOUT. Internal Regulators As soon as power is provided to HVIN, internal power supplies power the DCUVLO detection circuitry. REGOUT is used to drive the internal power MOSFETs. Bypass REGOUT to GND with a minimum 2.2µF ceramic capacitor. The HVIN LDO steps down VHVIN to a nominal output voltage (VREGOUT) of 8.75V. A second parallel LDO powers REGOUT from INBIAS. A tertiary winding connected through a diode to INBIAS powers up REGOUT once switching commences. This powers REGOUT to 10.5V (typ) and shuts off the current flowing from HVIN to REGOUT. This results in a lower onchip power dissipation and higher efficiency. MAX5953A MAX5953B MAX5953C MAX5953D +5V R PPWM PGND C Undervoltage Lockout for DC-DC Converter Connect PGOOD to DCUVLO to ensure the PD interface is ready prior to the DC-DC converter. The DCUVLO block monitors the input voltage at HVIN through an Figure 5. Secondary-Side Synchronous Rectifier Driver Using a High-Speed Optocoupler ______________________________________________________________________________________ 17 MAX5953A/MAX5953B/MAX5953C/MAX5953D The two-switch power topology recovers energy stored in both the magnetizing and the parasitic leakage inductances of the transformer. The Typical Application Circuit, Figure 3, shows the schematic diagram of a -48V input flyback converter using the MAX5953A. Figure 4 shows the schematic diagram of a -48V input forward converter and a 5V, 3A output isolated power supply. MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Soft-Start Program the MAX5953A/MAX5953B/MAX5953C/ MAX5953D soft-start with an external capacitor (CCSS) connected between CSS and GND. When the device turns on, C CSS charges with a constant current of 33µA, ramping up to 7.3V. During this time, the feedback input (OPTO) is clamped to VCSS + 0.6V. This initially holds the duty cycle lower than the value the regulator imposes, thus preventing voltage overshoot at the output. When the IC turns off, the soft-start capacitor internally discharges to GND. I ×t CFLTINT ≅ FLTINT SH 1.4 where IFLTIN is typically 80µA, and tSH is the desired ignore time during which current-limit events from the current-limit comparator are ignored. This is an approximate formula; some testing may be required to fine tune the actual value of the capacitor. Calculate the approximate bleed resistor needed for the desired recovery time using the following formula: Oscillator The oscillator is externally programmable through a resistor connected from RTCT to REGOUT and a capacitor connected from RTCT to GND. The PWM frequency is one-half the frequency seen at RTCT with a 50% duty cycle. Use the following formula to calculate the oscillator components: RRTCT ≅ 1 ⎛ ⎞ VREGOUT 2fs (CRTCT + CPCB )In⎜ ⎟ ⎝ VREGOUT − VTH,RTCT ⎠ where CPCB is the stray capacitance on the PC board (14pF, typ), VTH,RTCT is the RTCT peak trip level, and fS is the switching frequency. Integrating Fault Protection The integrating fault protection feature allows the IC to ignore transient overcurrent conditions for a programmable amount of time, giving the power-supply time to behave like a current source to the load. This can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. The ignore time is programmed externally by connecting a capacitor from FLTINT to GND. Under sustained overcurrent faults, the voltage across this capacitor ramps up toward the FLTINT shutdown threshold (2.7V, typ). When V FLTINT reaches the shutdown threshold, the power supply shuts down. A high-value bleed resistor connected in parallel with the FLTINT capacitor allows the capacitor to discharge toward the restart threshold (1.9V, typ). FLTINT drops to the restart threshold allowing for soft-starting the supply again. The fault integration circuit works by forcing an 80µA current into FLTINT for one clock cycle every time the current-limit comparator ILIM (Figure 9) trips. Use the following formula to calculate the approximate capacitor needed for the desired shutdown time: 18 RFLTINT ≅ tRT CFLTINT × 0.3514 where tRT is the desired recovery time. Choose tRT ≥ 10 x tSH. Typical values for tSH can range from a few hundred microseconds to a few milliseconds. Shutdown Shut down the controller section of the IC by driving DCUVLO to GND using an open-collector or open-drain transistor connected to GND. The DC-DC converter section shuts down if REGOUT is below its DCUVLO level. Current-Sense Comparator The current-sense (CS) comparator and its associated logic limit the peak current through the internal MOSFET. Current is sensed at CS as a voltage across a sense resistor between the source of the MOSFET and GND. The power MOSFET switches off when the voltage at CS reaches 156mV. Select the current-sense resistor, RSENSE, according to the following equation: RSENSE = 0.156V / ILimPrimary where ILimPrimary is the maximum peak primary-side current. To reduce switching noise, connect CS to an external RC lowpass filter for additional filtering (Figure 3). Applications Information Design Example Design Example 1: PD with three-output flyback DCDC converter Figure 6 shows an isolated three-output flyback DC-DC converter. It provides output voltages of 10V at 30mA, 5.1V at 1.8A, and 2.55V at 5.4A. Design Example 2: PD with nonisolated step-down (buck) converter Figure 7 shows a buck converter with 12V, 0.75A output. Caution: this converter does not have active current limit. ______________________________________________________________________________________ ______________________________________________________________________________________ -48V D1 56.7V GATE C1 0.068µF -48VOUT R15 210kΩ C2 100pF INBIAS R3 (RDISC) 25.5kΩ C3 2.2µF R6 210kΩ R5 210kΩ C10 22µF 63V OUT GATE DRVIN REGOUT RCFF RAMP VEE RCLASS UVLO C5 1000pF R7 25.5kΩ 16 9 30 41 44 45 10 8 6 V+ R8 1MΩ RTCT 42 FLTINT 43 CSS C6 100pF 24 C7 0.01µF 22 GND 25 OPTO MAX5953A U1 C8 100pF PGND 23 20 CS BST PPWM 21 SRC R14 470Ω C13 0.22µF R10 0.18Ω INBIAS XFRMRL XFRMRH 26, 27 R9 1kΩ DRNH 33, 34 *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE R3, 25.5kΩ. R11 2kΩ C4 4700pF R4 (RCL) 255Ω R2* 0Ω R1* OPEN 4 HVIN 39 PPWM C12 0.1µF 2 3 D6 C E T1 D12 D11 GND N.C. 1, 4 5 8 LED U2 7 FOD2712 FB 6 COMP C19 0.068µF C11 0.1µF C9 0.22µF INBIAS R25 OPEN 40 28, 29 31, 32 36 -48VOUT D4 R18 22Ω R17 22Ω G2 R21 2.52kΩ R20 2.74kΩ R23 1MΩ N3 1kΩ N1 R19 G1 R24 1kΩ R22 221Ω N4 N2 C20 0.068µF A2 A1 D3 R16 1kΩ D2 T2 PA0264 C24 0.1µF A2 A2 G2 A1 G1 D5 A1 VOUT2 C15 22µF C23 220µF -48VOUT C18 2200pF VOUT2 C22 220µF C17 220µF C16 VOUT3 100pF C14 0.47µF C21 0.1µF D8 R27 10kΩ R28 10kΩ VOUT1 (10V AT 30mA) D9 VOUT3 D7 C17A 100µF C26 0.1µF D10 RTN VOUT3 (2.55V AT 5.4A) VOUT2 (5.1V AT 1.8A) MAX5953A/MAX5953B/MAX5953C/MAX5953D -48VRTN 37 DCUVLO 18 R16 316kΩ PGOOD R17 14.7kΩ PPWM R6 100Ω C25 0.1µF IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Figure 6. PD with Three-Output Flyback DC-DC Converter 19 20 -48V D1 60V -48VRTN 0.5A C1 68nF C3 100pF R3 210kΩ R1 (RDISC) 25.5kΩ C4 2.2µF C2 22µF 63V C5 4700pF R2 (RRCLASS) 255Ω OUT GATE DRVIN C6 150pF R5 1kΩ R6 100kΩ RTCT 42 FLTINT 43 REGOUT RCFF RAMP VEE RCLASS V+ R4 26.7kΩ 16 9 30 41 44 45 10 8 4 CSS C7 100pF 24 R8 316kΩ C8 0.022µF 22 PGOOD GND 25 OPTO MAX5953A U1 37 DCUVLO 18 R9 14.7kΩ PGOOD PGOOD 23 20 CS DRNH 33, 34 PGND PGND HVIN 39 26, 27 SRC R10 OPEN C9 OPEN INBIAS XFRMRL XFRMRH BST PPWM 21 40 28, 29 31, 32 36 C13 1µF R7 3.9kΩ TL431CD C10 0.022µF D4 L1 220µH C16 0.01µF R13 14.3kΩ C11 22µF R12 1.78kΩ R11 6.81kΩ GND C14 0.15µF C12 1µF OUT 12V, 0.75A C15 0.03µF R16 4.99kΩ MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Figure 7. PD with Nonisolated Step-Down (Buck) Converter ______________________________________________________________________________________ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs COMPONENT Power FETS Current-Sense Resistors Diodes Capacitors Magnetics SUPPLIERS WEBSITE International Rectifier www.irf.com Fairchild www.fairchildsemi.com Vishay-Siliconix www.vishay.com/brands/siliconix/main.html Dale-Vishay www.vishay.com/brands/dale/main.html IRC www.irctt.com/pages/index.cfm ON Semi www.onsemi.com General Semiconductor www.gensemi.com Central Semiconductor www.centralsemi.com Sanyo www.sanyo.com Taiyo Yuden www.t-yuden.com AVX www.avxcorp.com Coiltronics www.cooperet.com Coilcraft www.coilcraft.com Pulse Engineering www.pulseeng.com Layout Recommendations All connections carrying pulsed currents must be very short, as wide as possible, and have a ground plane as a return path. The inductance of these connections must be kept to a minimum due to the high di/dt of the currents in high-frequency-switching power converters. Current loops must be analyzed in any layout proposed, and the internal area kept to a minimum to reduce radiated EMI. Ground planes must be kept as intact as possible. ______________________________________________________________________________________ 21 MAX5953A/MAX5953B/MAX5953C/MAX5953D Table 3. Component Suppliers MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Block Diagrams V+ UVLO REF 2.4V REF EN V+ 21.8V CLASSIFICATION 6.8V MAX5953A MAX5953B MAX5953C MAX5953D 2.4V, 0.8 HYST RCLASS PGOOD** Q4 39V VGATE, 6V 1.2V, REF EN UVLO* PGOOD*** 5V, REF Q3 OUT Q2 38Ω 200mV Q1 0.6Ω GATE *MAX5953A/MAX5953C ONLY. **MAX5953C/MAX5953D ONLY. ***MAX5953A/MAX5953B ONLY. VEE Figure 8. Powered Device Interface Block Diagram 22 ______________________________________________________________________________________ IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs INBIAS REGOK REGOUT HVIN REG DCUVLO OVT REF (1.25V) REFOK DCUVLO DCUVLO RCFF 1.25V 5V 5V IFLT 80µA Q PPWM 7.5V D 50Ω T R FLTINT RAMP BST GND DRNH OVRLD 2.7V/1.9V R 80ns DELAY Q LEVEL SHIFT 0.4Ω QH XFRMRH CPWM S OPTO LEADINGEDGE DELAY 5V ONE SHOT 30Ω QB DRVIN 33µA CLK Q T-FF CSS SHDN R T XFRMRL OSC 0.4Ω THERMAL SHUTDOWN OVT QL SRC PGND OVT DCUVLO REFOK REGOK OVRLD 50Ω GND MAX5953A MAX5953B MAX5953C MAX5953D GND RTCT CS ILIM 10MHz 150mV PGND Figure 9. DC-DC Converter Block Diagram (Voltage-Mode PWM Controller and Two-Switch Power Stage) ______________________________________________________________________________________ 23 MAX5953A/MAX5953B/MAX5953C/MAX5953D Block Diagrams (continued) 24 -48V D1 60V -48VRTN C1 68nF R3 (RDISC) 25.5kΩ ______________________________________________________________________________________ 16 9 30 41 44 45 10 8 6 OUT GATE DRVIN REGOUT RCFF RAMP VEE RCLASS UVLO V+ RTCT 42 FLTINT 43 CSS 24 22 GND 25 OPTO MAX5953A U1 DCUVLO PGOOD 23 DRNH CS 20 PGND PGND HVIN 33, 34 *R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE R3, 25.5kΩ. RRCLASS R2* R1* 4 37 18 39 26, 27 SRC INBIAS XFRMRL XFRMRH BST PPWM 21 40 28, 29 31, 32 36 C E FB GND COMP U2 FOD2712 LED SGND OUT MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs Typical Operating Circuit IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs OPTO SRC SRC XFRMRL XFRMRL DRVIN XFRMRH XFRMRH DRNH DRNH N.C. BST TOP VIEW 36 35 34 33 32 31 30 29 28 27 26 25 DCUVLO 37 24 CSS N.C. 38 23 PGND HVIN 39 22 GND INBIAS 40 21 PPWM REGOUT 41 20 CS 19 N.C. 18 ** 17 N.C. MAX5953A MAX5953B MAX5953C MAX5953D N.C. 47 14 N.C. N.C. 48 13 N.C. 2 3 4 5 6 7 8 9 10 11 12 VEE 1 N.C. + VEE OUT GATE OUT 15 RCLASS 16 46 N.C. 45 N.C. * RAMP N.C. 44 V+ RCFF N.C. 43 N.C. 42 N.C. RTCT FLTINT THIN QFN 7mm x 7mm *UVLO FOR MAX5953A/MAX5953C N.C. FOR MAX5953B/MAX5953D ** PGOOD FOR MAX5953A/MAX5953B PGOOD FOR MAX5953C/MAX5953D Selector Guide PGOOD or PGOOD UVLO MAX5953A PGOOD Adjustable MAX5953B PGOOD Fixed MAX5953C PGOOD Adjustable MAX5953D PGOOD Fixed PART Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 25 MAX5953A/MAX5953B/MAX5953C/MAX5953D Pin Configuration Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX5953A/MAX5953B/MAX5953C/MAX5953D IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs (NE-1) X e E/2 k e D/2 CL (ND-1) X e D D2 D2/2 b L E2/2 DETAIL B e E2 CL L L1 CL k CL L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 26 ______________________________________________________________________________________ E 1 2 IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 E 2 2 Revision History Pages changed at Rev 1: 1, 27 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 © 2006 Maxim Integrated Products M. Quijano is a registered trademark of Maxim Integrated Products, Inc. MAX5953A/MAX5953B/MAX5953C/MAX5953D Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)