19-0749; Rev 0; 7/07 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA The MAX7302 serial-interfaced peripheral features 9 level-translating I/Os, and operates from a 1.62V to 3.6V power supply. The MAX7302 features a port supply VLA that allows level-translation on I/O ports to operate from a separate power supply from 1.62V to 5.5V. An address select input, AD0, allows up to four unique slave addresses for the device. The MAX7302 ports P2–P9 can be configured as inputs, push-pull outputs, and open-drain outputs. Port P1 can be configured as a general-purpose input, open-drain output, or an open-drain INT output. Ports P2–P9 can be configured as OSCIN and OSCOUT, respectively. Ports P2–P9 can also be used as configurable logic arrays (CLAs) to form user-defined logic gates, replacing external discrete gates. Outputs are capable of sinking up to 25mA, and sourcing up to 10mA when configured as push-pull outputs. The MAX7302 includes an internal oscillator for PWM, blink, and key debounce, or to cascade multiple MAX7302s. The external clock can be used to set a specific PWM and blink timing. The RST input asynchronously clears the 2-wire interface and terminates a bus lockup involving the MAX7302. All ports configured as an output feature a 33-step PWM, allowing any output to be set from fully off, 1/32 to 31/32 duty cycle, to fully on. All output ports also feature LED blink control, allowing blink periods of 1/8s, 1/4s, 1/2s, 1s, 2s, 4s, or 8s. Any port can blink during this period with a 1/16 to 15/16 duty cycle. The MAX7302 is specified over the -40°C to +125°C temperature range and is available in 16-pin QSOP and 16-pin TQFN (3mm x 3mm) packages. Features ♦ 1.62V to 5.5V I/O Level-Translation Port Supply (VLA) ♦ 1.62V to 3.6V Power Supply ♦ 9 Individually Configurable GPIO Ports P1 Open-Drain I/O P2–P9 Push-Pull or Open-Drain I/Os ♦ Individual 33-Step PWM Intensity Control ♦ Blink Controls with 15 Steps on Outputs ♦ 1kHz PWM Period Provides Flicker-Free LED Intensity Control ♦ 25mA (max) Port Output Sink Current (100mA max Ground Current) ♦ Inputs Overvoltage Protected Up to 5.5V (VLA) ♦ Transition Detection with Optional Interrupt Output ♦ Optional Input Debouncing ♦ I/O Ports Configurable as Logic Gates (CLA) ♦ External RST Input ♦ Oscillator Input and Output Enable Cascading Multiple Devices ♦ Low 0.75µA (typ) Standby Current Ordering Information PINPACKAGE PKG CODE -40°C to +125°C 16 QSOP E16-4 -40°C to +125°C 16 TQFN-EP* (3mm x 3mm) PART TEMP RANGE MAX7302AEE+ MAX7302ATE+ T1633-4 +Denotes lead-free package. *EP = Exposed paddle. Typical Operating Circuit Applications +1.8V +4.5V Cell Phones Servers VLA VDD System I/O Ports LCD/Keypad Backlights LED Status Indicators µC SDA SDA SCL SCL RST RST INT P1/INT MAX7302 ADO Pin Configurations appear at end of data sheet. GND P2 P3 P4 P5 P6 P7 P8 P9 1.8V OPEN-DRAIN OUTPUT 4.5V PUSH-PULL OUTPUT 4.5V LOGIC INPUT 3.3V LOGIC INPUT 2.5V LOGIC INPUT SMBus is a trademark of Intel Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX7302 General Description I2C-/SMBus™-compatible, MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA ABSOLUTE MAXIMUM RATINGS GND Current ....................................................................100mA Continuous Power Dissipation (TA = +70°C) 16-Pin QSOP (derate 8.3mW/°C over +70°C)..............666mW 16-Pin TQFN (derate 14.7mW/°C over +70°C) ..........1176mW Operating Temperature Range .........................-40°C to +125°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C (All voltages referenced to GND.) VDD ..........................................................................-0.3V to +4V VLA, SCL, SDA, AD0, RST, P1..................................-0.3V to +6V P2–P9 ............................................................-0.3V to VLA + 0.3V P1–P9 Sink Current ............................................................25mA P2–P9 Source Current ........................................................10mA SDA Sink Current ...............................................................10mA VDD Current .......................................................................10mA VLA Current ........................................................................35mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 1.62V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage VDD 1.62 3.60 V Port Logic Supply Voltage VLA 1.62 5.50 V Power-On-Reset Voltage Power-On-Reset Hysteresis VPOR VDD rising VPORHYST 1.0 1.3 1.6 V 10 158 300 mV 0.75 2 ISTB Internal oscillator disabled; SCL, SDA, digital inputs at VDD or GND; P1–P9 (as inputs) at VLA or GND IOSC Internal oscillator enabled; SCL, SDA, digital inputs at VDD or GND; P1–P9 (as inputs) at VLA or GND 17 25 Supply Current (Interface Running) ISUP fSCL = 400kHz; other digital inputs at VDD or GND 31 40 µA Port Supply Current (VLA) IVLA Port inputs at VLA or GND 0.06 5 µA Input High Voltage SDA, SCL, AD0, RST VIH µA Standby Current (Interface Idle) Input Low Voltage SDA, SCL, AD0, RST 0.7 x VDD VIL 0.3 x VDD Input High Voltage P1–P9 VIHP Input is VDD referred Input Low Voltage P1–P9 VILP Input is VDD referred Input High Voltage P1–P9 VIHPA Input is VLA referred Input Low Voltage P1–P9 VILPA Input is VLA referred Input Leakage Current SDA, SCL, AD0, RST IIH, IIL VDD or GND IIHP, IILP VLA or GND Input Leakage Current P1–P9 0.7 x VDD 0.7 x VLA Output Low Voltage SDA 2 V V -1 +1 µA -2 +2 µA VOH VOLSDA pF VDD = 1.62V, ISINK = 3mA 0.05 0.11 VDD = 2.5V, ISINK = 16mA 0.19 0.31 VDD = 3.3V, ISINK = 20mA 0.19 0.31 VLA = 1.62V, ISOURCE = 0.5mA Output High Voltage P2–P9 V 0.3 x VLA 8 VOL V V 0.3 x VDD Input Capacitance SDA, SCL, AD0, P1–P9, RST Output Low Voltage P1–P9 V 1.55 1.58 VLA ≥ 2.5V, ISOURCE = 5mA VLA - 0.4 2.32 VLA ≥ 3.3V, ISOURCE = 10mA VLA - 0.6 3.1 ISINK = 6mA _______________________________________________________________________________________ V V 0.3 V SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA (VDD = 1.62V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V, TA = +25°C.) (Note 1) (Figures 10, 15, 16 and 17) PARAMETER SYMBOL CONDITIONS Oscillator Frequency fCLK Port Output Data Valid High Time tPPVH fCLK = internal oscillator fCLK = OSCIN external input CL ≤ 100pF Port Output Data Valid Low Time (Note 6) tPPVL CL ≤ 100pF (Note 2) Port Input Setup Time Port Input Hold Time CLA Rise Time P5, P9 as Push-Pull Outputs tPSU tPH CL = 100pF CL = 100pF CLA Fall Time P5, P9 as Push-Pull Outputs CLA Propagation Delay P2, P3, or P4 to P5; P6, P7, or P8 to P9 INT Input Data Valid Time INT Reset Delay Time from Acknowledge RST Rising to START Condition Setup Time RST Pulse Width tRFCLA CL = 100pF, VLA ≥ 2.7V tPDCLA CL = 100pF, VLA ≥ 2.7V tIV tIR MIN TYP UNITS 1 4 kHz MHz µs 1 / fCLK 0 4 s µs µs 17 ns 14 28 CL = 100pF CL = 100pF tRST tW MAX 32 50 ns 4 4 µs µs ns ns 900 500 SERIAL INTERFACE TIMING CHARACTERISTICS (VDD = 1.62V to 3.6V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V, TA = +25°C.) (Note 1) (Figure 10) PARAMETER Serial-Clock Frequency Bus Timeout Bus Free Time Between a STOP and a START Condition SYMBOL CONDITIONS MIN TYP fSCL MAX UNITS 400 kHz tTIMEOUT tBUF 1.3 ms µs Hold Time, (Repeated) START Condition tHD,STA 0.6 µs Repeated START Condition Setup Time tSU,STA 0.6 µs STOP Condition Setup Time Data Hold Time tSU,STO tHD,DAT 0.6 Data Setup Time tSU,DAT 100 ns SCL Clock Low Period tLOW 1.3 µs SCL Clock High Period Rise Time of Both SDA and SCL Signals, Receiving tHIGH tR 0.7 (Notes 2, 4) 20 + 0.1Cb 300 µs ns tF Fall Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Pulse Width of Spike Suppressed Capacitive Load for Each Bus Line 31 (Note 3) 0.9 µs µs (Notes 2, 4) 20 + 0.1Cb 300 ns tF.TX (Note 4) 20 + 0.1Cb 250 ns tSP Cb (Note 5) (Note 2) 50 400 ns pF Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design. Note 2: Guaranteed by design. Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 4: Cb = total capacitance of one bus line in pF. tR and tF are measured between 0.3 x VDD and 0.7 x VDD. Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. Note 6: A startup time is required for the internal oscilator to start if it is not running already. _______________________________________________________________________________________ 3 MAX7302 PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS Typical Operating Characteristics (VDD = 3.3V, VLA = 3.3V and TA = +25°C, unless otherwise noted.) VDD = 3.6V 1.0 0.8 0.6 0.4 VDD = 1.62V VDD = 3.3V 12 0 -25 0 25 50 75 100 125 -50 -25 0 TEMPERATURE (°C) 25 70 60 50 VDD = 3.3V 40 30 VDD = 1.62V 20 INTERFACE IDLE INTERNAL OSCILLATOR RUNNING 0.2 -50 MAX7302 toc02 8 4 0 VDD = 3.3V VDD = 1.62V VDD = 3.6V 80 10 0 50 75 100 -50 125 -25 0 TEMPERATURE (°C) VOL vs. TEMPERATURE 0.4 MAX7302 toc04 LOAD CURRENT = 20mA 0.24 VDD = 1.62V VDD = 3.3V 0.3 100 3.0 VOH (V) VOL (V) VDD = 3.3V 75 3.6 2.4 0.18 50 125 VOH vs. TEMPERATURE VOL vs. ISINK 0.30 25 TEMPERATURE (°C) MAX7302 toc06 1.2 16 INTERFACE RUNNING 90 SUPPLY CURRENT (µA) 1.4 100 MAX7302 toc05 SUPPLY CURRENT (µA) 1.6 VDD = 3.6V SUPPLY CURRENT (µA) INTERFACE IDLE INTERNAL OSCILLATOR DISABLED 1.8 STANDBY CURRENT vs. TEMPERATURE 20 MAX7302 toc01 2.0 STANDBY CURRENT vs. TEMPERATURE MAX7302 toc03 STANDBY CURRENT vs. TEMPERATURE VOL (V) 0.2 VDD = 3.6V VDD = 3.3V 1.8 0.12 1.2 0.1 0.06 0.6 0 -25 0 25 50 75 100 125 LOAD CURRENT = 10mA 0 0 -50 0 5 TEMPERATURE (°C) 10 15 20 25 30 -50 35 -25 0 50 INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE 3.5 45 MAX7302 toc08 VLA = 3.6V MAX7302 toc07 4.0 25 FREQUENCY (kHz) 3.0 VLA = 3.3V 2.5 2.0 VLA = 1.62V 1.5 40 VDD = 3.6V VDD = 3.3V 35 VDD = 1.62V 1.0 0.5 0 0 2 4 6 ISOURCE (mA) 4 8 10 12 75 TEMPERATURE (°C) ISINK (mA) VOH vs. ISOURCE VOH (V) MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA 30 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 125 100 125 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA CLA PROPAGATION DELAY OUTPUT RISING STAGGERED PWM OUTPUTS MAX7302 toc09 MAX7302 toc10 CL = 100pF PORT2 5V/div PORT2 2V/div PORT3 5V/div PORT3 2V/div PORT4 5V/div PORT5 2V/div PORT5 5V/div 400µs/div 40ns/div CLA PROPAGATION DELAY OUTPUT FALLING MAX7302 toc11 CL = 100pF PORT2 2V/div PORT3 2V/div PORT5 2V/div 40ns/div _______________________________________________________________________________________ 5 MAX7302 Typical Operating Characteristics (continued) (VDD = 3.3V, VLA = 3.3V and TA = +25°C, unless otherwise noted.) SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 Pin Description PIN 6 NAME FUNCTION QSOP TQFN 1 15 VLA Port Supply for P1–P9. Connect VLA to a power supply between 1.62V and 5.5V. Bypass VLA to GND with a 0.047µF ceramic capacitor. 2 16 AD0 Address Input. Sets the device slave address. Connect to GND, VDD, SCL, or SDA to provide four address combinations. 3 1 RST Reset Input. RST is an active-low input, referenced to VDD, that clears the 2-wire interface and can be configured to put the device in the power-up reset and/or to reset the PWM and blink timing. 4 2 P1/INT 5 3 P2/OSCIN 6 4 P3/OSCOUT 7, 8, 9, 11, 12, 13 5, 6, 7, 9, 10, 11 P4–P9 10 8 GND Ground 14 12 SCL Serial-Clock Input 15 13 SDA Serial-Data I/O 16 14 VDD Positive Supply Voltage. Bypass VDD to GND with a 0.047µF ceramic capacitor. — EP EP Input/Output Port. P1/INT is a general-purpose I/O that can be configured as a transition detection interrupt output. Input/Output Port. P2/OSCIN is a general-purpose I/O that can be configured as the oscillator input for PWM and blink features. Input/Output Port. P3/OSCOUT is a general-purpose I/O that can be configured as the PWM/blink/timing oscillator output for PWM and blink features. Input/Output Ports. P4–P9 are general-purpose I/Os. Exposed Paddle on Package Underside. Connect to GND. _______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA VLA VDD MAX7302 AD0 P1–P9 OUTPUT LOGIC I/O SCL I 2C SDA RST I/O CONTROL INPUT LOGIC REGISTER BANK CLA GND Detailed Description The MAX7302 9-port, general-purpose port expander operates from a 1.62V to 3.6V power supply. Port P1 can be configured as an input and an open-drain output. Port P1 can also be configured to function as an INT output. Ports P2–P9 can be configured as inputs, push-pull outputs, and open-drain outputs. Ports P2–P9 can be used as simple configurable logic arrays (CLAs) to form user-defined logic gates. Each port configured as an open-drain or push-pull output can sink up to 25mA. Push-pull outputs also have a 5mA source drive capability. The MAX7302 is rated to sink a total of 100mA into any combination of its output ports. Output ports have PWM and blink capabilities, as well as logic drive. Initial Power-Up On power-up, the MAX7302 default configuration has all 9 ports, P1–P9, configured as input ports with logic levels referenced to VLA. The transition detection interrupt status flag resets and stays high (see Tables 1 and 2). Device Configuration Registers The device configuration registers set up the interrupt function, serial-interface bus timeout, and PWM/blink oscillator options, global blink period, and reset options (see Tables 3 and 4). _______________________________________________________________________________________ 7 MAX7302 Block Diagram MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Table 1. Register Address Map ADDRESS AUTOINCREMENT ADDRESS Port P1 or INT Output REGISTER 0x01 0x02 0x80 Port P2 or OSCIN Input 0x02 0x03 0x80 Port P3 or OSCOUT Output 0x03 0x04 0x80 Port P4 0x04 0x05 0x80 Port P5 0x05 0x06 0x80 Port P6 0x06 0x07 0x80 Port P7 0x07 0x08 0x80 Port P8 0x08 0x09 0x80 Port P9 0x09 0x0A or 0x4A 0x80 Configuration 26 0x26 0x27 0xEC Configuration 27 0x27 0x28 0x8F Ports P2–P5 Configurable Logic CLA0 0x28 0x29 0x00 Ports P6–P9 Configurable Logic CLA1 0x29 0x2A 0x00 Write Ports P2–P5 Same Data; Read P2 0x3C 0x3D 0x80 Write Ports P6–P9 Same Data; Read P6 0x3D 0x3E 0x80 0x3C–0x3F 0x3F–0x40 0x00 CLA0 and CLA1 Configurable Logic Enable 0x70 0x71 0x00 CLA0 and CLA1 Configurable Logic Lock 0x71 0x72 0x00 Configuration 67 Lock, Ports P1–P5 Lock 0x72 0x73 0x00 Ports P6–P9 Lock 0x73 0x74 0xF0 FACTORY RESERVED (Do not write to these registers) 0x00 0x01 0x80 FACTORY RESERVED (Do not write to these registers) POR STATE Table 2. Power-Up Register Status REGISTER POWER-UP CONDITION REGISTER DATA ADDRESS CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 Ports P1–P9 Ports P_ are VLA-referred input ports with interrupt and debounce disabled 0x01–0x09 1 0 0 0 0 0 0 0 Configuration 26 RST does not reset registers or counters; blink period is 1Hz; transition flag clear; interrupt status flag clear 0x26 1 1 1 0 1 1 0 0 Configuration 27 Ports P1–P9 are GPIO ports; bus timeout is disabled 0x27 1 0 0 0 1 1 1 1 Ports CLA0 to CLA1 Default gate structure 0x28–0x29 0 0 0 0 0 0 0 0 CLA0 to CLA1 CLA not enable 0x70 0 0 0 0 0 0 0 0 Configuration 27 Lock, Ports P1–P5 Lock Configuration 27 is not locked; ports P1–P5 are not locked 0x72 0 0 0 0 0 0 0 0 Ports P6–P9 Lock Ports P6–P9 are not locked 0x73 1 1 1 1 0 0 0 0 8 _______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 Table 3. Configuration Register (0x26) REGISTER BIT DESCRIPTION VALUE D7 Interrupt status flag (read only) 0 An interrupt has occurred on at least one interrupt enabled input port. 1* No interrupt has occurred on an interrupt enabled input port. D6 Transition flag (read only) 0 A transition has occurred on an input port. 1* No transition has occurred on an input port. D5 D4, D3, D2 Reserved Blink prescalor bits D1 RST timer D0 RST POR FUNCTION — Reserved 0/1 Blink timer bits, see Table 10. 0* RST does not reset counters PWM/blink 1 RST resets PWM/blink counters 0* RST does not reset registers to power-on-reset state. 1 RST resets registers to power-on-reset state. *Default state. Table 4. Configuration Register (0x27) REGISTER BIT DESCRIPTION D7 Bus timeout D6, D5, D4 Reserved D3 P3/OSCOUT D2 P2/OSCIN D1 P1/INT output D0 Input transition VALUE FUNCTION 0 Enables the bus timeout feature. 1 Disables the bus timeout feature. 0 Reserved 1 Reserved 0 Sets P3 to output the oscillator. 1* Sets P3 as a GPIO controlled by register 0x03. 0 Sets P2 as the oscillator input. 1* Sets P2 as a GPIO controlled by register 0x02. 0 Sets P1 as the interrupt output. 1 Sets P1 as a GPIO controlled by register 0x01. 0 Set to 0 on power-up to detect transition on inputs. *Default state. _______________________________________________________________________________________ 9 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Slave Address The MAX7302 is set to one of four I2C slave addresses, using the address input AD0 (see Table 5) and is accessed over an I2C or SMBus serial interface up to 400kHz. The MAX7302 slave address is determined on each I2C transmission, regardless of whether or not the transmission is actually addressing the device. The MAX7302 distinguishes whether address input AD0 is connected to SDA, SCL, VDD, or GND during the transmission. Therefore, the MAX7302 slave address can be configured dynamically in an application without toggling the device supply. I/O Port Registers The port I/O registers set the I/O ports, one register per port (see Tables 6 and 7). Ports can be independently configured as inputs or outputs (D7), push-pull or open drain (D6). Port P1 can only be configured as an input or an open-drain output. The push-pull bit (D6) setting for the port I/O register P1 is ignored. I/O Input Port Configure a port as an input by writing a logic-high to the MSB (bit D7) of the port I/O register (see Table 6). See Figure 1 for input port structure. To obtain the logic Table 5. Slave Address Selection DEVICE ADDRESS AD0 CONNECTION A6 A5 A4 A3 A2 A1 GND 1 0 0 1 1 0 A0 R W 0 0 1 1 0 1 VDD 1 0 0 1 1 0 SCL 1 0 0 1 1 1 0 SDA 1 0 0 1 1 1 1 level of the port input, read the port I/O register bit, D0. This readback value is the instantaneous logic level at the time of the read request if debounce is disabled for the port (port I/O register bit D2 = 0), or the debounced result if debounce is enabled for the port (port I/O register bit D2 = 1). I/O Output Port Configure a port as an output by writing a logic-low to the MSB (bit D7) of the port I/O register. See Figures 2 and 3 for output port structure. The device reads back the logic level, PWM, or the blink setting of the port (see Table 7). The MAX7302 monitors the logic level of ports configured as CLA outputs (see the Configurable Logic Array (CLA) section). Port Supplies and Level Translation The port supply, VLA, provides the logic supplies to all push-pull I/O ports. Ports P2–P9 can be configured as push-pull I/O ports (see Figure 3). VLA powers the logichigh port output voltage sourcing the logic-high port load current. VLA provides level translation capability for the outputs and operates over a 1.62V to 5.5V voltage independent of the MAX7302 power-supply voltage, VDD. Each port set as an input can be configured to switch midrail of either the V DD or the V LA port supplies. Whenever the port supply reference is changed from VDD to VLA, or vice versa, read the port register to clear any transition flag on the port. 0 1 0 1 Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01/0x41 to 0x09/049) 10 REGISTER BIT DESCRIPTION VALUE FUNCTION D7 Port I/O set bit 1 Sets the I/O port as an input. D6 Port supply reference 0 Refers the input to the VLA supply voltage. 1 Refers the input to the VDD supply voltage. D5 Transition interrupt enable 0 Disables the transition interrupt. 1 Enables the transition interrupt. D4, D3 Reserved bits 0 Do not write to these registers. D2 Debounce D1 Port transition state (read only) D0 Port status (read only) 0 Disables debouncing of the input port. 1 Enables debouncing of the input port. 0 No transition has occurred since the last port read. 1 A transition has occurred since the last port read. 0 Port input is logic-low. 1 Port input is logic-high. ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 VDD VLA PORT_ [2] (DEBOUNCE) PORT_ [6] (THRESHOLD SELECT) PORT_ [0] (PORTIN) 0 I/O DEBOUNCE LOGIC 1 TRANSITION DETECTION TRANSITION DETECTION INTERRUPT LOGIC PORT_ [4:3] PORT_ [5] INTERRUPT ENABLE INT INT2 INT INT9 Figure 1. Input Port Structure Table 7. Port I/O Registers (I/O Port Set as an Output, Registers 0x01 to 0x09) REGISTER BIT DESCRIPTION VALUE FUNCTION D7 Port I/O set bit 0 Sets the I/O port as an output. 0 Sets the output type to open drain. D6 Output port set to push-pull or open drain 1 Sets the output type to push-pull. 0 Sets the output to PWM mode. D5 PWM/blink enable D4 Duty-cycle bit 4 0/1 MSB of the 5-bit duty-cycle setting. See Tables 9 and 11. D3 Duty-cycle bit 3 0/1 Bit 3 of the 5-bit duty-cycle setting. See Tables 9 and 11. D2 Duty-cycle bit 2 0/1 Bit 2 of the 5-bit duty-cycle setting. See Tables 9 and 11. D1 Duty-cycle bit 1 0/1 Bit 1 of the 5-bit duty-cycle setting. See Tables 9 and 11. D0 Duty-cycle bit 0 0/1 LSB of the 5-bit duty-cycle setting. See Tables 9 and 11. 1 Sets the output to blink mode. ______________________________________________________________________________________ 11 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA PORT_ [5] 5-BIT PWM 0 PORT_ [4:0] CLOCK 3-BIT PRESCALER 4-BIT BLINK CONFIG26 [4:2] PORT_ [3:0] I/O 1 Figure 2. Output Port Structure V+ VLA V+ SELECT VLA SELECT INPUT PORT P1 OUTPUT PORT P2–P9 INPUT OUTPUT P1 P2–P9 Figure 3. Port I/O Structure Ports P2–P9 are overvoltage protected to VLA. This is true even for a port used as an input with a VDD port logicinput threshold. Port P1 is overvoltage protected to 5.5V, independent of VDD and VLA (see Figure 3). To mix logic outputs with more than one voltage swing on a group of ports using the same port supply, set the port supply voltage (VLA) to be the highest output voltage. Use push-pull outputs and port P1 for the highest voltage ports, and use open-drain outputs with external pullup resistors for the lower voltage ports. When P2–P9 are acting as inputs referenced to VDD, make sure the VLA voltage is greater than VDD - 0.3V. Port Lock Registers Use the port lock registers to lock any combination of port I/O register functionality (see Table 8). The port lock registers are unlocked on power-up or by configuring the RSTPOR bit to reset to POR value. The bits in the port lock register can only be written to once. After setting a bit to logic-high, the bit can only be cleared by powering off the device. 12 When a bit position in the port lock register is set, the corresponding port I/O registers cannot change. When a port I/O register is locked as an output, none of its output register settings can change. When a port I/O register is locked as an input, only bits D0 and D1 can change, and the locked input behaviour options, such as debounce and transition detection, operate as normal. Input Debounce The MAX7302 samples the input ports every 31ms if input debouncing is enabled for an input port (D2 = 1 of the port I/O register). The MAX7302 compares each new sample with the previous sample. If the new sample and the previous sample have the same value, the corresponding internal register updates. When the port input is read through the serial interface, the MAX7302 does not return the instantaneous value of the logic level from the port because debounce is active. Instead, the MAX7302 returns the stored debounced input signal. ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 Table 8. Port Lock Registers ADDRESS CODE REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 0x72 Port P5 Port P4 Port P3 Port P2 Port P1 — Configuration register 0x27 0 0x73 — — — — Port P9 Port P8 Port P7 Port P6 When debouncing is enabled for a port input, transition detection applies to the stored debounced input signal value, rather than to the instantaneous value at the input. This process allows for useful transition detection of noisy signals, such as keyswitch inputs, without causing spurious interrupts. Port Input Transition Detection and Interrupt Any transition on ports configured as inputs automatically set the D1 bit of that port’s I/O registers high. Any input can be selected to assert an interrupt output indicating a transition has occurred at the input port(s). The MAX7302 samples the port input (internally latched into a snapshot register) during a read access to its port P_ I/O register. The MAX7302 continuously compares the snapshot with the port’s input condition. If the device detects a change for any port input, an internal transition flag sets for that port. Read register 0x26 to clear the interrupt, then read all the port I/O registers (0x01 to 0x09) by initiating a burst read to clear the MAX7302’s internal transition flag. Note that when debouncing is enabled for a port input, transition detection applies to the stored debounced input signal value, rather than to the instantaneous value at the input. Transition bits D4 and D3 must be set to 0 to detect the next rising or falling edge on the input port P_. The MAX7302 allows the user to select the input port(s) that cause an interrupt on the INT output. Set INT for each port by using the INTenable bit (bit D5) in each port P_ register. The appropriate port’s transition flag always sets when an input changes, regardless of the port’s INTenable bit settings. The INTenable bits allow processor interrupt only on critical events, while the inputs and the transition flags can be polled periodically to detect less critical events. When debounce is disabled, signal transtions between the 9th and 11th falling edges of clock will not be registered since the transition is detected and cleared at the same read cycle. Ports configured as outputs do not feature transition detection, and therefore, cannot cause an interrupt. The exception to this rule is the CLA outputs. The INT output never reasserts during a read sequence because this process could cause a recursive reentry into the interrupt service routine. Instead, if a data change occurs during the read that would normally set the INT output, the interrupt assertion is delayed until the STOP condition. If the changed input data is read before the STOP condition, a new interrupt is not required and not asserted. The INT bit and INT output (if selected) have the same value at all times. Transition Flag The Transition bit in device configuration register 0x26 is a NOR of all the port I/O registers’ individual Transition bits. A port I/O register’s Transition bit sets when that port is set as an input, and the input changes from the port’s I/O registers last read through the serial interface. A port’s individual Transition bit clears by reading that port’s I/O register. The Transition flag of configuration register 0x26 is only cleared after reading all port I/O registers on which a transition has occurred. RST Input The active-low RST input operates as a hardware reset which voids any on-going I2C transaction involving the MAX7302. This feature allows the MAX7302 supply current to be minimized in power critical applications by effectively disconnecting the MAX7302 from the bus. RST also operates as a chip enable, allowing multiple devices to use the same I2C slave address if only one MAX7302 has its RST input high at any time. RST can be configured to restore all port registers to the powerup settings by setting bit D0 of device configuration register 0x26 (Table 1). RST can also be configured to reset the internal timing counters used for PWM and blink by setting bit D1 of device configuration register 0x26. When RST is low, the MAX7302 is forced into the I2C STOP condition. The reset action does not clear the interrupt output INT. The RST input is referenced to VDD and is overvoltage tolerant up to the supply voltage, VLA. ______________________________________________________________________________________ 13 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA INT Output Port P1 can be configured as a latching interrupt output, INT, that flags any transients on any combination of selected ports configured as inputs. Configurable logic gate outputs can also be monitored as readback inputs with the same options as normal I/O port inputs. Any transitions occurring at the selected inputs assert INT low to alert the host processor of data changes at the selected inputs. Reset INT by reading any ports I/O registers (0x01 to 0x09). Standby Mode Upon power-up, the MAX7302 enters standby mode when the serial interface is idle. If any of the PWM intensity control, blink, or debounce features are used, the operating current rises because the internal PWM oscillator is running and toggling counters. When using OSCIN to override the internal oscillator, the operating current varies according to the frequency at OSCIN. When the serial interface is active, the operating current also increases because the MAX7302, like all I2C slaves, has to monitor every transmission. The bus timeout and debounce circuits use the internal oscillator even if OSCIN is selected. Internal Oscillator and OSCIN/OSCOUT External Clock Options The MAX7302 contains an internal 32kHz oscillator. The MAX7302 always uses the internal oscillator for bus timeout and for debounce timing (when enabled). It is used by default to generate PWM and blink timing. The internal oscillator only runs when the clock output OSCOUT is needed to keep the operating current as low as possible. The MAX7302 can use an external clock source instead of the internal oscillator for the PWM and blink timing. The external clock can range from DC to 1MHz, and it MAX7302 P3/OSCOUT Ensure that the blink phase of all the devices remains synchronized by programming the OSCIN and OSCOUT functionality before programming any feature that causes a MAX7302’s internal oscillator to operate (blink, PWM, bus timeout, or key debounce). Configure the RST input to reset the internal timing counters used for PWM and blink by setting bit D1 of device configuration register 0x26 (see Table 3). PWM and Blink Timing The MAX7302 divides the 32kHz nominal internal oscillator OSC or external clock source OSCIN frequency by 32 to provide a nominal 1kHz PWM frequency. Use the reset MAX7302 MAX7302 P2/OSCIN P2/OSCIN MAX7302 P3/OSCOUT connects to the P2/OSCIN port. The P3/OSCOUT port provides a buffered and level-shifted output of the internal oscillator or external clock to drive other devices. Select the P2/OSCIN and P3/OSCOUT port options using the device configuration register 0x67 bits D2 and D3 (see Table 4). The P2/OSCIN port is overvoltage protected to supply voltage VLA, so the external clock can exceed VDD if V LA is greater than V DD . The port P2 register (see Tables 2 and 6) sets the P2/OSCIN logic threshold (30%/70%) to either the VDD supply or the VLA. Use OSCOUT or an external clock source to cascade up to four MAX7302s per master for applications requiring additional ports. To synchronize the blink action across multiple MAX7302s (see Figures 4 and 5), use OSCOUT from one MAX7302 to drive OSCIN of the other MAX7302s. This process ensures the same blink frequency of all the devices, but also make sure to synchronize the blink phase. The blink timing of multiple MAX7302s is synchronous at the instant of power-up because the blink and PWM counters clear by each MAX7302’s internal reset circuit, and by default the MAX7302s’ internal oscillators are off upon power-up. MAX7302 P2/OSCIN P3/OSCOUT MAX7302 P2/OSCIN Figure 4. Synchronizing Multiple MAX7302s (Internal Oscillator) 14 ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA 0 TO 1MHz EXTERNAL OSCILLATOR 0 TO 1MHz MAX7302 P2/OSCIN P2/OSCIN MAX7302 P2/OSCIN P2/OSCIN P3/OSCOUT MAX7302 EXTERNAL OSCILLATOR MAX7302 MAX7302 P2/OSCIN MAX7302 P3/OSCOUT MAX7302 P2/OSCIN Figure 5. Synchronizing Multiple MAX7302s (External Clock) Table 9. PWM Settings on Output Port PWM SETTINGS REGISTER DATA D7 D6 D5 D4 D3 D2 D1 Port P_ is a static logic-level low output port 0 X 0 0 0 0 0 0 Port P_ is a PWM output port; PWM duty cycle is 1/32 0 X 0 0 0 0 0 1 Port P_ is a PWM output port; PWM duty cycle is 2/32 0 X 0 0 0 0 1 0 Port P_ is a PWM output port; PWM duty cycle is 3/32 0 X 0 0 0 0 1 1 Port P_ is a PWM output port; PWM duty cycle is 4/32 0 X 0 0 0 1 0 0 Port P_ is a PWM output port; PWM duty cycle is 30/32 0 X 0 1 1 1 1 0 Port P_ is a PWM output port; PWM duty cycle is 31/32 0 X 0 1 1 1 1 1 Port P_ is a static logic-level high output port 0 1 1 1 X X X X … D0 … function to synchronize multiple MAX7302s that are operating from the same OSCIN, or to synchronize a single MAX7302’s blink timing to an external event. Configure the RST input to reset the internal timing counters used by PWM and blink by setting bit D1 of the device configuration register 0x26 (see Table 3). The MAX7302 uses the internal oscillator by default. Configure port P2 using device configuration register 0x27 bit D2 (see Table 4) as an external clock source input, OSCIN, if the application requires a particular or more accurate timing for the PWM or blink functions. OSCIN only applies to PWM and blink; the MAX7302 always uses the internal oscillator for debouncing and bus timeout. OSCIN can range up to 1MHz. Use device configuration register 0x27 bit D3 (see Table 4) to configure port P3 as OSCOUT to output a MAX7302’s clock. The MAX7302 buffers the clock output of either the internal oscillator OSC or the external clock source OSCIN, according to port D2’s setup. Synchronize multiple MAX7302s without using an external clock source input by configuring one MAX7302 to generate OSCOUT from its internal clock, and use this signal to drive the remaining MAX7302s’ OSCIN. A PWM period contains 32 cycles of the nominal 1kHz PWM clock (see Figure 6). Set ports individually to a PWM duty cycle between 0/32 and 31/32. For static logic-level low output, set the ports to 0/32 PWM, and for static logic-level high output, set the port register to 0111XXXX (see Table 9). The MAX7302 staggers the PWM timing of the 9-port outputs, in single or dual ports, by 1/8 of the PWM period. These phase shifts distribute the port-output switching points across the PWM period (see Figure 7). This staggering reduces the di/dt output-switching transient on the supply and also reduces the peak/mean current requirement. All ports feature LED blink control. A global blink period of 1/8s, 1/4s, 1/2s, 1s, 2s, 4s, or 8s applies to all ports (see Table 10). Any port can blink during this period with a 1/16 to 15/16 duty cycle, adjustable in 1/16 increments (see Table 11). For PWM fan control, the MAX7302 can set the blink frequency to 32Hz. ______________________________________________________________________________________ 15 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA PORT REGISTER VALUE 0b0X000000 0b0X000001 0b0X000010 977µs NOMINAL PWM PERIOD (1024Hz PERIOD) 0b0X011101 OUTPUT LOW 29/32 DUTY PWM 0b0111XXXX LOW HIGH-Z OUTPUT LOW 2/32 DUTY PWM OUTPUT LOW 3/32 DUTY PWM 0b0X011111 LOW HIGH-Z OUTPUT LOW 1/32 DUTY PWM 0b0X000011 0b0X011110 HIGH-Z OUTPUT STATIC LOW (STATIC LOGIC-LOW OUTPUT OR LED DRIVE ON) LOW HIGH-Z LOW HIGH-Z LOW HIGH-Z OUTPUT LOW 30/32 DUTY PWM LOW HIGH-Z OUTPUT LOW 31/32 DUTY PWM LOW HIGH-Z OUTPUT STATIC HIGH (STATIC LOGIC-HIGH OUTPUT OR LED DRIVE OFF) LOW Figure 6. Static and PWM Port Output Waveforms 977µs NOMINAL PWM PERIOD 0 1 2 NEXT PWM PERIOD NEXT PWM PERIOD 3 4 5 6 7 8 OUTPUT P8 OUTPUT P8 OUTPUT P8 OUTPUTS P1, P9 OUTPUTS P1, P9 OUTPUTS P1, P9 OUTPUT P2 OUTPUT P2 OUTPUT P2 OUTPUT P3 OUTPUTP3 OUTPUT P3 OUTPUT P4 OUTPUT P4 OUTPUT P5 OUTPUT P5 OUTPUT P6 OUTPUT P6 OUTPUT P7 OUTPUT P7 Figure 7. Staggered PWM Phasing Between Port Outputs 16 ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA BLINK OR PWM SETTING Blink period is 8s (0.125Hz) Blink period is 4s (0.25Hz) Blink period is 2s (0.5Hz) Blink period is 1s (1Hz) Blink period is a 1/2s (2Hz) Blink period is a 1/4s (4Hz) Blink period is an 1/8s (8Hz) Blink period is a 1/32s (32Hz) PWM DEVICE CONFIGURATION REGISTER 0x26 BIT D4 BLINK2 0 0 0 0 1 1 1 1 X BIT D3 BLINK1 0 0 1 1 0 0 1 1 X BIT D2 BLINK0 0 1 0 1 0 1 0 1 X BLINK OR PWM FREQUENCY (32kHz INTERNAL OSCILLATOR) (Hz) BLINK OR PWM FREQUENCY (0 TO 1MHz EXTERNAL OSCILLATOR) 0.125 0.25 0.5 1 2 4 8 32 1024 OSCIN / 262,144 OSCIN / 131,072 OSCIN / 65,536 OSCIN / 32,768 OSCIN / 16,384 OSCIN / 8192 OSCIN / 4096 OSCIN / 1024 OSCIN / 32 Table 11. Blink Settings on Output Ports PWM SETTINGS REGISTER DATA D7 D6 D5 D4 D3 D2 D1 D0 Port P_ is a static logic-level low output port 0 X 1 0 0 0 0 0 Port P_ is a PWM output port; PWM duty cycle is 1/16 0 X 1 0 0 0 0 1 Port P_ is a PWM output port; PWM duty cycle is 2/16 0 X 1 0 0 0 1 0 Port P_ is a PWM output port; PWM duty cycle is 3/16 0 X 1 0 0 1 0 0 1 1 1 0 … … Port P_ is a PWM output port; PWM duty cycle is 14/16 0 X 1 0 Port P_ is a PWM output port; PWM duty cycle is 15/16 0 X 1 0 1 1 1 1 Port P_ is a static logic-level high output port (32/32) 0 1 1 1 X X X X Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28) FUNCTION REGISTER BIT D5 D4 D3 D2 XOR noninverted 0 XOR P3 inverted 1 0 XOR P2 inverted 1 X XOR both ports inverted 0 D1 D0 0 X 0 1 1 1 3 input AND/OR all noninverted 0 0 0 3 input AND/OR P2 inverted 0 0 1 3 input AND/OR P3 inverted 0 1 0 3 input AND/OR P4 inverted 0 1 3 input AND/OR P2 and P3 inverted 1 1 1 0 1 1 0 3 input AND/OR P2 and P4 inverted 1 0 1 3 input AND/OR P3 and P4 inverted 1 1 0 3 input AND/OR all inverted 1 1 1 ______________________________________________________________________________________ 17 MAX7302 Table 10. Blink and PWM Frequencies MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Table 12. CLA0 (P2–P5) Configuration Register Setting (0x28) (continued) REGISTER BIT FUNCTION D5 D4 D3 2 input AND/OR P2 and P3 noninverted D2 D1 0 2 input AND/OR P2 and P3 inverted 0 2 input AND/OR P2 inverted and P3 X 1 2 input AND/OR P2 and P3 both inverted 1 0 D0 0 1 1 0 1 1 2 input AND/OR P2 and P4 noninverted 0 0 2 input AND/OR P2 and P4 inverted 1 0 1 2 input AND/OR P2 inverted and P4 0 2 input AND/OR P2 and P4 both inverted 1 2 input AND/OR P3 and P4 noninverted 0 2 input AND/OR P3 and P4 inverted 1 2 input AND/OR P3 inverted and P4 2 input AND/OR P3 and P4 both inverted 0 1 0 X 1 1 1 0 1 1 1 0 0 X D1 D0 1 Table 13. Output P5 Configuration BIT LOGIC LEVEL D7 D6 FUNCTION 0 Output not cascaded to CLA1 1 Output cascaded to CLA1 0 Output noninverted 1 Output inverted Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29) FUNCTION REGISTER BIT D5 D4 D3 D2 XOR noninverted 0 XOR P7 inverted 1 XOR P6 inverted 0 1 X XOR both ports inverted 0 0 X 0 1 1 1 3 input AND/OR all noninverted 0 0 0 3 input AND/OR P6 inverted 0 0 1 3 input AND/OR P7 inverted 0 1 0 3 input AND/OR P8 inverted 0 1 3 input AND/OR P6 and P7 inverted 1 1 1 0 1 1 0 3 input AND/OR P6 and P8 inverted 1 0 1 3 input AND/OR P7 and P8 inverted 1 1 0 3 input AND/OR all inverted 1 2 input AND/OR P6 and P7 noninverted 2 input AND/OR P6 and P7 inverted 2 input AND/OR P6 inverted and P7 2 input AND/OR P6 and P7 both inverted 18 0 X 1 1 1 0 0 1 0 1 ______________________________________________________________________________________ 1 0 1 1 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 Table 14. CLA1 (P6–P9) Configuration Register Setting (0x29)(continued) REGISTER BIT FUNCTION D5 D4 D3 D2 D1 D0 2 input AND/OR P6 and P8 noninverted 0 0 2 input AND/OR P6 and P8 inverted 1 0 1 2 input AND/OR P6 inverted and P8 2 input AND/OR P6 and P8 both inverted 1 2 input AND/OR P7 and P8 noninverted 0 2 input AND/OR P7 and P8 inverted 1 2 input AND/OR P7 inverted and P8 2 input AND/OR P7 and P8 both inverted D7 D6 LOGIC LEVEL Cascade input noninverted 1 Cascade input inverted 0 Output noninverted 1 Output inverted 1 1 0 1 1 1 0 0 X 1 REGISTER REGISTER DATA D7–D2 D1 D0 CLA0 and CLA1 configurable logic lock CLA0 is not locked CLA0 is locked CLA1 is not locked CLA1 is locked Table 16. Configurable Logic-Array Enable Register (0x70) REGISTER 1 Table 17. Configurable Logic-Array Lock Register (0x71) FUNCTION 0 X 0 1 Table 15. Output P9 and Cascade P5 Input Configuration BIT 0 0 — — — — CLA1 CLA0 X X 0 1 0 1 X X REGISTER DATA D7–D2 D1 D0 CLA0 and CLA1 configurable logic enable CLA1 CLA0 Ports P2–P5 are GPIO ports — X 0 Ports P2–P5 are configurable logic CLA0 — X 1 Ports P6–P9 are GPIO ports — 0 X Ports P6–P9 are configurable logic CLA1 — 1 X ______________________________________________________________________________________ 19 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Table 18. Port I/O Registers (I/O Port 5 and 9 Configured as CLA Outputs, Registers 0x05 and 0x09) REGISTER BIT D7 D6 DESCRIPTION Don’t care Port supply reference VALUE x 0 1 0 1 FUNCTION Don’t care. Refers inputs to the VL supply voltage; sets outputs to open drain. Refers inputs to the VDD supply voltage; sets outputs to push-pull. Disables the transition interrupt. Enables the transition interrupt. D5 Transition interrupt enable D4 Transition detection bit 1 0 Detects the next transition on the port input. D3 Transition detection bit 0 0 Detects the next transition on the port input. D2 Debounce D1 Port transition state D0 Port status 0 1 0 1 0 1 Disables debouncing of the input port. Enables debouncing of the input port. No transition has occurred since the last port read. A transition has occurred since the last port read. Port input is logic-low. Port input is logic-high. Configurable Logic Array (CLA) The CLA configures groups of four ports as either a combinational logic gate up to three inputs, or a two input exclusive OR/NOR gate (see Tables 12-15). Eight-port dual groups can be cascaded to form a two-level gate with the intermediate term brought out as an output or not, as desired. If fewer than three gate inputs are needed, the unused CLA input(s) (which can be any combination of the three CLA inputs) remain available as independent GPIO ports (see Figure 8). Use the configurable logic-array enable register (see Table 16) to enable ports as CLAs. Use the configurable logic-array lock register (see Table 17) to permanently lock in any logic-array combination of CLAs until the next power cycle. Setting D0 and D1 to logichigh in the configurable logic-array lock register locks the corresponding bit position in the configurable logic-array enable register. Additionally, the appropriate CLA_ register (addresses 0x28 and 0x29) cannot be changed. The configurable logic-array lock register is unlocked on power-up, or by RST when configured by the 20 RSTPOR bit in the configure register. Each lock bit can only be written to once per power cycle. A CLA’s input(s) and output can be read through the serial interface like a normal input port. The MAX7302 creates a gate that provides an independent real-time logic function, and every node of it can be examined through the I2C interface with optional debounce and transition detection. Setting bits D0 and D1 to logic-high enables the CLA functionality and sets ports P5 and P9 as CLA outputs (see Table 16). When in CLA mode, the port I/O register data is interpreted differently for CLA output ports (see Table 18). Bit D7 that normally selects the port direction is ignored because either port P5 or P9 is always an output. Bit D6 sets both the CLA output type (push-pull or open drain) and the logic threshold for reading the CLA output status back through the I2C interface. The other bits set the readback options, such as debounce and transition detection interrupt. ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA MAX7302 ENABLE P2 PIN P2 DEBOUNCE TRANSITION DETECTION DEBOUNCE TRANSITION DETECTION INVERT P2 PIN P3 INVERT P3 P2–P5 [CLA0] ENABLE P3 ENABLE P4 PIN P4 DEBOUNCE TRANSITION DETECTION INVERT P4 INVERT P5 P5 OUTPUT REGISTER PIN P5 P5 IS CLA/GPIO ENABLE EXOR23 ENABLE EXOR23 = /D5 * D4 IN CLA REGISTER 0x28 INVERT P5 CASCADE ENABLE P5 CASCADE ENABLE P6 PIN P6 DEBOUNCE TRANSITION DETECTION DEBOUNCE TRANSITION DETECTION DEBOUNCE TRANSITION DETECTION INVERT P6 PIN P7 P6–P9 [CLA1] INVERT P7 ENABLE P7 ENABLE P8 PIN P8 INVERT P8 INVERT P9 P9 OUTPUT REGISTER PIN P9 P9 IS CLA/GPIO ENABLE EXOR67 ENABLE EXOR67 = /D5 * D4 IN CLA REGISTER 0x29 Figure 8. Configurable Logic-Array Structure P4 P5 P3 P2 P3 P4 P5 P6 P5 P6 P7 P7 P6 P7 P2 P2 P3 P4 P2 P7 P8 P9 P9 P3 P2 P7 P9 P9 P9 EXAMPLE 1: EXAMPLE 2: EXAMPLE 3: EXAMPLE 4: EXAMPLE 5: REGISTER 0x28: DATA VALUE 8’b1011_1110 REGISTER 0x28: DATA VALUE 8’b0010_0011 REGISTER 0x28: DATA VALUE 8’b1001_1011 REGISTER 0x28: DATA VALUE 8’b0101_1010 REGISTER 0x28: DATA VALUE 8’b1110_1111 REGISTER 0x29: DATA VALUE 8’b0000_1100 REGISTER 0x29: DATA VALUE 8’b0011_1101 REGISTER 0x29: DATA VALUE 8’b1101_1010 REGISTER 0x29: DATA VALUE 8’b0001_1010 REGISTER 0x29: DATA VALUE 8’b0101_1010 Figure 9. Configurable Logic Examples ______________________________________________________________________________________ 21 MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Serial Interface Serial-Addressing The MAX7302 operates as a slave that sends and receives data through an I2C-compatible, 2-wire interface. The interface uses a serial-data line (SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and from the MAX7302 and generates the SCL clock that synchronizes the data transfer (see Figure 10). The MAX7302 SDA line operates as both an input and an open-drain output. A 4.7kΩ (typ) pullup resistor is required on SDA. The MAX7302 SCL line operates only as an input. A 4.7kΩ (typ) pullup resistor is required on SCL if there are multiple masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output. Each transmission consists of a START condition (see Figure 11) sent by a master, followed by the MAX7302 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition (see Figure 11). START and STOP Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (see Figure 11). Bit Transfer One data bit is transferred during each clock pulse. The data on SDA must remain stable while SCL is high (see Figure 12). SDA tLOW tBUF tSU,STA tSU,DAT tHD,STA tSU,STO tHD,DAT tHIGH SCL tHD,STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION RESET tWL(RST) Figure 10. 2-Wire Serial Interface Timing Details SDA SDA SCL S P START CONDITION STOP CONDITION Figure 11. START and STOP Conditions 22 SCL DATA LINE STABLE; CHANGE OF DATA DATA VALID ALLOWED Figure 12. Bit Transfer ______________________________________________________________________________________ START CONDITION SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Message Format for Writing to the MAX7302 A write to the MAX7302 comprises the transmission of the MAX7302’s slave address with the R/W bit set to zero, followed by at least 1 byte of information (see Figure 16). The first byte of information is the command byte. The command byte determines which register of the MAX7302 is to be written to by the next byte, if received. If a STOP condition is detected after the command byte is received, the MAX7302 takes no further action beyond storing the command byte (see Figure 15). Any bytes received after the command byte are data bytes. The first data byte goes into the internal register of the MAX7302 selected by the command byte (see Figure 16). If multiple data bytes are transmitted before a STOP condition is detected, these bytes are generally stored in subsequent MAX7302 internal registers because the command byte address autoincrements (see Table 3). The Slave Address The MAX7302 has a 7-bit long slave address (Figure 14). The 8th bit following the 7-bit slave address is the R/W bit. Set R/W bit low for a write command and high for a read command. The first 5 bits of the MAX7302 slave address (A6–A2) are always 1, 0, 0, 1, and 1. Slave address bit A1, A0 is selected by the address input AD0. AD0 can be connected to GND, VDD, SDA, or SCL. The MAX7302 has four possible slave addresses (see Table 5), and therefore, a maximum of four MAX7302 devices can be controlled independently from the same interface. CLOCK PULSE FOR ACKNOWLEDGE START CONDITION SCL Message Format for Reading The MAX7302 is read using the MAX7302’s internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. The pointer autoincrements after each data byte is read using the same rules as for a write. Thus, a read is initiated by first configuring the MAX7302’s command byte by performing a write (Figure 15). The master can now read n consecutive bytes from the MAX7302 with the first data byte being read from the register addressed by the initialized command byte (see Figure 17). When performing readafter-write verification, remember to reset the command byte’s address because the stored command byte address has been autoincremented after the write. 1 2 8 9 SDA BY TRANSMITTER SDA BY RECEIVER S Figure 13. Acknowledge SDA 1 0 0 1 1 A1 R/W A0 MSB ACK LSB SCL Figure 14. Slave Address D15 D14 D13 D12 D11 D10 D9 D8 ACKNOWLEDGE FROM MAX7302 S SLAVE ADDRESS 0 R/W A REGISTER ADDRESS A P ACKNOWLEDGE FROM MAX7302 Figure 15. Register Address Received ______________________________________________________________________________________ 23 MAX7302 Acknowledge The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data (see Figure 13). Thus, each effectively transferred byte requires 9 bits. The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When the master is transmitting to the MAX7302, the MAX7302 generates the acknowledge bit because the MAX7302 is the recipient. When the MAX7302 is transmitting to the master, the master generates the acknowledge bit because the master is the recipient. MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA WRITE TO OUTPUT PORTS REGISTERS (P4) SCL 1 2 1 0 3 4 5 6 7 8 9 A1 A0 0 A SLAVE ADDRESS S SDA 0 1 COMMAND BYTE 1 START CONDITION 0 0 0 0 0 1 0 0 A ACKNOWLEDGE FROM SLAVE R/W MSB DATA LSB AA P STOP ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE DATA VALID P9 TO P1 tPPV Figure 16. Write to Output Port Registers READ FROM INPUT PORTS REGISTERS SCL S SDA 1 2 3 4 5 6 7 8 9 1 0 0 1 1 A1 A0 1 A R/W START CONDITION MSB LSB ACKNOWLEDGE FROM SLAVE DATA1 P9 TO P1 DATA1 A MSB DATA4 LSB NA STOP NO ACKNOWLEDGE ACKNOWLEDGE FROM MASTER DATA2 DATA3 tPH P DATA4 tPSU Figure 17. Read from Input Port Registers INTERRUPT VALID/RESET SCL SDA S 1 2 3 4 5 6 7 8 9 1 0 0 1 1 A1 A0 1 A START CONDITION P9 TO P1 R/W DATA1 MSB DATA2 LSB ACKNOWLEDGE FROM SLAVE A MSB DATA3 ACKNOWLEDGE FROM MASTER DATA2 LSB NA P STOP NO ACKNOWLEDGE DATA3 INT tIV tIR tIV tIR Figure 18. Interrupt and Reset Timing Operation with Multiple Masters If the MAX7302 is operated on a 2-wire interface with multiple masters, a master reading the MAX7302 should use a repeated start between the write that sets the MAX7302’s address pointer, and the read(s) that takes the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1 has set up the MAX7302’s address pointer, but before master 1 has read the data. If master 2 subsequently changes the MAX7302’s address pointer, then master 1’s delayed read can be from an unexpected location. 24 Bus Timeout Clear device configuration register 0x27 bit D7 to enable the bus timeout function (see Table 4), or set it to disable the bus timeout function. Enabling the timeout feature resets the MAX7302 serial-bus interface when SCL stops either high or low during a read or write. If either SCL or SDA is low for more than nominally 31ms after the start of a valid serial transfer, the interface resets itself and sets up SDA as an input. The MAX7302 then waits for another START condition. ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA Hot Insertion Serial interfaces SDA, SCL, and AD0 remain high impedance with up to 6V asserted on them when the MAX7302 is powered down (VDD = 0V) independent of the voltages on the port supply VLA. When VDD = 0V, or if VDD falls below the MAX7302’s reset threshold, all I/O ports become high impedance. The ports remain high impedance to signals between 0V and the port supply VLA. If a signal outside this range is applied to a port, the port’s protection diodes clamp the input signal to VLA or 0V, as appropriate. If supply VLA is lower than the input signal, the port pulls up VLA and the protection diode effectively powers any load on VLA from the input signal. This behavior is safe if the current through each protection diode is limited to 10mA. If it is important that I/O ports remain high impedance when all the supplies are powered down, including the port supply VLA, then ensure that there is no direct or parasitic path for MAX7302 input signals to drive current into either the regulator providing VLA or other circuits powered from VLA. One simple way to achieve this is with a series small-signal Schottky diode, such as the BAT54, between the port supply and the VLA input. Output Level Translation The open-drain output configuration of the ports allows them to level translate the outputs to lower (but not higher) voltages than the V LA supply. An external pullup resistor converts the high-impedance, logic-high condition to a positive voltage level. Connect the resistor to any voltage up to V LA. For interfacing CMOS inputs, a pullup resistor value of 220kΩ is a good starting point. Use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. Driving LED Loads When driving LEDs, use a resistor in series with the LED to limit the LED current to no more than 25mA. Choose the resistor value according to the following formula: RLED = (VSUPPLY - VLED - VOL) / ILED where: RLED is the resistance of the resistor in series with the LED (Ω) VSUPPLY is the supply voltage used to drive the LED (V) VLED is the forward voltage of the LED (V) V OL is the output low voltage of the MAX7302 when sinking ILED (V) ILED is the desired operating current of the LED (A). For example, to operate a 2.2V red LED at 20mA from a 5V supply, RLED = (5 - 2.2 - 0.8) / 0.020 = 100Ω. Driving Load Currents Higher than 25mA The MAX7302 can sink current from loads drawing more than 25mA by sharing the load across multiple ports configured as open-drain outputs. Use at least one output per 25mA of load current; for example, drive a 90mA white LED with four ports. The register structure of the MAX7302 allows only one port to be manipulated at a time. Do not connect ports directly in parallel because multiple ports cannot be switched high or low at the same time, which is necessary to share a load safely. Multiple ports can drive high-current LEDs because each port can use its own external current-limiting resistor to set that port’s current through the LED. The exceptions to this paralleling rule are the four ports, P2–P5, and the four ports, P6–P9. These groups of four ports can be programmed simultaneously through the pseudoregisters 0x3C and 0x3D, respectively. A write access to 0x3C writes the same data to registers 0x02 through 0x05. A write access to 0x3D writes the same data to registers 0x06 through 0x09. Either of these groups of four ports can be paralleled to drive a load up to 100mA. Power-Supply Considerations The MAX7302 operates with a VDD power-supply voltage of 1.62V to 3.6V. Bypass VDD to GND with a 0.047µF capacitor as close as possible to the device. The port supply VLA is connected to a supply voltage between 1.62V to 5.5V and bypassed with a 0.1µF capacitor as close as possible to the device. The VDD supply and port supply are independent and can be connected to different voltages or the same supply as required. Power supplies VDD and VLA can be sequenced in either order or together. ______________________________________________________________________________________ 25 MAX7302 Applications Information SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA 16 VDD ADO 2 15 SDA RST 3 14 SCL P7 + P8 VLA 1 P9 TOP VIEW SCL 12 11 10 9 SDA 13 8 GND 13 P9 VDD 14 7 P6 P2/OSCIN 5 12 P8 VLA 15 6 P5 P3/OSCOUT 6 11 P7 5 P4 10 GND P5 8 9 P6 QSOP AD0 16 *EP + 1 2 3 4 P3/OSCOUT P4 7 MAX7302 P2/OSCIN MAX7302 RST P1/INT 4 P1/INT MAX7302 Pin Configurations TQFN *EP = Exposed pad. Chip Information PROCESS: BiCMOS 26 ______________________________________________________________________________________ SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA QSOP.EPS PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH 21-0055 F 1 ______________________________________________________________________________________ 1 27 MAX7302 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) (NE - 1) X e E MARKING 12x16L QFN THIN.EPS MAX7302 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA E/2 D2/2 (ND - 1) X e D/2 AAAA e CL D D2 k CL b 0.10 M C A B E2/2 L E2 0.10 C C L 0.08 C C L A A2 A1 L L e e PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 28 ______________________________________________________________________________________ I 1 2 SMBus/I2C Interfaced 9-Port, Level-Translating GPIO and LED Driver with CLA PKG 8L 3x3 12L 3x3 REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. A 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 b 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 D 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 E 2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10 e L N 0.55 0.75 0.45 0.55 0.65 0.30 12 8 0.40 ND 2 3 4 2 3 4 0 A1 k 0.02 0.05 0 0.20 REF 0.25 - 0.02 0.05 0 0.20 REF - 0.25 0.50 16 NE A2 EXPOSED PAD VARIATIONS 0.50 BSC. 0.50 BSC. 0.65 BSC. 0.35 16L 3x3 - 0.02 0.05 0.20 REF - 0.25 - PKG. CODES E2 D2 MIN. NOM. MAX. MIN. NOM. MAX. PIN ID JEDEC TQ833-1 0.25 0.70 1.25 0.25 0.70 1.25 0.35 x 45° T1233-1 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEEC WEED-1 T1233-3 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 T1233-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-1 T1633-2 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633F-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633FH-3 0.65 0.80 0.95 0.65 0.80 0.95 0.225 x 45° WEED-2 T1633-4 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 T1633-5 0.95 1.10 1.25 0.95 1.10 1.25 0.35 x 45° WEED-2 - NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm. PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm 21-0136 I 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX7302 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)