MAXIM MAX9742

19-0731; Rev 0; 1/07
KIT
ATION
EVALU
E
L
B
AVAILA
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Features
The MAX9742 stereo Class D audio power amplifier
delivers up to 2 x 16W into 4Ω loads. The MAX9742
features high-power efficiency (92% with 8Ω loads),
eliminating the need for a bulky heatsink and conserving power. The MAX9742 operates from a 20V to 40V
single supply or a ±10V to ±20V dual supply. Features
include fully differential inputs, comprehensive clickand-pop suppression, low-power shutdown mode, and
an externally adjustable gain. Short-circuit and thermaloverload protection prevent the device from being
damaged during a fault condition.
The MAX9742 is available in a thermally efficient 36-pin
TQFN (6mm x 6mm x 0.8mm) package and is specified
over the -40°C to +85°C extended temperature range.
2 x 16W Output Power (RL = 4Ω, THD+N = 10%)
High Efficiency: Up to 92% with RL = 8Ω
Mute and Shutdown Modes
Differential Inputs Suppress Common-Mode Noise
Adjustable Gain
Integrated Click-and-Pop Suppression
Low 0.06% THD+N at 3.5W, RL = 8Ω
Output Short-Circuit and Thermal Protection
Available in Space-Saving, 6mm x 6mm, 36-Pin
TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9742ETX+
-40°C to +85°C
36 TQFN-EP*
Applications
CRT TVs
PKG
CODE
T3666-3
+Denotes lead-free package.
Flat-Panel Display TVs
*EP = Exposed paddle.
Audio Docking Stations
Pin Configuration located at end of data sheet.
Multimedia Monitors
Simplified Block Diagrams
RF1
SINGLE-SUPPLY CONFIGURATION
CFBL
20V TO 40V
FBL VDD
LEFT NEGATIVE
AUDIO INPUT
LEFT POSITIVE
AUDIO INPUT
CIN
CIN
RIN1
INL-
RIN2
MAX9742
CLASS D
MODULATOR AND
HALF-BRIDGE
INL+
RF2
OUTL
COUT
LF
RZBL
CFBL
CF
VDD
MID
CZBL
2
RF2
RIGHT POSITIVE
AUDIO INPUT
RIGHT NEGATIVE
AUDIO INPUT
CIN
RIN2
CIN
RIN1
CFBR
CLASS D
MODULATOR AND
HALF-BRIDGE
INR+
OUTR
COUT
LF
RZBL
INRCONTROL LOGIC/
POWER-UP
SEQUENCING
FBR
VSS
ON
RF1
CZBL
SFT
SHDN
CFBR
CF
CSFT
OFF
Simplified Block Diagrams continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9742
General Description
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
ABSOLUTE MAXIMUM RATINGS
VDD to VSS, NSENSE ..............................................-0.3V to +45V
MID, LGND, LVDD, REGM, REGP, OUTR,
OUTL to VSS .......................................................-0.3V to +45V
MID, LGND, LVDD, REGM, REGP, OUTR,
OUTL to VDD.......................................................-45V to +0.3V
REGLS to VSS .........................................................-0.3V to +12V
MID to REGP, REGM...............(VREGM - 0.3V) to (VREGP + 0.3V)
REGP to REGM.......................................................-0.3V to +12V
LVDD to LGND ..........................................................-0.3V to +6V
SHDN to LGND.........................................................-0.3V to +4V
SFT to LGND ............................................................-0.3V to +6V
FB_, IN_+, IN_-, REFCUR to REGP,
REGM..................................(VREGM - 0.3V) to (VREGP + 0.3V)
BOOTR to OUTR ....................................................-0.3V to +12V
BOOTL to OUTL .....................................................-0.3V to +12V
OUTR, OUTL Shorted to LGND..................................Continuous
Continuous Power Dissipation (TA = +70°C) (Note 1)
Single-Layer Board:
36-Pin TQFN (derate 26.3mW/°C above +70°C) ...........2.11W
Multilayer Board:
36-Pin TQFN (derate 35.7mW/°C above +70°C) ...........2.86W
Junction-to-Ambient Thermal Resistance (θJA)
Single-Layer Board:
36-Pin TQFN.................................................................38°C/W
Multilayer Board:
36-Pin TQFN.................................................................28°C/W
Junction-to-Case Thermal Resistance (θJC) ...................1.4°C/W
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Actual power capabilities are dependent on PCB layout. See the Thermal Considerations section.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single-Supply, Single-Ended Output
(VDD = 24V, VSS = VSUB = LGND = 0V, VSHDN = 3.3V, VMID = 12V, CVDD = 660µF, CMID1 = 10µF, CMID2 = 10µF, R1 = R2 = R3 =
10kΩ, CSFT = 0.47µF, COUT = 1000µF, CFB_1 = 150pF, CFB_2 = 10pF, CBOOT = 0.1µF, CREGP = CREGM = 1µF, RIN_ = 30.1kΩ,
RF1A = 121kΩ, RF1B = 562kΩ, RF2 = 681kΩ, RREF = 68kΩ, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
Supply Voltage Range
VDD
Supply Current
IDD
CONDITIONS
(Note 3)
MIN
TYP
20
MAX
UNITS
40
V
No load, output filter removed
15
mA
Mute Mode Supply Current
No load, VSFT = 0V (outputs not switching)
8
mA
Shutdown Current
No load, VSHDN = 0V
Switching Frequency
Power-Supply Rejection Ratio
(Note 4)
fSW
PSRR
Crosstalk
(Notes 5 and 6)
Continuous Output Power
(Notes 5, 6, and 7)
Efficiency
(Notes 5, 6, and 7)
2
POUT
0.8
1.3
mA
300
kHz
VDD = 24V + 500mVP-P, f = 1kHz
68
dB
L to R, R to L, RL = 8Ω, POUT = 1W, f = 1kHz
-78
dB
RL = 8Ω, fIN = 1kHz, THD+N = 10%
9.5
RL = 8Ω, fIN = 1kHz, THD+N = 10%,
VDD = 35V
20.5
RL = 4Ω, fIN = 1kHz, THD+N = 10%
16
RL = 8Ω, POUT = 9.5W, THD+N = 10%
92
_______________________________________________________________________________________
W
%
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
(VDD = 24V, VSS = VSUB = LGND = 0V, VSHDN = 3.3V, VMID = 12V, CVDD = 660µF, CMID1 = 10µF, CMID2 = 10µF, R1 = R2 = R3 =
10kΩ, CSFT = 0.47µF, COUT = 1000µF, CFB_1 = 150pF, CFB_2 = 10pF, CBOOT = 0.1µF, CREGP = CREGM = 1µF, RIN_ = 30.1kΩ,
RF1A = 121kΩ, RF1B = 562kΩ, RF2 = 681kΩ, RREF = 68kΩ, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.) (Note 2)
PARAMETER
Total Harmonic Distortion Plus
Noise
SYMBOL
THD+N
Signal-to-Noise Ratio
Half-Bridge Switch
On-Resistance
SNR
CONDITIONS
MIN
RL = 8Ω, POUT = 3.5W
0.06
RL = 4Ω, POUT = 5W
0.08
POUT = 9.5W, RL = 8Ω,
BW = 22Hz to 22kHz
(Notes 5 and 6)
Unweighted
88
A-weighted
93
0.4
No load (Note 4)
IMID
tSON
Power-On to Full Operation
tPU
Thermal-Overload Threshold
Temperature
0.7
Ω
+1
µA
50
-1
Shutdown-to-Full Operation
UNITS
dB
IN_ Input Bias Current
MID Input Bias Current
MAX
%
RDS(ON)
Switch Rise and Fall Times
TYP
fIN = 1kHz,
BW = 22Hz to 22kHz
(Notes 5, 6, and 7)
VDD = 24V, no load
ns
50
µA
68
ms
VSHDN = 3.3V
1.5
s
TSH
Junction temperature
150
Short-Circuit Output Current
ISC
OUT_ shorted to VDD or VSS
Click-and-Pop
KCP
Peak voltage, 32-samples
per second, A-weighted
(Notes 4 and 8)
2.9
o
4.5
Into shutdown
-38
Out of shutdown
-40
C
A
dBV
DIGITAL INPUTS (SHDN) (Note 9)
Logic-Input Low Voltage
VIL
Logic-Input High Voltage
VIH
0.4
V
+1
µA
2.4
Input Leakage Current
V
-1
ELECTRICAL CHARACTERISTICS—Dual Supplies
(VDD = 15V, VSS = VSUB = -15V, VSHDN = 3.3V, VMID = LGND = 0V, CVDD = CVSS = 1000µF, CBYP = 1µF, CSFT = 0.22µF, CFB_1 =
150pF, CFB_2 = 10pF, CBOOT = 0.1µF, CREGP = CREGM = 1µF, RIN_ = 30.1kΩ, RF1A = 121kΩ, RF1B = 562kΩ, RF2 = 681kΩ, RREF =
68kΩ, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
MAX
UNITS
Positive Supply Voltage Range
VDD
(Note 3)
CONDITIONS
10
20
V
Negative Supply Voltage
Range
VSS
(Note 3)
-20
-10
V
11
mA
Positive Supply Mute Mode
Current
No load, VSFT = 0V (outputs not switching)
Negative Supply Mute Mode
Current
No load, VSFT = 0V (outputs not switching)
MIN
TYP
8
-12
-8
mA
_______________________________________________________________________________________
3
MAX9742
ELECTRICAL CHARACTERISTICS—Single-Supply, Single-Ended Output (continued)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(VDD = 15V, VSS = VSUB = -15V, VSHDN = 3.3V, VMID = LGND = 0V, CVDD = CVSS = 1000µF, CBYP = 1µF, CSFT = 0.22µF, CFB_1 =
150pF, CFB_2 = 10pF, CBOOT = 0.1µF, CREGP = CREGM = 1µF, RIN_ = 30.1kΩ, RF1A = 121kΩ, RF1B = 562kΩ, RF2 = 681kΩ, RREF =
68kΩ, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Positive Supply Current
IDD
No load, output filter removed
Negative Supply Current
ISS
No load, output filter removed
Positive Supply Shutdown
Current
No load, VSHDN = 0V
Negative Supply Shutdown
Current
No load, VSHDN = 0V
Output Offset Voltage
Output referred, affected by RIN_ and RF_
tolerances (Note 4)
PSRR
POUT
Efficiency
(Notes 5, 6, and 7)
Total Harmonic Distortion
Plus Noise
Signal-to-Noise Ratio
23
36
-36
-23
-1
5
97
VSS = -10V to -20V
100
VDD = 15V + 500mVP-P, f = 1kHz
67
VSS = -15V + 500mVP-P, f = 1kHz
64
L to R, R to L, RL = 8Ω, POUT = 1W, f = 1kHz
-61
RL = 8Ω
14
RL = 8Ω, VDD = 18V,
VSS = -18V
21
fIN = 1kHz,
THD+N = 10%
(Notes 5, 6, and 7) R = 4Ω, V
L
DD = 12V,
VSS = -12V
SNR
mA
1
µA
µA
30
mV
+1
µA
dB
dB
W
9.5
RL = 8Ω, POUT = 15W, THD+N = 10%
THD+N
UNITS
mA
-0.03
VDD = 10V to 20V
93
fIN = 1kHz,
BW = 22Hz to 22kHz
(Notes 5, 6, and 7)
RL = 8Ω, POUT = 5W
0.06
RL = 4Ω, POUT = 10W
0.08
POUT = 14W,
RL = 8Ω, BW = 22Hz to
22kHz (Notes 5 and 6)
Unweighted
89
A-weighted
94
%
%
dB
Shutdown-to-Full Operation
tSON
Short-Circuit Output Current
ISC
OUT_ shorted to VDD or VSS
Click-and-Pop
KCP
Peak voltage, 32-samples
per second, A-weighted
(Notes 4 and 8)
4
MAX
-1
Crosstalk
(Notes 5 and 6)
Continuous Output Power
TYP
0.001
IN_ Input Bias Current
Power-Supply Rejection Ratio
(Note 4)
MIN
2.9
68
ms
4.5
A
Into shutdown
-36
Out of shutdown
-36
dBV
_______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
(VDD = 24V, VSS = VSUB = LGND = 0V, VSHDN = 3.3V, VMID = 12V, CVDD = 660µF, CMID1 = 10µF, CMID2 = 10µF, R1 = R2 = R3 =
10kΩ, CSFT = 0.47µF, COUT = 1000µF, CFB_1 = 150pF, CFB_2 = 10pF, CBOOT = 0.1µF, CREGP = CREGM = 1µF, RIN_ = 30.1kΩ, RF1A
= 121kΩ, RF1B = 562kΩ, RF2 = 681kΩ, RREF = 68kΩ, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA =
+25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Offset Voltage
(Note 4)
7
Power-Supply Rejection Ratio
(Note 4)
PSRR
VDD = 20V to 40V
88
VDD = 24V + 500mVP-P, f = 1kHz
77
Continuous Output Power
POUT
RL = 8Ω, fIN = 1kHz, THD+N = 10%,
(Notes 6, 10, and 11)
32
W
RL = 8Ω, POUT = 10W, THD+N = 10%,
(Notes 5 and 6)
83
%
0.08
%
Efficiency
Total Harmonic Distortion Plus
Noise (Notes 6, 10, and 11)
THD+N
Signal-to-Noise Ratio
SNR
Shutdown-to-Full Operation
tSON
Click-and-Pop
KCP
fIN = 1kHz, BW = 22Hz to 22kHz,
RL = 8Ω, POUT = 10W
POUT = 32W, RL = 8Ω,
BW = 22Hz to 22kHz
(Notes 6, 10, and 11)
Unweighted
90
A-weighted
96
68
Peak voltage, 32-samples
per second, A-weighted
(Notes 4, 11, and 12)
Into shutdown
-47
Out of shutdown
-32
mV
dB
dB
ms
dBV
Note 2: All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
Note 3: Supply pumping may occur at high output powers with low audio frequencies. Use proper supply bypassing to prevent the
device from entering overvoltage protection due to supply pumping. See the Supply Pumping Effects and the Supply
Undervoltage and Overvoltage Protection sections.
Note 4: Amplifier inputs AC-coupled to ground.
Note 5: For RL = 4Ω, LF = 22µH and CF = 0.68µF. For RL = 6Ω, LF = 33µH and CF = 0.47µF. For RL = 8Ω, LF = 47µH and CF =
0.33µF.
Note 6: Testing performed with four-layer PCB.
Note 7: Both channels driven in phase.
Note 8: Testing performed with an 8Ω resistor connected between LC filter output and ground. Mode transitions are controlled by
SHDN. KCP level is calculated as 20log[(peak voltage during mode transition, no input signal) / 1VRMS].
Note 9: Digital input specifications apply to both single-supply and dual-supply operation.
Note 10: Channels driven 180° out-of-phase. Load connected between LC filter outputs.
Note 11: LF = 22µH and CF = 0.68µF.
Note 12: Testing performed with an 8Ω resistor connected between LC filter outputs. Mode transitions are controlled by SHDN. KCP
level is calculated as 20log[(peak voltage during mode transition, no input signal) / 1VRMS].
_______________________________________________________________________________________
5
MAX9742
ELECTRICAL CHARACTERISTICS—Single-Supply, BTL Configuration
Typical Operating Characteristics
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
SINGLE SUPPLY
VDD = 24V
f = 1kHz
SINGLE SUPPLY
VDD = 32V
f = 1kHz
SINGLE SUPPLY
VDD = 36V
f = 1kHz
10
10
RL = 6Ω
1
RL = 8Ω
RL = 6Ω
1
THERMALLY
LIMITED
RL = 4Ω
0.1
THD+N (%)
RL = 8Ω
THD+N (%)
THD+N (%)
10
100
MAX9742 toc02
100
MAX9742 toc01
100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
MAX9742 toc03
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
0.1
RL = 8Ω
RL = 6Ω
1
THERMALLY
LIMITED
0.1
RL = 4Ω
RL = 4Ω
0.01
5
10
15
20
0
10
20
30
20
30
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
THERMALLY
LIMITED
0.1
10
VDD = 24V
VDD = 36V
1
0.1
10
20
30
40
f = 1kHz
f = 100Hz
0.01
0.01
0
1
0.1
THERMALLY
LIMITED
RL = 4Ω
0.01
DUAL SUPPLY
RL = 8Ω
THD+N (%)
THD+N (%)
1
0
10
20
30
40
0
50
5
10
15
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER (W)
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
SINGLE SUPPLY
VDD = 24V
RL = 4Ω
10
1
f = 1kHz
THD+N (%)
10
THD+N (%)
10
100
1
f = 1kHz
1
f = 1kHz
0.1
0.1
0.1
f = 100Hz
f = 100Hz
0.01
f = 100Hz
0.01
0.01
5
20
MAX9742 toc09
THERMALLY LIMITED
MAX9742 toc08
DUAL SUPPLY
RL = 4Ω
MAX9742 toc07
100
40
MAX9742 toc06
BTL
CONFIGURATION
VDD = 24V
RL = 8Ω
f = 1kHz
10
RL = 8Ω
100
MAX9742 toc05
100
MAX9742 toc04
RL = 6Ω
10
0
10
OUTPUT POWER PER CHANNEL (W)
SINGLE SUPPLY
VDD = 40V
f = 1kHz
10
15
20
25
OUTPUT POWER PER CHANNEL (W)
6
0
40
OUTPUT POWER PER CHANNEL (W)
100
THD+N (%)
0.01
0.01
0
THD+N (%)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
30
0
5
10
OUTPUT POWER PER CHANNEL (W)
15
0
5
10
15
OUTPUT POWER PER CHANNEL (W)
_______________________________________________________________________________________
20
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
1
f = 1kHz
0.1
f = 100Hz
1
f = 1kHz
1
f = 100Hz
f = 100Hz
0
10
20
30
5
10
0
15
5
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
DUAL SUPPLY
RL = 4Ω
10
0.1
f = 100Hz
1
THD+N (%)
THD+N (%)
f = 1kHz
POUT = 8W
POUT = 13W
1
0.1
0.1
0.01
MAX9742 toc15
DUAL SUPPLY
RL = 8Ω
POUT = 8W
POUT = 4W
0.001
20
30
1k
10k
1k
10k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
POUT = 9W
1
0.1
FREQUENCY (Hz)
100k
MAX9742 toc18
0.1
POUT = 12W
0.001
0.001
10k
POUT = 17W
1
0.01
0.01
0.001
1k
10
BTL CONFIGURATION
VDD = 24V
RL = 8Ω
POUT = 5W
POUT = 3W
100k
100
MAX9742 toc17
10
SINGLE SUPPLY
VDD = 24V
RL = 4Ω
THD+N (%)
0.1
0.01
100
MAX9742 toc16
POUT = 5W
100
100
100k
FREQUENCY (Hz)
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
1
100
THD+N (%)
THD+N (%)
40
OUTPUT POWER (W)
100
10
0.01
0.01
10
20
100
MAX9742 toc14
100
10
1
0
15
10
OUTPUT POWER (W)
BTL CONFIGURATION
VDD = 24V
RL = 8Ω
TA = 40°C
10
0
40
MAX9742 toc13
100
THD+N (%)
0.01
0.01
0.001
MAX9742 toc12
f = 1kHz
0.1
0.1
0.01
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
TA = 40°C
10
THD+N (%)
THD+N (%)
THD+N (%)
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
TA = 40°C
10
100
MAX9742 toc11
BTL CONFIGURATION
VDD = 24V
RL = 8Ω
10
100
MAX9742 toc10
100
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
Typical Operating Characteristics (continued)
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs.
OUTPUT POWER WITH AND WITHOUT T-NETWORK
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
POUT = 50mW
100
MAX9742 toc20
10
MAX9742 toc19
10
SINGLE SUPPLY
VDD = 24V
RL = 4Ω
POUT = 50mW
10
MAX9742 toc21
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
f = 1kHz
THD+N (%)
THD+N (%)
1
1
THD+N (%)
WITHOUT T-NETWORK
1
0.1
0.1
0.1
WITH T-NETWORK
100
100k
10k
1k
100k
10k
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
100
4.5
90
4.0
80
3.5
EFFICIENCY
60
3.0
50
2.5
40
2.0
30
1.5
SYSTEM POWER
DISSIPATION
20
10
SINGLE SUPPLY
VDD = 30V
RL = 8Ω
fIN = 1kHz
EFFICIENCY (%)
EFFICIENCY (%)
80
5.0
POWER DISSIPATION (W)
90
70
5
MAX9742 toc23
3.5
60
3.0
50
2.5
40
2.0
1.0
20
1.5
0.5
10
SYSTEM POWER
DISSIPATION
1.0
DUAL SUPPLY
RL = 8Ω
fIN = 1kHz
0.5
0
0
0
5
10
20
15
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
MAX9742 toc24
2.5
MAX9742 toc25
90
90
1.5
60
50
SYSTEM POWER
DISSIPATION
40
30
1.0
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
fIN = 1kHz
20
10
0
0
5
10
OUTPUT POWER PER CHANNEL (W)
0.5
70
EFFICIENCY (%)
EFFICIENCY
70
POWER DISSIPATION (W)
2.0
7
EFFICIENCY
6
60
SYSTEM POWER
DISSIPATION
50
0
5
4
40
3
30
SINGLE SUPPLY
VDD = 24V
RL = 4Ω
fIN = 1kHz
20
10
15
9
8
80
80
5.0
4.0
EFFICIENCY
OUTPUT POWER PER CHANNEL (W)
100
10
4.5
70
15
10
1
30
0
0
0
0.1
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
MAX9742 toc22
100
0.01
OUTPUT POWER PER CHANNEL (W)
FREQUENCY (Hz)
FREQUENCY (Hz)
POWER DISSIPATION (W)
1k
0
0
5
10
15
20
OUTPUT POWER PER CHANNEL (W)
_______________________________________________________________________________________
2
1
0
25
POWER DISSIPATION (W)
100
8
0.01
0.001
0.01
0.01
EFFICIENCY (%)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
100
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
6
60
SYSTEM POWER
DISSIPATION
4
30
3
BTL CONFIGURATION
VDD = 24V
RL = 8Ω
fIN = 1kHz
20
10
0
20
30
10
1% THD+N
5
0
10% THD+N
15
1% THD+N
10
5
0
0
50
40
±10
±12
±14
±16
±18
±10
±20
±12
±14
±16
±18
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
SINGLE SUPPLY
RL = 8Ω
25
10% THD+N
15
20
20
10% THD+N
15
10
1% THD+N
5
30
SINGLE SUPPLY
RL = 4Ω
25
10% THD+N
20
45
15
1% THD+N
10
±20
MAX9742 toc31
30
10
20
DUAL SUPPLY
RL = 4Ω
1
MAX9742 toc29
0
2
25
25
BTL CONFIGURATION
RL = 8Ω
40
35
OUTPUT POWER (W)
40
5
DUAL SUPPLY
RL = 8Ω
MAX9742 toc30
50
OUTPUT POWER PER CHANNEL (W)
7
EFFICIENCY
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY (%)
70
POWER DISSIPATION (W)
8
80
OUTPUT POWER PER CHANNEL (W)
30
9
OUTPUT POWER PER CHANNEL (W)
10
90
MAX9742 toc27
MAX9742 toc26
100
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
MAX9742 toc28
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
10% THD+N
30
25
1% THD+N
20
15
10
5
5
0
25
30
35
40
20
30
35
22
26
24
28
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0
-5
ISS
DUAL SUPPLY
OUTPUT FILTER REMOVED
NO LOAD CONNECTED
VDD = |VSS|
16
15
14
-10
13
-15
-20
±14
±16
SUPPLY VOLTAGE (V)
±18
±20
0
IDD
-10
-20
ISS
-30
DUAL SUPPLY
VDD = |VSS|
OUTPUT FILTER REMOVED
INPUTS GROUNDED
NO LOAD CONNECTED
-40
-50
-60
12
±12
10
SUPPLY CURRENT (nA)
5
17
SUPPLY CURRENT (mA)
IDD
SINGLE SUPPLY
OUTPUT FILTER REMOVED
INPUTS GROUNDED
NO LOAD CONNECTED
30
MAX9742 toc34
18
MAX9742 toc32
15
±10
20
40
SUPPLY VOLTAGE (V)
20
10
25
MAX9742 toc33
20
SUPPLY CURRENT (mA)
0
0
20
25
30
SUPPLY VOLTAGE (V)
35
40
±10
±12
±14
±16
±18
±20
±22
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
Typical Operating Characteristics (continued)
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
0.2
MAX9742 toc36
-60
-80
30
35
1.0
5k
10k
20k
15k
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
SINGLE SUPPLY
VDD = 24V + 500mVP-P
RL = 8Ω
0
-20
-40
BTL
VDD = 24V + 500mVP-P
RL = 8Ω
-10
-20
-30
OUT_ PSRR
PSRR (dB)
PSRR (dB)
-30
0
MAX9742 toc39
20
MAX9742 toc40
FREQUENCY (Hz)
-40
-60
VSS = -15V + 500mVP-P
-40
-50
-60
-70
-80
-60
-80
-100
-70
-90
MID PSRR
VDD = 15V + 500mVP-P
-80
-100
-120
10
1k
100
10k
1k
10k
10
100k
100
1k
CROSSTALK vs. FREQUENCY
EXITING SHUTDOWN
(DUAL SUPPLY)
20
-50
R INTO L
SINGLE SUPPLY
RL = 8Ω
POUT = 1W
0
CROSSTALK (dB)
-40
R INTO L
-40
VOUT_
20V/div
-60
FILTERED
VOUT_
5V/div
-80
-100
-80
L INTO R
L INTO R
-90
-120
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
100k
MAX9742 toc43
DUAL SUPPLY
RL = 8Ω
VSHDN
2V/div
-20
-70
10
10k
CROSSTALK vs. FREQUENCY
-30
-60
100
FREQUENCY (Hz)
MAX9742 toc41
-20
10
FREQUENCY (Hz)
DUAL SUPPLY
RL = 8Ω
POUT = 1W
-10
100k
FREQUENCY (Hz)
0
10
0
100
10
FREQUENCY (MHz)
-20
-50
-80
SUPPLY VOLTAGE (V)
DUAL SUPPLY
RL = 8Ω
-10
0.1
40
MAX9742 toc38
0
25
-60
-120
-120
20
-40
-100
-100
0
PSRR (dB)
-40
SINGLE SUPPLY
RL = 8Ω
fIN = 1kHz
VOUT_ = -60dBV
-20
OUTPUT AMPLITUDE (dBV)
0.4
0
MAX9742 toc42
SUPPLY CURRENT (mA)
0.6
RBW = 10kHz
MEASURED AT SINGLEENDED FILTER OUTPUT
INPUTS AC GROUNDED
-20
OUTPUT AMPLITUDE (dBV)
SINGLE SUPPLY
INPUTS AC GROUNDED
NO LOAD CONNECTED
0.8
OUTPUT SPECTRUM FFT
WIDEBAND OUTPUT SPECTRUM
0
MAX9742 toc35
1.0
MAX9742 toc37
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
CROSSTALK (dB)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
20ms/div
FREQUENCY (Hz)
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742 toc45
MAX9742 toc44
DUAL SUPPLY
RL = 8Ω
VOUT_
20V/div
FILTERED
VOUT_
5V/div
VOUT_
10V/div
VOUT_
10V/div
FILTERED
VOUT_
5V/div
FILTERED
VOUT_
5V/div
10ms/div
CASE TEMPERATURE
vs. OUTPUT POWER
CASE TEMPERATURE
vs. OUTPUT POWER
OUTPUT WAVEFORM
SINGLE SUPPLY
VDD = 24V
RL = 8Ω
4-LAYER PCB
10
0
4
6
8
10
MAX9742 toc48
SINGLE SUPPLY
VDD = 24V
RL = 4Ω
4-LAYER PCB
100
CASE TEMPERATURE (°C)
20
MAX9742 toc49
120
MAX9742 toc47
30
60
40
VOUTR
10V/div
20
0
12
0
5
10
15
EMI AMPLITUDE vs. FREQUENCY
EMI AMPLITUDE vs. FREQUENCY
MAX9742 toc50
SINGLE SUPPLY
RL = 8Ω, POUT = 1.25W
SPEAKER CABLE
LENTH = 1m
30
12.8dBµV/m
BELOW LIMIT
18.1dBµV/m
BELOW LIMIT
20
MAX9742 toc51
40
SINGLE SUPPLY
RL = 4Ω, POUT_ = 1.25W
SPEAKER CABLE
LENTH = 1m
35
EN55022B LIMIT
9.4dBµV/m BELOW LIMIT
25
1µs/div
20
OUTPUT POWER PER CHANNEL (W)
40
35
SINGLE SUPPLY, VDD = 24V
INPUTS AC GROUNDED
VOUT
10V/div
80
OUTPUT POWER PER CHANNEL (W)
AMPLITUDE (dBµV/m)
CASE TEMPERATURE (°C)
VSHDN
2V/div
20ms/div
40
2
SINGLE SUPPLY
RL = 8Ω
10ms/div
50
0
MAX9742 toc46
SINGLE SUPPLY
RL = 8Ω
VSHDN
2V/div
15
10
AMPLITUDE (dBµV/m)
VSHDN
2V/div
ENTERING SHUTDOWN
(SINGLE SUPPLY)
EXITING SHUTDOWN
ENTERING SHUTDOWN
30
11.3dBµV/m
BELOW LIMIT
25
EN55022B LIMIT
7.8dBµV/m
BELOW LIMIT
5.8dBµV/m
BELOW LIMIT
7dBµV/m
BELOW
LIMIT
20
15
10
5
3.6dBµV/m
BELOW LIMIT
5
30
100
FREQUENCY (MHz)
1000
30
100
1000
FREQUENCY (MHz)
______________________________________________________________________________________
11
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, ±15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, TA = +25°C, unless otherwise noted. See Figure 1 for test circuits, see Typical Application Circuits/Functional Diagrams for
test circuit component values.)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Pin Description
PIN
NAME
1, 6, 18,
27, 28, 36
N.C.
2, 3
OUTL
4
SUB
5
BOOTL
7
INL+
Left-Channel Positive Input
8
INL-
Left-Channel Negative Input. Connect an external feedback capacitor between INL- and FBL. See the
Feedback Capacitor (CFB_) section.
9
FBL
Left-Channel Feedback Capacitor Terminal. Connect an external feedback capacitor between FBL and
INL-. See the Feedback Capacitor (CFB_) section.
10
REGM
-5V Internal Regulator Output. Regulator output voltage is with respect to MID. Bypass REGM with a 1µF
capacitor to signal ground plane (SGND). See the Supply Bypassing/Layout section.
11
MID
Midsupply Bias Voltage Input. The MID input biases the internal preamplifiers to the average value of the
VDD and VSS supply inputs. For dual-supply operation, connect to the signal ground plane (SGND). For
single-supply operation, apply a voltage to MID equal to 0.5 x VDD through an external resistive voltagedivider and decoupling network (see the Setting VMID section). See the Typical Application
Circuits/Functional Diagrams and Supply Bypassing/Layout sections.
12
REGP
12
FUNCTION
No Connection. Not internally connected.
Left Speaker Output
Device Substrate. Connect SUB to VSS.
Left-Channel Bootstrap Capacitor Terminal. Connect a 0.1µF capacitor between BOOTL and OUTL.
5V Internal Regulator Output. Regulator output voltage is with respect to MID. Bypass REGP with a 1µF
capacitor to the signal ground plane (SGND). See the Supply Bypassing/Layout section.
13
REFCUR
Reference Current Resistor Terminal. Connect an external resistor from REFCUR to REGP to set the
switching frequency and output short-circuit current-limit value. Use resistor values greater than or equal
to 58kΩ and less than or equal to 75kΩ. See the Setting the Switching Frequency and Output Current
Limit (RREF) section.
14
SFT
Soft-Start Capacitor Terminal/Mute Input. Connect a 0.22µF capacitor between SFT and PGND to utilize
the soft-start power-up sequence. Drive SFT low to mute the outputs.
15
LGND
Logic Ground. Connect LGND to signal ground (SGND) and power ground (PGND) planes. See the
Supply Bypassing/Layout section.
16
LVDD
Internal 5V Logic Supply. Bypass LVDD to LGND with a 0.1µF capacitor.
17
SHDN
Active-Low Shutdown Input. Drive SHDN high for normal operation. Drive SHDN low to place the device
into shutdown mode.
19
FBR
Right-Channel Feedback Capacitor Terminal. Connect an external feedback capacitor between FBR and
INR-. See the Feedback Capacitor (CFB_) section.
20
INR-
Right-Channel Negative Input. Connect an external feedback capacitor between INR- and FBR. See the
Feedback Capacitor (CFB_) section.
21
INR+
Right-Channel Positive Input
22
NSENSE
23
REGLS
Negative Supply Sense Input. NSENSE is internally connected to VSS. Connect a 1µF bypass capacitor
between NSENSE and REGLS.
7V Internal Regulator Output. REGLS output voltage is with respect to VSS. Bypass REGLS with a 1µF
capacitor to NSENSE.
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
PIN
NAME
24
BOOTR
FUNCTION
25, 26
OUTR
29, 30,
34, 35
VDD
Positive Power-Supply Input. Bypass VDD to LGND with a 0.1µF plus additional bulk capacitance. See
the Supply Pumping Effects section.
31, 32, 33
VSS
Negative Power-Supply Input. For dual-supply operation, connect to negative power-supply voltage
and bypass VSS to LGND with a 0.1µF plus additional bulk capacitance. For single-supply operation,
connect to LGND.
EP
EP
Exposed Paddle. EP is internally connected to device substrate. Connect EP to VSS through a large
section of copper to maximize power dissipation.
Right-Channel Bootstrap Capacitor. Connect a 0.1µF capacitor between BOOTR and OUTR.
Right Speaker Output
Test Circuits
SINGLE-ENDED CONFIGURATION
LF
+
OUTL
CF
RL
AUX-0025
FILTER
+
-
AUDIO
ANALYZER
-
+
+
-
-
MAX9742
LF
OUTR
CF
RL
Detailed Description
The MAX9742 is a two-channel, single-ended Class D
stereo amplifier capable of providing 16W of output
power on each channel into 4Ω loads in single- or dualsupply operation. The amplifier can also provide 32W
of output power in a mono bridge-tied-load (BTL) configuration. The device offers Class AB audio performance with Class D efficiency.
The differential input architecture reduces commonmode noise pickup. The device can also be configured
for single-ended input signals.
The connection of external feedback components
allows custom gain settings.
Class D Operation and Efficiency
BTL CONFIGURATION
LF
+
OUTL
CF
LF
OUTR
AUX-0025
FILTER
RL
MAX9742
+
AUDIO
ANALYZER
CF
-
-
NOTE: SINGLE-ENDED CONFIGURATION IS AC-COUPLED IN SINGLE-SUPPLY MODE.
Figure 1. Test Circuits for Single-Ended and BTL Configurations
Class D amplifiers are switch-mode devices capable of
significantly higher power efficiencies in comparison to
linear amplifiers. The output stage of the MAX9742 consists of a half-bridge speaker driver (see Figure 2). The
high efficiency of a Class D amplifier is attributed to the
region of operation of the output stage transistors. In a
Class D amplifier, the output transistors act as currentsteering switches by switching the output between VDD
and V SS (ground for single-supply operation). Any
power loss associated with the Class D output stage is
mostly due to the I2R loss of the MOSFET on-resistance
and quiescent current overhead. The theoretical best
______________________________________________________________________________________
13
MAX9742
Pin Description (continued)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
efficiency of a linear amplifier is 78%; however, that efficiency is only exhibited at peak output powers. Under
normal operating levels (typical music reproduction levels), efficiency falls below 30%, whereas the MAX9742
still exhibits 80% efficiency under the same conditions.
Since the output transistors switch the output to either
VDD or VSS (ground for single-supply operation), the
resulting output of a Class D amplifier is a high-frequency square wave. This square wave is pulse-widthmodulated by the audio input signal. In the MAX9742,
the pulse-width modulation (PWM) is accomplished by
comparing the input audio signal to an internally generated triangle wave oscillator. The resulting duty cycle of
NSENSE
(INTERNALLY
CONNECTED TO VSS)
CREGLS
1µF
the square wave is proportional to the level of the input
signal. When the input signal is at 0V, the duty cycle of
the MAX9742 output is equal to 50%. To extract the
amplified audio signal from this PWM waveform, the
output of the MAX9742 is fed to an external LC lowpass
filter (see the Single-Ended LC Output Filter Design (LF
and CF) section). The LC filter works as an averaging
circuit for the PWM output voltage waveform. The
resulting averaged output voltage is equal to the amplified audio signal. Figure 3a illustrates the resulting
PWM output waveform due to the varying input signal
level, and Figure 3b shows the recovered amplified
input signal after filtering.
CBOOT
0.1µF
DBOOT
1N4148
VDD
REGLS
MAX9742
7V REGULATOR
(WITH RESPECT TO VSS)
OUT_
GATE DRIVE LOGIC
VREGLS
VSS
LF
CF
VSS
DUAL-SUPPLY CONFIGURATION SHOWN
Figure 2. Simplified Block Diagram of the MAX9742 Output Stage
14
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
1
fSW
INTERNAL TRIANGLE
WAVE OSCILLATOR
INPUT
SIGNAL
VDD
VOUT_
VDD + VSS
2
VSS
NOTE: FOR CLARITY, SIGNAL PERIODS ARE NOT SHOWN TO ACTUAL SCALE.
Figure 3a. MAX9742 Output with an Applied Input Signal
VOUT_
VDD
AVERAGE VALUE
OF VOUT_
VDD + VSS
2
VSS
NOTE: FOR CLARITY, SIGNAL PERIODS ARE NOT SHOWN TO ACTUAL SCALE.
Figure 3b. MAX9742 Output with Resulting Output After Filtering
______________________________________________________________________________________
15
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Shutdown Mode
The MAX9742 features a low-power shutdown mode
that reduces quiescent current consumption to less
than 0.5mA in single-supply mode and less than 1µA in
dual-supply mode. Drive SHDN low to place the device
into shutdown mode. Connect SHDN to a logic-high for
normal operation.
The maximum voltage that may be applied to the SHDN
input is 4V (see the Absolute Maximum Ratings section). If the SHDN input must be controlled by a 5V
logic signal, limit the maximum voltage that can be
applied to the SHDN input to 4V through an external
resistive divider.
Click-and-Pop Suppression
The MAX9742 features comprehensive click-and-pop
suppression that minimizes audible transients on startup and shutdown. While in shutdown, the half-bridge
output transistor switches are turned off, causing each
output to go high impedance. During startup, or powerup, the input amplifiers are muted and an internal loop
sets the modulator bias voltages to the correct levels,
minimizing audible clicks and pops when the output
half-bridge is enabled. The value of the soft-start
capacitor, CSFT, affects the click-and-pop performance
and startup time of the MAX9742 (see the Soft-Start
Capacitor (CSFT) section). To maximize click-and-pop
suppression when powering up an audio system, drive
SHDN or SFT (see the Mute Function section) to 0V
until the rest of the circuitry in the system has had
enough time to stabilize. This ensures the MAX9742 is
the last device to be activated in the system and prevents transients caused by circuitry preceding the
MAX9742 from being amplified at the outputs.
Supply Undervoltage and
Overvoltage Protection
The MAX9742 features an undervoltage protection
function that prevents the device from operating if VDD
is less than +7V with respect to VMID input or if VSS is
greater than -7V with respect to VMID. This feature prevents improper operation when insufficient supply voltages are present. Once the supply voltage exceeds the
undervoltage threshold, the MAX9742 is turned on and
the amplifiers are powered, provided that SHDN is high
and the outputs are unmuted.
The MAX9742 also features an overvoltage protection
function that prevents the device from operating if the
potential difference between VDD and VSS exceeds
+46V. This feature prevents the MAX9742 from damaging itself due to excessive supply pumping effects (see
the Supply Pumping Effects section). The device
returns to normal operation once the potential difference between VDD and VSS drops below +46V.
Applications Information
Output Dynamic Range
Dynamic range is the difference between the noise
floor of the system and the output level at 10% THD+N.
It is essential that a system’s dynamic range be known
before setting the maximum output gain. Output clipping occurs if the output signal is greater than the
dynamic range of the system.
Use the THD+N vs. Output Power graph in Typical
Operating Characteristics to identify the system’s
dynamic range. Given the system’s supply voltage, find
the output power that causes 10% THD+N for a given
load. Use the following equation to determine the peak-
Mute Function
The MAX9742 features a clickless/popless mute mode.
When the device is muted, the outputs stop switching,
muting the speaker. The mute function only affects the
output stage and does not shutdown the device. To
mute the MAX9742, drive SFT to ground. Figure 4
shows how an external transistor (MOSFET or BJT) can
be used to easily mute the MAX9742.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX9742. When the junction temperature
exceeds approximately +160°C, the thermal protection
circuitry disables the amplifier output stage. The amplifiers are enabled once the junction temperature cools
by approximately 15°C. This results in a pulsing output
under continuous thermal-overload conditions.
16
SFT
MUTE
CONTROL
LOGIC/POWER-UP
SEQUENCING
CSFT
UN-MUTE
10kΩ
Figure 4. MAX9742 Mute Circuit
______________________________________________________________________________________
MAX9742
TO
OUTPUT
STAGE
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
(
)
VOUT_P−P = 2 2 POUT_10% × RL (V)
where POUT_10% is the output power that causes 10%
THD+N, RL is the load resistance, and VOUT_P-P is the
peak-to-peak output voltage. Determine the voltage
gain (AV) necessary to attain this output voltage based
on the maximum peak-to-peak input voltage (VIN_P-P):
AV =
VOUT_P−P
VIN_P−P
(V / V)
Set the closed-loop voltage gain of the MAX9742 less
than or equal to AV to prevent clipping of the output,
unless audible clipping is acceptable for the application.
Input Amplifier
The external feedback networks of the MAX9742 input
amplifiers allow custom gain settings while maximizing
dynamic range. The input amplifiers also accommodate
a variety of standard amplifier configurations including
differential input, single-ended input, and summing
amplifiers. Due to the output current limitations of the
internal input amplifiers, always select feedback resistors
(RF1, see the Typical Application Circuits/Functional
Diagrams) with values greater than or equal to 400kΩ. To
preserve gain accuracy, avoid using feedback resistors
with values greater than 1MΩ. For proper operation, limit
common-mode input voltages to ±3V.
Differential Input Configuration
The Typical Application Circuits/Functional Diagrams
show each channel of the MAX9742 configured as differential input amplifiers. A differential input offers
improved noise immunity over a single-ended input. In
systems that include high-speed digital circuitry, highfrequency noise can couple into the amplifier’s input
traces. The signals appear at the amplifier’s inputs as
common-mode noise. A differential input amplifier
amplifies the difference of the two inputs, and signals
common to both inputs are subtracted out. When configured for differential inputs, the voltage gain of the
MAX9742 is set by:
AV =
RF1
(V / V)
RIN1
where A V is the desired voltage gain in V/V. R IN1
should be equal to RIN2, and RF1 should be equal to
RF2.
When using the differential input configuration, the
common-mode rejection ratio (CMRR) is primarily limited by the external resistor tolerances. Ideally, to
achieve the highest possible CMRR, the resistors
should be perfectly matched and the following condition should be met:
RF1
RF2
=
RIN1
RIN2
To ensure the MAX9742 input amplifiers operate as
fully differential integrators, connect a capacitor
between IN_+ and MID whose value is equal to CF (see
the Feedback Capacitor (CFB_) section).
Single-Ended Input
Each channel of the MAX9742 can be configured as a
single-ended input amplifier by connecting IN_+ to MID
(through an external resistor, ROS) and driving IN_- with
the input source (see Figure 5). In this configuration,
the MAX9742 is configured as a single-ended amplifier
whose voltage gain is equal to:
AV = −
RF
(V / V)
RIN
where AV is the desired voltage gain in V/V.
To minimize output offset voltages due to input bias currents, connect a resistor, ROS, (see Figure 5) between
IN_+ and MID. Select the value of ROS so that the DC
resistances looking out of inputs of the amplifier (IN_+
and IN_-) are equal. For example, when using the dualsupply configuration with a DC-coupled input source, the
value of ROS should be equal to RF||RIN.
RF
OUT_
CFB_
FB_
CIN
RIN
IN_-
MAX9742
TO CLASS D
MODULATOR
VIN
IN_+
ROS
MID
Figure 5. Single-Ended Input Configuration
______________________________________________________________________________________
17
MAX9742
to-peak output voltage that causes 10% THD+N for a
given load.
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Summing Configuration (Audio Mixer)
Figure 6 shows the MAX9742 configured as a summing
amplifier, which allows multiple audio sources to be linearly mixed together. Using this configuration, the output of the MAX9742 is equal to the weighted sum of the
input signals:
VOUT_ = − (VIN1
RF
RF
RF
+ VIN2
+ VIN3
)
RIN1
RIN2
RIN3
As shown in the above equation, the weighting or
amount of gain applied to each input signal source is
determined by the ratio of RF and the respective input
resistor (RIN1, RIN2, RIN3) connected to each signal
source. Select RF and RIN_ so that the dynamic range
of the MAX9742 is not exceeded when the input signals
are at their maximum values and in phase with each
other (see the Output Dynamic Range section).
To minimize output offset voltages due to input bias
currents, connect a resistor, R OS , (see Figure 6)
between IN_+ and MID. Select the value of ROS such
that the DC resistances looking out of inputs of the
amplifier (IN_+ and IN_-) are equal. For example, when
using the dual-supply configuration with a DC-coupled
input source, the value of R OS should be equal to
RF||RIN1||RIN2|| ||RINn.
Mono Bridge-Tied-Load (BTL)
Configuration
The MAX9742 also accommodates a mono bridge-tiedload (BTL) configuration that can be used in singlesupply and dual-supply applications. In the BTL
configuration, the speaker load is driven differentially
by connecting the half-bridge outputs as a full H-bridge
driver. To drive the speaker differentially, the inputs of
both channels must be driven by the same audio signal
with one channel 180° out-of-phase with the other
channel. Figure 7 shows the connections required for
BTL operation.
The advantages of BTL operation include reduced
component count due to the elimination of the outputcoupling capacitors when using single-supply operation, a 6dB increase in gain due to the load being
driven differentially, increased output power into a single load, and the minimization of the supply-pumping
since each half bridge is driven 180° out-of-phase (see
the Supply Pumping Effects section). For single-supply
applications, the output-coupling capacitors are not
needed for BTL operation since the DC voltage present
at each half-bridge output is equal in value and applies
to each side of the load. This means no DC voltage
appears across the load, and therefore, no DC current
flows into the speaker.
RF
OUT_
CFB_
FB_
CIN
VIN1
VIN2
RIN1
CIN
RIN2
CIN
RIN3
MAX9742
IN_TO CLASS D
MODULATOR
IN_+
VIN3
ROS
MID
R
R
R
VOUT_ (VIN1 F × VIN2 F × VIN3 F )
RIN2
RIN3
RIN1
Figure 6. Summing Amplifier Configuration
18
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Component Selection
Feedback Capacitor (CFB_)
To maximize dynamic range, an external feedback
capacitor (CFB_) is needed to generate an error signal
for the Class D modulator. The feedback capacitor configures the input amplifier stage as an integrator whose
output is equal to an error signal consisting of the sum
of the integrated input audio and PWM output signals.
The integrator provides a noise-shaping function for the
closed-loop response of the amplifier.
RF1
CFBL
FBL
VDD
DIFFERENTIAL
AUDIO INPUT
CIN
RIN1
CIN
RIN2
MAX9742
INLCLASS D
MODULATOR
AND GATE DRIVE
INL+
OUTL
LF
VOUT_P-P
VDD/2
CZBL
CF
CF
RF2
RZBL
VSS
MID
CF
CIN
CIN
RIN2
RIN1
2 x VOUT_P-P
0V
VDD
RZBL
RF2
CF
INR+
CLASS D
MODULATOR
AND GATE DRIVE
INR-
OUTR
LF
CZBL
VDD/2
VOUT_P-P
VSS
FBR
CFBR
RF1
R
AV_BTL = 2 × F_
RIN_
RIN1 = RIN2, RF1 = RF2
Figure 7. Input Signal Source and Load Connections for BTL Operation
______________________________________________________________________________________
19
MAX9742
Since each half-bridge output stage is only capable of
driving loads as small as 4Ω and each half-bridge sees
half of the differential load resistance when configured
for BTL, only use the BTL configuration with loads
greater than or equal to 8Ω. The MAX9742 may be thermally limited when using the BTL configuration with
high supply voltages due to the decreased load resistance seen by each half bridge. For optimum performance, the PCB should be thermally optimized to
achieve the continuous output powers required for the
application (see the Thermal Considerations section).
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
To guarantee stability and minimize distortion, select
the external feedback resistor (R F_ ) and capacitor
(CFB_) so that the following conditions are met:
RF_ × CFB_ ≥
21.5
and RF _ > 400kΩ
fSW
where f SW is the output switching frequency determined by R REF (see the Setting the Switching
Frequency and Output Current Limit (RREF) section).
Setting the Switching Frequency and
Output Current Limit (RREF)
Resistor RREF determines the output switching frequency
(fSW) and the output short-circuit current-limit value (ISC).
Set fSW and ISC with the following equations:
fSW =
1
(Hz)
68kΩ
RREF
68kΩ
(A)
ISC = 3.6A ×
RREF
3.3µs ×
For example, selecting a 68kΩ resistor for RREF results
in a switching frequency of 303kHz and an output
short-circuit current limit of 4.5A.
To prevent damage to the MAX9742 during output
short-circuit conditions and to utilize its full output
power capabilities, use resistor values greater than or
equal to 58kΩ and less than or equal to 75kΩ for RREF.
Input-Coupling Capacitor
The AC-coupling capacitors (CIN) and input resistors
(RIN_) form highpass filters that remove any DC bias
from an input signal (see the Typical Application
Circuits/Functional Diagrams). CIN prevents any DC
components from the input-signal source from appearing at the amplifier outputs. The -3dB point of the highpass filter, assuming zero source impedance due to the
input signal source, is given by:
f−3dB =
1
(Hz)
2π × RIN × CIN
Choose CIN so that f-3dB is well below the lowest frequency of interest. Setting f-3dB too high affects the amplifier’s
low-frequency response. Use capacitors with low-voltage
coefficient dielectrics. Aluminum electrolytic, tantalum, or
20
film dielectric capacitors are good choices for AC-coupling capacitors. Capacitors with high-voltage coefficients, such as ceramics (non-C0G dielectrics), can
result in increased distortion at low frequencies.
Single-Ended LC Output Filter Design (LF and CF)
An LC output filter is needed to extract the amplified
audio signal from the PWM output (see Figure 8). The LC
circuit forms an LCR lowpass filter (neglecting voice coil
inductance) with the impedance of the speaker. To provide a maximally flat-frequency response, the LCR filter
should be designed to have a Butterworth response and
should be optimized for a specific speaker load. Table 1
provides some recommended standard LF and CF component values for 4Ω, 6Ω, and 8Ω speaker loads. The
component values given in Table 1 provide an approximate -3dB cutoff frequency (fC) of 40kHz. The following
paragraph provides information on calculating filter component values for cutoff frequencies other than 40kHz
and speaker loads not listed in Table 1.
The LCR filter has the following 2nd order transfer function:
1
LF × CF
H(s) =
1
1
s2 +
s +
RSPKR × CF
LF × CF
where LF is the value of the filter inductor, CF is the
value of the filter capacitor, and RSPKR is the DC resistance of the speaker. The voice coil inductance of the
speaker has been neglected to simplify filter calculations (see the Zobel Network section). The above transfer function is presented in the general 2nd order
transfer function format given below:
H(s) =
ωn2
s 2 + 2 × ζ × ωn × s + ωn2
where wn is the natural frequency in radians/s and ζ is
the damping ratio of the 2nd order system. For an ideal
Butterworth response, ζ is equal to 0.707 and ωC is
equal to the -3dB cutoff frequency, ωc. Using the above
transfer functions and converting to Hertz, the -3dB cutoff frequency of the filter is:
fC =
1
2 × π ×
(Hz)
LF × CF
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
1
(F)
4 × π × fC × RSPKR × ζ
1
LF =
(H)
2
4 × π × fC2 × CF
CF =
Since the frequency response of the output filter is
dependent on the speaker resistance, it is best to optimize the LC filter for a particular load resistance. To
calculate the component values of the LC filter for a
given speaker load resistance, first select an appropriate cutoff frequency for the filter. The cutoff frequency
should be high enough so that upper audio frequency
band attenuation is kept to a minimum while providing
sufficient attenuation at the switching frequency (fSW) of
the MAX9742. Once the cutoff frequency is determined,
calculate CF using the DC resistance of the speaker
(RSPKR) and a damping ratio (ζ) equal to 0.707. Finally,
calculate LF using the resulting CF value.
When selecting CF, use capacitors with DC voltage ratings greater than VDD.
When selecting LF, it is important to take into account
the DC resistance, current capabilities, and upper frequency limitations of the inductor. Choosing an inductor with minimum DC resistance minimizes I2R losses
due to the filter inductor and therefore preserves power
efficiency. The inductor current rating should be
greater than the maximum peak output current to prevent the inductor from going into saturation. Output
inductor saturation introduces nonlinearities into the
output signal and therefore increases distortion. The
Table 1. Recommended LC Filter
Component Values for Various Speaker
Loads (fC = 40kHz)
DC RESISTANCE OF SPEAKER (Ω)
LF (µH)
CF (µF)
4
22
0.68
6
33
0.47
8
47
0.33
upper frequency limit of the inductor should also be
taken into account. The load connected to the output of
the half-bridge (LC filter and speaker) should remain
inductive at the switching frequency of the MAX9742. If
not, a significant amount of high-frequency energy is
dissipated in the resistive load, therefore, increasing
the supply current to excessive levels. To prevent this
from occurring, select an output inductor whose selfresonant frequency is substantially higher than the
switching frequency of the MAX9742.
To minimize possible EMI radiation, place the LC filter
near the MAX9742 on the PCB.
Table 2 provides some suggested inductor manufacturers.
BTL LC Output Filter Design
When using the BTL configuration, optimize the output filter for fully differential operation (see Figure 9 and Table
3). Follow the design criteria provided for the singleended filter except use half the value of the BTL resistance for the output filter calculations. This is because
each half-bridge output sees half of the BTL resistance.
For example, with a BTL resistance of 8Ω the ideal filter
component values are CF = 0.7µF and LF = 22.5µH for a
maximally flat differential filter response with an approximate cutoff frequency of 40kHz. Rounding to the nearest
standard component values yields CF = 0.68µF and LF =
22µH. Also connect ground-terminated Zobel networks
on each side of the speaker load (see the Zobel Network
section). Ground terminating the Zobel networks prevents excessive peaking in the common-mode frequency response of the filter.
SINGLE-ENDED OUTPUT FILTER
LF
OUT_
RSPKR
CF
NOTE: AN OUTPUT-COUPLING CAPACITOR (COUT) IS NEEDED FOR SINGLE-SUPPLY,
SINGLE-ENDED OUTPUT CONFIGURATION.
Figure 8. Single-Ended LC Output Filter
Table 2. Suggested Inductor Manufacturers
MODEL
DO3340P
MANUFACTURER
Coilcraft
DIMENSIONS
WEBSITE
12.95mm x 9.4mm x 11.43mm
www.coilcraft.com
CDRH127
Sumida
12.3mm x 12.3mm x 8mm
www.sumida.com
11RHBP
Toko
11mm x 11mm x 13.75mm
www.tokoam.com
SLF12575
TDK
12.5mm x 12.5mm x 7.5mm
www.component.tdk.com
______________________________________________________________________________________
21
MAX9742
Using the transfer functions and the equation for fc, the
following expressions for LF and CF can be derived:
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
To maximize the performance of the differential output
filter and minimize EMI radiation, keep the ground connections of the CF capacitors close together on the
PCB and place the filter near the MAX9742.
The component ratings for CF and LF follow the same
requirements mentioned in the Single-Ended LC Output
Filter Design (LF and CF) section.
Zobel Network
For speaker loads that have appreciable amounts of
voice coil inductance (> 33µH), peaking in the frequency response of the output may occur near the cutoff frequency of the LC filter, which may cause the device to
go into current limit at high output powers. This peaking
is due to the resonant circuit formed by the LC output
filter and complex impedance of the speaker. To nullify
the peaking in the frequency response, connect a
Zobel network (series RC circuit) in parallel with the
speaker load as shown in Figure 10. The Zobel circuit
reduces the peaking by dampening the reactive behavior of the speaker. For the single-ended output configuration, use the following equations to calculate the
component values for the Zobel network:
the LC filter. For the BTL configuration, use half of the
BTL resistance for the Zobel network calculations.
Connect a ground-terminated Zobel network on each
side of the BTL resistance to prevent excessive peaking in the common-mode response of the output filter.
For most applications, RZBL should have a minimum
power rating of 1/4W or greater. CZBL should have a
voltage rating greater than or equal to VDD.
Table 3. Recommended Differential LC
Filter Component Values for an 8Ω BTL
Speaker Load (fC = 40kHz)
DC Resistance of Speaker (Ω)
LF (µH)
CF (µF)
8
22
0.68
LF
OUT_
RZBL
RZBL = 1.2 × RSPKR (Ω)
1
(F)
CZBL =
2π × RSPKR × fC
where RZBL is the value of the Zobel resistor, CZBL is
the value of the Zobel capacitor, RSPKR is the DC resistance of the speaker, and fC is the cutoff frequency of
LSPKR
SPEAKER
LOAD
CF
CZBL
RSPKR
LF
OUTL
CF
BRIDGE-TIED-LOAD (BTL) OUTPUT FILTER
RZBL
CZBL
LF
LSPKR
SPEAKER
LOAD
OUTL
CZBL
RSPKR
CF
CF
RSPKR
CF
LF
OUTR
Figure 9. BTL LC Output Filter
22
RZBL
LF
OUTR
NOTE: AN OUTPUT-COUPLING CAPACITOR (COUT) IS NEEDED FOR SINGLE-SUPPLY,
SINGLE-ENDED OUTPUT CONFIGURATION.
Figure 10. Zobel Network Connections for High-Inductance
Speakers
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Capacitor (CBOOT)
For most applications, use a CBOOT capacitor ≥ 0.1µF
and ≤ 0.22µF. For proper operation, use capacitors with
low ESR and voltage ratings greater than 7V for CBOOT.
Output-Coupling Capacitors
(COUT, Single-Ended, Single-Supply Operation)
The MAX9742 requires output-coupling capacitors for
single-supply operation. Since the MAX9742 outputs
switch between VDD and ground in single-supply operation, there is a DC component equal to 0.5 x VDD present at the outputs. The output-coupling capacitor
blocks this DC component, preventing DC current from
flowing into the load. The output capacitor and the load
resistance of the speaker form a highpass filter. The
-3dB point of the highpass filter can be approximated by:
f−3dB =
1
2π × RSPKR × COUT
(Hz)
where f-3dB is the -3dB cutoff frequency of the filter,
RSPKR is the DC resistance of the speaker, and COUT is
the value of the output-coupling capacitor. As with the
input capacitor, choose COUT such that f-3dB is well
below the lowest frequency of interest. Setting f-3dB too
high affects the amplifier‘s low-frequency response.
Select capacitors with low ESR to minimize power losses. Since the output-coupling capacitor has a large
amplitude AC current (resulting average output current
due to the LC filter) flowing through it at high output
powers, it is important to select an output-coupling
capacitor that has an appropriate ripple current rating.
To prevent damage to the output-coupling capacitor,
use the following equation to calculate the required
RMS ripple current rating for COUT:
IRMS_RIPPLE =
VDD
(A)
2.83 × RSPKR
where IRMS_RIPPLE is the minimum required RMS ripple
current rating for COUT and RSPKR is the DC resistance
of the speaker. The ripple current ratings of capacitors
are frequency dependent, so be sure to select a
capacitor based on its ripple current rating within the
audio frequency range.
Select output-coupling capacitors with DC voltage ratings greater than VDD.
In single-supply operation with single-ended outputs, the
leakage current of COUT can affect the startup time of
the MAX9742. To minimize startup time delays due to
COUT, use capacitors with leakage current ratings less
than 1µA for COUT. See the Startup Time Considerations
section for more information on optimizing the startup
time of the MAX9742.
Setting VMID
The voltage present at the MID input biases the internal
amplifiers and should be set to the average value of
VDD and VSS for maximum dynamic range. For dualsupply operation, connect MID to ground. For singlesupply operation, set MID to 0.5 x V DD through an
external resistive divider. To minimize power dissipation
while providing enough input bias current for the MID
input, select divider-resistors with values greater than
or equal to 10kΩ and less than or equal to 20kΩ.
Connect a decoupling network between MID and the
SGND plane (see the Supply Bypassing/Layout section) to provide a sufficient low- and high-frequency AC
ground for the internal amplifiers. Figure 11 shows the
recommended decoupling networks for bypassing the
MID input.
______________________________________________________________________________________
23
MAX9742
Bootstrap Diode (DBOOT)
To provide sufficient gate drive voltage to the high-side
transistor of the half-bridge output stage, an external
diode (DBOOT) and capacitor (CBOOT) are needed for
the internal bootstrapping circuitry (see Figure 2). To
maintain high power efficiencies and maximum output
power at low audio frequencies, use fast-recovery
switching diodes for DBOOT. Silicon diodes equivalent
to 1N914, BAS16, or 1N4148 work well.
Multiple-Pole MID Network vs.
Single-Pole VMID Network for Increased PSRR
Performance (Single-Supply Operation)
A multiple-pole MID network improves PSRR performance over a single-pole network. Since the input
amplifiers of the MAX9742 are biased at V MID, any
noise coupled into the MID input using the MID bias
network supply appears at the outputs of the MAX9742.
Increasing the number of poles in the MID network provides further attenuation of low-frequency noise at the
MID input, and therefore, improving the AC PSRR performance of the MAX9742. Figure 11 shows the recommended single-pole and two-pole MID input bias
networks. Figure 12 illustrates the differences of the
MAX9742’s low-frequency AC PSRR performance with
the single-pole and two-pole networks shown in Figure
11.
SINGLE-POLE NETWORK
VDD
Soft-Start Capacitor (CSFT)
The soft-start capacitor determines the timing for the
soft-start power-up sequencing that minimizes audible
clicks-and-pops during power-up/power-down transitions and when entering/exiting shutdown mode.
Connect a capacitor between SFT and ground for
proper operation. For optimum performance, this
capacitor should equal 0.22µF. Using capacitor values
much smaller than these values degrade click-andpop performance and values much greater lengthen
startup time.
Startup Time Considerations
At the beginning of the soft-start sequence, the
MAX9742 ensures V OUT_ is approximately equal to
VMID before continuing the soft-start sequence. For single-supply operation with single-ended outputs, the
output-coupling capacitors (COUT) are first gradually
charged up to V MID before continuing soft-start
sequencing. This gradual charging up of COUT minimizes audible transients that may appear across the
R1
10kΩ
TO
MID
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
CMID2
1µF
20
SINGLE SUPPLY
VDD = 24V + 500mVP-P
RL = 8Ω
0
-20
TWO-POLE NETWORK
VDD
R1
10kΩ
R2
10kΩ
1-POLE MID NETWORK
-40
-60
-80
R3
10kΩ
CMID1
10µF
MAX9742 fg12
CMID1
22µF
R2
10kΩ
PSRR (dB)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
TO
MID
CMID2
10µF
2-POLE MID NETWORK
-100
-120
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 11. Recommended MID Input Bias Networks
24
Figure 12. Comparison of MAX9742 AC PSRR with Single-Pole
and Two-Pole MID Networks
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
For dual-supply operation, the startup time of the
MAX9742 is primarily dependent on the value of CSFT
since it controls the rate of the soft-start sequencing.
In single-supply operation, the overall startup time is
affected by the values of CMID1, CMID2, CSFT, COUT
(single-ended outputs) and the value of the resistors
used to bias the MID input. This is because soft-start
power-up sequencing is dependent on the charging-up
of the MID input bias network and the charging rate of
COUT. As with dual-supply operation, the startup time is
also affected by the value of CSFT since it controls the
rate of the soft-start sequencing. Using the component
values shown in Figure 11 and a CSFT capacitor value
of 0.22µF yields a typical single-supply power-up time
of 1.5s.
For single-supply operation with single-ended outputs,
the leakage current of COUT can also affect the startup
time of the MAX9742. To minimize startup time delays
due to COUT, use capacitors with leakage current ratings less than 1µA for COUT.
Supply Pumping Effects
When using the MAX9742 in the single-ended output
configuration, the power-supply voltages (V DD and
VSS) may increase if the supplies cannot sink current.
This “supply pumping” is primarily due to the inductive
loading of the LC filter and the voice coil inductance of
the speaker. The inductive load connected to the output of the device prevents the output current from
changing instantaneously. When the MAX9742 drives
this inductive load, a continuous current flows at the
output whose value is equal to the running average of
the output switching currents, or in other words, the
amplified audio signal. This averaged current continues
to flow during both switching cycles of the half-bridge,
which means that some of the current is pumped back
towards the opposite power supply. If the respective
supply cannot sink this current, it flows into supply
bypass capacitor causing the voltage across the
capacitor to increase.
The amount of current pumped back into the opposite
supply is proportional to the duty cycle of the switching
period. For example, if the magnitude of the average
(continuous) current during a single switching cycle is
equal to -1A and the duty cycle of the output is equal to
25%, this means the VSS supply provides 0.75A of current while the VDD supply must sink 0.25A. Since the
VDD supply cannot sink this current, it flows into the
bypass capacitor causing the VDD supply voltage to be
pumped up. Figures 13a and 13b illustrates the continuous output current flow that causes the supply pumping action.
______________________________________________________________________________________
25
MAX9742
speaker loads during mode transitions. After COUT is
charged up to VMID, the MAX9742 concludes the softstart sequence by precharging CREGLS, CBOOT, and
C IN. Once the soft-start sequence is complete, the
MAX9742 begins normal operation.
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
IPUMP = DUTY CYCLE x IAVG
VDD
CVDD
OFF
VDD
CVDD
ON
LF
IAVG
IAVG
LF
CF
CF
OFF
ON
VSS
CVSS
VSS
CVSS
CASE 1: IAVG FLOWING INTO HALF-BRIDGE CAUSING VOLTAGE ACROSS CVDD TO INCREASE (DUTY CYCLE < 50%).
IAVG = AVERAGE (CONTINUOUS) OUTPUT CURRENT DURING ONE SWITCHING CYCLE.
IPUMP = AMOUNT OF CURRENT PUMPED INTO SUPPLY BYPASS CAPACITOR.
Figure 13a. Continuous Output Current Flow for Positive Supply Pumping
VDD
CVDD
VDD
CVDD
OFF
ON
IAVG
LF
LF
IAVG
CF
CF
ON
OFF
CVSS
VSS
IPUMP = DUTY CYCLE x IAVG
CVSS
VSS
CASE 2: IAVG FLOWING OUT OF HALF-BRIDGE CAUSING VOLTAGE ACROSS CVSS TO INCREASE (DUTY CYCLE > 50%).
IAVG = AVERAGE (CONTINUOUS) OUTPUT CURRENT DURING ONE SWITCHING CYCLE.
IPUMP = AMOUNT OF CURRENT PUMPED INTO SUPPLY BYPASS CAPACITOR.
Figure 13b. Continuous Output Current Flow for Negative Supply Pumping
26
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
capacitor decreases the supply voltage variations due
to supply pumping. Using large bypass capacitors
helps minimize supply voltage variations by providing
sufficient supply decoupling at low output frequencies.
To prevent the MAX9742 from entering supply overvoltage protection mode at low output frequencies (as low
as 20Hz), use supply bypass capacitors with values of
at least 1000µF for dual-supply operation and 660µF for
single-supply operation.
Alternate Methods for Mitigating Supply Pumping
Using the BTL configuration minimizes the supply
pumping effect since the outputs are driven 180° outof-phase with each other. Driving the outputs 180° outof-phase causes each half-bridge to pump up and
draw current from opposite supplies, which reduces
the magnitude of the of the supply pumping.
For the single-ended output configuration, the supply
pumping can be minimized by driving the channels
180° out-of-phase and reversing the polarity of one
speaker connection (see Figure 14). Reversing the
polarity of one speaker minimizes any adverse affects
on the audio quality by ensuring that the physical displacement of the speaker cones matches the physical
displacement of the speakers when driven with in
phase signals.
⎛ VSUPPLY ⎞
1
⎛
⎞
VPUMP_MAX = ⎜
⎟
⎟ × ⎜⎝ f
OUT × RSPKR × CSUPPLY ⎠
⎝ 2π 2 ⎠
where VPUMP_MAX is the magnitude increase of the
supply rail, VSUPPLY is the nominal voltage magnitude
of the respective supply, fOUT is the frequency of the
audio signal, and CSUPPLY is the value of the respective supply bypass capacitor. The above equation
shows that increasing the value of the supply bypass
RF1
CFBL
CIN
RIN1
VDD
FBL
INL-
LEFT-CHANNEL
AUDIO INPUT
+
CIN
-
RIN2
LF
INL+
CFBL
-
OUTL
CF
RF2
+
MAX9742
MID
CFBR
CIN
LF
+
OUTR
INR+
+
RIGHT-CHANNEL
AUDIO INPUT
RF2
RIN2
CF
CIN
-
-
RIN1
INRFBR
AV -
RF
CFBR
RIN_
RIN1 = RIN2, RF1 = RF2
DUAL-SUPPLY CONFIGURATION
RF1
VSS
Figure 14. Circuit Configuration for Minimizing Supply Pumping
______________________________________________________________________________________
27
MAX9742
Worst-case supply pumping occurs at high output powers with low-frequency signals and small load resistances. Since the period is longer for low-frequency
signals, the continuous output current has more time to
pump up the supply rails during each cycle of the
audio signal. Additionally, for most stereo audio
sources the low-frequency audio content (bass) is primarily monophonic. This means both output channels
are basically equal in magnitude and in phase at low
frequencies causing twice as much pump-up current to
flow into the supply bypass capacitors and therefore
doubling the supply pump-up voltages. Assuming
purely sinusoidal output signals, the worst-case supply
voltage increase due to supply pumping can be
approximated using the following equation:
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
T-Network for Low THD Performance
at Low Output Powers (Optional)
If low THD+N performance is needed at low-output powers, replace the feedback resistor (RF1) in each channel
with the T-network shown in Figure 15. The T-network
provides additional attenuation of audio band noise,
therefore, providing improved THD+N performance at
lower output powers. Use the following expressions to
select RIN1, RIN2, RF1a, RF1b, and RF2:
RIN1 =
Output Limiting Diodes (Optional)
In applications where the output can be driven to clipping, a pair of diodes around the feedback capacitor
helps reduce distortion. Clipping is most likely to happen when driving high-impedance speakers with lower
supply voltages, for example, 8Ω loads with a 24V single supply. Diodes such as BAV99, a dual series silicon
switching diode, are a good choice. Connect these
diodes around the feedback capacitor as shown in
Figure 16.
RF1a + RF1b
683kΩ
121kΩ + 562kΩ
=
=
(Ω)
AV
AV
AV
RIN1 = RIN2 (Ω)
RF2 = RF1a + RF1b (Ω)
CFB_
where AV is the desired voltage gain in V/V. To maximize CMRR and minimize gain mismatch between
channels, use the closest 1% tolerance resistor values
available for RIN1, RIN2, RF1a, RF1b, and RF2.
See the THD+N vs. Output Power With and Without
T-Network plot in the Typical Operating Characteristics
for a comparison of the THD+N performance with and
without the optional T-network.
TO IN_-
TO FB_
Figure 16. Connection of Output Limiting Diodes
RF1b
562kΩ
RF1a
121kΩ
TO OUT_
CFB_2
10pF
R +R
AV = F1a F1b
RIN1
RF2 = RF1a + RF1b = 688kΩ
RIN1 = RIN2
CFB_1
150pF
FB_
CIN
RIN1
CIN
RIN2
NEGATIVE
AUDIO INPUT
POSITIVE
AUDIO INPUT
MAX9742
IN_TO CLASS D
MODULATOR
IN_+
RF2
681kΩ
CFB_1
150pF
TO MID
Figure 15. Optional T-Network for Minimizing THD+N at Low Output Powers
28
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Thermal Considerations
Class D amplifiers provide much better efficiency and
thermal performance than a comparable Class AB
amplifier. However, the system’s thermal performance
must be considered with realistic expectations along
with its many parameters.
Continuous Sine Wave vs. Music
When a Class D amplifier is evaluated in the lab, often
a continuous sine wave is used as the signal source.
While this is convenient for measurement purposes, it
represents a worst-case scenario for thermal loading
on the amplifier. It is not uncommon for a Class D
amplifier to enter thermal shutdown if driven near maximum output power with a continuous sine wave. The
PCB must be optimized for best dissipation (see the
PCB Thermal Considerations section). Audio content,
both music and voice, has a much lower RMS value relative to its peak output power. Therefore, while an
audio signal may reach similar peaks as a continuous
sine wave, the actual thermal impact on the Class D
amplifier is highly reduced. If the thermal performance
of a system is being evaluated, it is important to use
actual audio signals instead of sine waves for testing. If
sine waves must be used, the thermal performance is
less than the system’s actual capability for real music
or voice.
PCB Thermal Considerations
The exposed paddle is the primary route for conducting
heat away from the IC. With a bottom-side exposed paddle, the PCB and its copper becomes the primary
heatsink for the Class D amplifier. Solder the exposed
paddle to a copper polygon. Add as much copper as
possible from this polygon to any adjacent pin on the
Class D amplifier as well as to any adjacent components,
provided these connections are at the same potential.
Table 4. Minimum Required Voltage
Ratings for Regulator Bypass Capacitors
CAPACITOR
VOLTAGE RATING (V)
CREGP
VMID + 5
CREGM
VMID - 5
CREGLS
7
CLVDD
5
______________________________________________________________________________________
29
MAX9742
Supply Bypassing/Layout
To maximize output power and minimize distortion,
proper layout and supply bypassing is essential. To
prevent ground-loop-induced noise and minimize noise
due to parasitic ground inductance, use separate
ground planes for input-signal ground connections
(SGND plane) and output-power ground connections
(PGND plane). For dual-supply applications, connect
MID to the SGND plane. For single-supply operation,
connect MID to an external voltage-divider and bypass
MID to the SGND plane with a decoupling network (see
Figure 11). This provides a sufficient low- and high-frequency AC ground for the internal amplifiers. Connect
the SGND and PGND planes together at a single point
in the PCB near the MAX9742. Minimize the parasitic
trace inductances and resistances associated with the
VDD and VSS connections, by using wide traces of minimal length.
Proper power-supply bypassing is essential to ensure
low distortion operation and to prevent excessive supply pumping when using the single-ended output configuration. For dual-supply operation, bypass VDD and
VSS to PGND with 1000µF aluminum electrolytic capacitors. VDD and VSS should also be bypassed to PGND
with 0.1µF capacitors as physically close as possible to
VDD and VSS pins to provide sufficient high-frequency
decoupling. Also, connect an additional 1µF capacitor
between VDD and VSS. For single-supply operation,
bypass VDD to PGND with two 330µF capacitors. VDD
should also be bypassed to PGND with an additional
0.1µF capacitor as physically close as possible to the
VDD pin.
The MAX9742 includes voltage regulators for the internal amplifiers, logic circuitry, and gate-drive circuitry
that require external bypassing. Bypass REGP and
REGM to the SGND plane with 1µF capacitors. Bypass
REGLS to NSENSE with a 1µF capacitor. Bypass LVDD
to LGND with a 0.1µF capacitor. The voltage rating
requirements of the external bypass capacitors must
be taken into account. This is especially important
when selecting the REGP and REGM bypass capacitors since the ground-referenced voltages present at
these regulator outputs are dependent on the voltage
applied to the MID input. The minimum required voltage ratings for the regulator bypass capacitors are
summarized in Table 4.
30
28 N.C.
29 VDD
30 VDD
31 VSS
32 VSS
33 VSS
34 VDD
35 VDD
27
N.C.
2
26
OUTR
3
25
OUTR
4
24
BOOTR
5
23
REGLS
22
NSENSE
7
21
INR+
8
20
INR-
9
19
FBR
1
+
MAX9742
12
13
14
15
16
17
18
REGP
REFCUR
SFT
LGND
LVDD
SHDN
N.C.
6
11
N.C.
OUTL
OUTL
SUB
BOOTL
N.C.
INL+
INLFBL
36 N.C.
TOP VIEW
10
Auxiliary Heatsinking
If operating in higher ambient temperatures, it is possible to improve the thermal performance of a PCB with
the addition of an external heatsink. The thermal resistance to this heatsink must be kept as low as possible
to maximize its performance. With a bottom-side
exposed paddle, the lowest resistance thermal path is
on the bottom of the PCB. The topside of the IC is not a
significant thermal path for the device, and therefore, is
not a cost-effective location for a heatsink. Place the
inductor of the external LC output filter in close proximity to the IC. This not only helps minimize EMI radiation
at the output traces, but also helps draw heat away
from the MAX9742.
Pin Configuration
MID
These copper paths must be as wide as possible. Each
of these paths contributes to the overall thermal capabilities of the system.
The copper polygon to which the exposed paddle is
attached should have multiple vias to the opposite side
of the PCB, where they connect to another copper polygon. Make this polygon as large as possible within the
system’s constraints for signal routing.
Additional improvements are possible if all the traces
from the device are made as wide as possible.
Although the IC pins are not the primary thermal path
out of the package, they do provide a small amount.
The total improvement would not exceed approximately
10%, but it could make the difference between acceptable performance and thermal problems.
REGM
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
TQFN
(6mm × 6mm × 0.8mm)
Chip Information
PROCESS: BCD
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
RF1
CFBL
10V TO 20V
FBL VDD
LEFT NEGATIVE
AUDIO INPUT
LEFT POSITIVE
AUDIO INPUT
CIN
CIN
RIN1
INL-
RIN2
MAX9742
CLASS D
MODULATOR AND
HALF-BRIDGE
INL+
RF2
OUTL
LF
RZBL
CFBL
CF
CZBL
MID
RF2
RIGHT POSITIVE
AUDIO INPUT
RIGHT NEGATIVE
AUDIO INPUT
CIN
RIN2
CIN
RIN1
CFBR
CLASS D
MODULATOR AND
HALF-BRIDGE
INR+
OUTR
LF
RZBL
INRCONTROL LOGIC/
POWER-UP
SEQUENCING
FBR
VSS
CZBL
SFT
SHDN
CFBR
CF
ON
CSFT
-10V TO -20V OFF
RF1
DUAL SUPPLY CONFIGURATION
______________________________________________________________________________________
31
MAX9742
Simplified Block Diagram (continued)
32
CMID1
10µF
R2
10kΩ
R1
10kΩ
VDD
CMID2
10µF
R3
10kΩ
= PGND
RIN1
30.1kΩ
RIN2
30.1kΩ
RIN2
30.1kΩ
RIN1
30.1kΩ
CFBL
150pF
CFBR
150pF
RF2
681kΩ
RF2
681kΩ
CONNECT PGND AND SGND TO
A SINGLE POINT ON THE PCB
NEAR THE MAX9742
CIN
0.47µF
CIN
0.47µF
CIN
0.47µF
= SGND
RIGHT NEGATIVE
AUDIO INPUT
RIGHT POSITIVE
AUDIO INPUT
LEFT POSITIVE
AUDIO INPUT
LEFT NEGATIVE
AUDIO INPUT
CIN
0.47µF
SINGLE-SUPPLY OPERATION
DEVICE CONNECTED FOR AV = 22V/V
20 INR-
VMID - 5V
-
+
17
14
SFT
OPTIONAL
ON
CFBR2
10pF
RF1a
121kΩ
OFF
SHDN
19
VDD
CSFT
0.47µF
15
LGND
5V SUPPLY
7V REGULATOR
(WITH RESPECT
TO VSS)
VSS
4
CVDD
330µF
LVDD 16
NSENSE 22
REGLS 23
BOOTR 24
OUTR 25, 26
REFCUR 13
BOOTL 5
OUTL 2, 3
REGP 12
SUB
CVDD
330µF
29, 30, 34, 35
VMID + 5V
CURRENT
REFERENCE
RF1b
562kΩ
CONTROL LOGIC/
POWER-UP
SEQUENCING
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VDD
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VMID - 5V
VDD
CREGM
1µF
20V TO 40V
5V REGULATOR
(WITH RESPECT TO VMID)
REGM
VSS
-5V REGULATOR
(WITH RESPECT TO VMID)
10
31, 32, 33
FBL
RF1b
562kΩ
9
FBR
VMID - 5V
VMID + 5V
+
-
CFBR1
150pF
21 INR+
11 MID
7 INL+
8 INL-
VMID + 5V
MAX9742
CFBL1
150pF
OPTIONAL
CFBL2
10pF
RF1a
121kΩ
RREF
68kΩ
0.1µF
CLVDD
0.1µF
CREGLS
1µF
DBOOT
1N4148
CBOOT
0.1µF
DBOOT
1N4148
CBOOT
0.1µF
CREGP
1µF
CF
0.33µF
LF
47µH
CF
0.33µF
LF
47µH
RZBL
10Ω
CZBL
0.47µF
RZBL
10Ω
CZBL
0.47µF
COUT
1000µF
COUT
1000µF
8Ω
8Ω
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Application Circuits/Functional Diagrams
______________________________________________________________________________________
= PGND
CFBL1
150pF
CFBR1
150pF
RF2
681kΩ
RF2
681kΩ
CONNECT PGND AND SGND TO
A SINGLE POINT ON THE PCB
NEAR THE MAX9742
CIN
0.47µF
RIN2
30.1kΩ
CIN
0.47µF
RIN1
30.1kΩ
RIN2
30.1kΩ
RIN1
30.1kΩ
CIN
0.47µF
= SGND
RIGHT NEGATIVE
AUDIO INPUT
RIGHT POSITIVE
AUDIO INPUT
LEFT POSITIVE
AUDIO INPUT
LEFT NEGATIVE
AUDIO INPUT
CIN
0.47µF
DUAL-SUPPLY OPERATION
DEVICE CONNECTED FOR AV = 22V/V.
20 INR-
VMID - 5V
-
+
17
14
SFT
OPTIONAL
ON
CFBR2
10pF
RF1a
121kΩ
OFF
SHDN
19
VDD
CSFT
0.22µF
15
LGND
5V SUPPLY
7V REGULATOR
(WITH RESPECT
TO VSS)
VSS
OUTL 2, 3
LVDD 16
NSENSE 22
REGLS 23
BOOTR 24
OUTR 25, 26
REFCUR 13
BOOTL 5
VSS
4
0.1µF
REGP 12
SUB
CVDD
1000µF
29, 30, 34, 35
VMID + 5V
CURRENT
REFERENCE
RF1b
562kΩ
CONTROL LOGIC/
POWER-UP
SEQUENCING
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VDD
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VMID - 5V
VDD
CREGM
1µF
10V TO 20V
RF1b
562kΩ
5V REGULATOR
(WITH RESPECT TO VMID)
REGM
-5V REGULATOR
(WITH RESPECT TO VMID)
10
31, 32, 33
VSS
0.1µF
FBL
CVDD
1000µF
CBYP
1µF
9
FBR
VMID - 5V
VMID + 5V
+
-
CFBR1
150pF
21 INR+
11 MID
7 INL+
8 INL-
VMID + 5V
MAX9742
CFBL1
150pF
-10V TO -20V
CFBL2
10pF
OPTIONAL
RREF
68kΩ
CLVDD
0.1µF
CREGLS
0.1µF
CF
0.33µF
LF
47µH
CF
0.33µF
LF
47µH
DBOOT
1N4148
CBOOT
0.1µF
DBOOT
1N4148
CBOOT
0.1µF
CREGP
1µF
CZBL
0.47µF
RZBL
10Ω
CZBL
0.47µF
RZBL
10Ω
8Ω
8Ω
Typical Application Circuits/Functional Diagrams (continued)
______________________________________________________________________________________
33
MAX9742
RF1a
121kΩ
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
34
CMID1
10µF
R2
10kΩ
R1
10kΩ
VDD
CMID2
10µF
R3
10kΩ
POSITIVE
AUDIO INPUT
NEGATIVE
AUDIO INPUT
= PGND
RF2
681kΩ
RF2
681kΩ
CONNECT PGND AND SGND TO
A SINGLE POINT ON THE PCB
NEAR THE MAX9742
RIN1
30.1kΩ
CIN
0.47µF
= SGND
RIN2
30.1kΩ
RIN2
30.1kΩ
RIN1
30.1kΩ
CIN
0.47µF
CIN
0.47µF
CIN
0.47µF
BRIDGE-TIED-LOAD (BTL), SINGLE-SUPPLY OPERATION
DEVICE CONNECTED FOR AV = 44V/V.
CFBR1
150pF
CFBL1
150pF
20 INR-
VMID - 5V
-
+
17
14
SFT
OPTIONAL
ON
CFBR2
10pF
RF1a
121kΩ
OFF
SHDN
19
VDD
CSFT
0.47µF
15
LGND
5V SUPPLY
7V REGULATOR
(WITH RESPECT
TO VSS)
VSS
4
CVDD
330µF
LVDD 16
NSENSE 22
REGLS 23
BOOTR 24
OUTR 25, 26
REFCUR 13
BOOTL 5
OUTL 2, 3
REGP 12
SUB
CVDD
330µF
29, 30, 34, 35
VMID + 5V
CURRENT
REFERENCE
RF1b
562kΩ
CONTROL LOGIC/
POWER-UP
SEQUENCING
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VDD
VSS
CLASS D
MODULATOR AND
HALF-BRIDGE
VMID - 5V
VDD
CREGM
1µF
20V TO 40V
5V REGULATOR
(WITH RESPECT TO VMID)
REGM
VSS
-5V REGULATOR
(WITH RESPECT TO VMID)
10
31, 32, 33
FBL
RF1b
562kΩ
9
FBR
VMID - 5V
VMID + 5V
+
-
CFBR1
150pF
21 INR+
11 MID
7 INL+
8 INL-
VMID + 5V
MAX9742
CFBL1
150pF
OPTIONAL
CFBL2
10pF
RF1a
121kΩ
RREF
68kΩ
CLVDD
0.1µF
CREGLS
1µF
DBOOT
1N4148
CBOOT
0.1µF
DBOOT
1N4148
CBOOT
0.1µF
CREGP
1µF
0.1µF
CF
0.68µF
LF
22µH
CF
0.68µF
LF
22µH
RZBL
5Ω
CZBL
0.82µF
CZBL
0.82µF
RZBL
5Ω
8Ω
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Application Circuits/Functional Diagrams (continued)
______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
QFN THIN.EPS
______________________________________________________________________________________
35
MAX9742
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9742
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.