FUJITSU SEMICONDUCTOR DATA SHEET 8-bit Proprietary Microcontroller CMOS F2MC-8L MB89560H Series MB89567H/567HC/P568/PV560 ■ DESCRIPTION The MB89560H series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontroller contains a variety of peripheral functions such as I2C interface, timers, 2 ch PWM timers, 8/16-bit timer, 21bit timebase timer, 8 bit PWC timer , 17-bit Watch prescaler, Watch-dog timer, High speed UART, 8-bit SIO, UART/SIO, LCD controller/driver (optional booster), Two type Programmable Pulse Generators (PPG), an A/D converter, and external interrupt. *: F2MC stands for FUJITSU Flexible Microcontroller. ■ FEATURES • • • • • • • • • F2MC-8L family CPU core Low-voltage operation (when an A/D converter is not used) Low current consumption (applicable to the dual-clock system) Minimum execution time: 0.32 µs at 12.5 MHz I2C interface circuit LCD controller/driver : 24 segments x 4 commons (max. 96 pixels, duty LCD mode and Static LCD mode) LCD booster function (option) Wild register (max. 6 different address locations) 10-bit A/D converter: 8 channels (Continued) ■ PACKAGE 80-pin Plastic LQFP (FPT-80P-M05) FPT-80P-M05 80-pin Plastic QFP (FPT-80P-M06) FPT-80P-M06 80-pin Plastic LQFP (FPT-80P-M11) FPT-80P-M11 80-pin Ceramic MQFP (MQP-80C-P01) MQP-80C-P01 MB89560H Series (Continued) • Three types of Serial Interface: High Speed UART (Transfer rate from 300 to 192000 bps /10 MHz main clock) 8-bit Serial I/O (SIO) UART/SIO • Two type of Programmable Pulse Generator(PPG) : 6-bit PPG and 12-bit PPG • Six types of timer 8 bit PWM 2 channels timers 8/16 bit timer/counter (8 bits x 2 channels or 16 bits x 1 channel) 21bit timebase timer 8 bit PWC timer operation Watch prescaler(17 bits) Watch-dog timer • I/O ports: max. 50 channels • External interrupt 1: 8 channels • External interrupt 2 (wake-up function): 4 channels • Low-power consumption modes (stop mode, sleep mode, and watch mode) • LQFP-80 and QFP-80 package • CMOS technology ■ PRODUCT LINEUP Part number MB89P568 MB89PV560 Mass production products (mask ROM products) OTP Piggy-back ROM size 32 K × 8 bits (internal mask ROM) 48 K × 8 bits (internal PROM) 56 K × 8 bits (external ROM) RAM size 1K × 8 bits Parameter Classification MB89567H MB89567HC CPU functions Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Minimum interrupt processing time: : 136 : 8 bits : 1 to 3 bytes : 1, 8, 16 bits : 0.4 µs/10 MHz : 3.6 µs/10 MHz Ports General-purpose I/O ports (N-channel open drain) : 20 pins (2 shared with I2C inputs, 16 shared with LCD, 2 shared with other resources) : 30 pins (shared with resources) : 50 pins General-purpose I/O ports (CMOS) Total 2 1K × 8 bits 21-bit timebase timer 21 bits Interrupt cycle: 211, 213, 216 or 220 tinst *5 Watchdog timer Reset generate cycle: min. 220 tinst for main clock, min. 213 tinst for sub clock Watch prescaler 17 bits Interrupt cycle: 0.50s, 1.00s, 2.00s, 4.00s/32.768 KHz for subclock 8/16-bit timer/ counter Can be operated either as a 2-channel 8-bit timer/counter (Timer 1 and Timer 2, each with its own independent operating clock cycle), or as one 16-bit timer/counter In Timer 1 or 16-bit timer/counter operation, event counter operation (external clock-triggered) and square wave output capable 8-bit PWM 2 ch timer 8-bit interval timer operation (square wave output capable, operating clock cycle: 1, 8, 16, 64 tinst) 8-bit resolution PWM operation (conversion cycle: 256 to 256 x 64 tinst) 8/16-bit timer/counter output for counter clock selectability MB89560H Series Part number Parameter MB89567H MB89567HC MB89P568 MB89PV560 PWC timer 8-bit timer operation (count clock cycle: 1, 4, 32 tinst) 8-bit reload timer operation (toggle output possible, operating clock cycle: 1 - 32 tinst) 8-bit pulse width measurement (continuous measurement possible: High and Low widths, H to H, L to L, period & H at same time and High & rising to rising) 10-bit A/D converter*2 10-bit resolution × 8 channels A/D conversion function (conversion time: 60 tinst) Continuous activation by an 8/16-bit timer/counter output or a timebase timer output capable. 6 bit PPG Internal 6-bit counter Pulse width and cycle are program selectable 12 bit PPG Internal 12-bit counter Pulse width and cycle are program selectable I2C interface*4 Not Available 1 channel Use a 2-wire protocol to communicate with other device High speed UART Transfer data length: 4, 6, 7, 8 bits Transfer rate (300 to 192000 bps /10 MHz main clock) support sub-clock mode UART/SIO Transfer data length: 7, 8 bits for UART, 8 bits for SIO Transfer rate (1201 to 78125 bps / 10 MHz main clock) support sub-clock mode 8-bit serial I/O 8 bits, LSB first/MSB first selectability One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 2, 8, 32 tinst) LCD Common output: 4 (max.) Segment output: 24 (max.) LCD driving power (bias) pins: 4 LCD display RAM size: 12 bytes (24 × 4 bits, max. 96 pixels) Duty LCD mode and Static LCD mode Booster for LCD driving: option Dividing resister for LCD driving: Built-in*1 Wild register Maximum of 6-byte data can be assigned in 6 different address. Used to replace any data in the ROM when specific address and data are assigned in Wild register. Wild register can be set up by using different communication methods through the device. External interrupt 1 (wake-up function) 8 independent channels (interrupt vector, request flag, request output enable) Edge selectability (rising/falling) Used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) External interrupt 2 (wake-up function) 4 channels (“L” level interrupts, independent input enable). Used also for wake-up from stop/sleep mode. (Low-level detection is also permitted in stop mode.) Standby mode Sleep mode, stop mode and clock mode CMOS Process Operating voltage* 3.5 V to 5.5 V 3.5 V to 5.5 V 2.7 to 5.5 V 2.7 to 5.5 V*3 * :Varies with conditions such as the operating frequency. (See “■ Electrical Characteristics.”) *1 : When booster is used, the bias is reduced by 1/3. it can be selected by mask option. *2 : When the A/D converter is used, operating voltage must be 3.5V to 5.5V. *3 : Use MBM27C512-20 as the external ROM (operating voltage: 4.5 V to 5.5 V) *4 : I2C is complied to Intel Corp. System Management Bus Rev. 1.0 specification and to the Philips I2C specification. *5 : 1 tinst = one instruction cycle (execution time) which can be selected as 1/4, 1/8, 1/16, or 1/64 of main clock if main clock mode is selected , or 1/2 of the subclock if subclock mode is selected 3 MB89560H Series ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB89567H MB89567HC MB89P568-101 MB89P568-102 MB89PV560-101 MB89PV560-102 FPT-80P-M05 FPT-80P-M06 FPT-80P-M11 MQP-80C-P01 ■ DIFFERENCES AMONG PRODUCTS 1. Memory Size Before evaluating using the OTPROM (one-time PROM) products, verify its differences from the product that will actually be used. Take particular care on the following points: • The stack area, etc., is set at the upper limit of the RAM. 2. Current Consumption • For the MB89PV560, add the current consumed by the EPROM mounted in the piggy-back socket. • When operating at low speed, the current consumed by the one-time PROM product is greater than for the mask ROM product. However, the current consumption is roughly the same in sleep or stop mode. • (For more information, see “■ Electrical Characteristics.”) 3. Mask Options The functions available as options and the method of specifying options differ between products. Before using options check “■ Mask Options.” 4. Functionalities different between products in MB89560H series Functionalities MB89567H MB89567HC Power-on reset wait time Regulator stab. time + Regulator recovery. time + Osc. stab. time Wait time for external reset in stop/sub/clock mode or wait time for external interrupt trigger recover from main stop mode Regulator recovery time + Osc. stab. time MB89P568 Regulator stab. time + Osc. stab. time Osc. stab. time Osc. stab. time Port pin pullup resistors Selectable by software. Not available. AD conversion time 60 tINST * 33 tINST * I2C noise cancelling circuit — Always available independent of ICCR:DMBP bit selection. Note: For more information on tINST see “■ Electrical Characteristics (4) Instruction cycles" * : Instruction cycle 4 MB89PV560 Not available when ICCR:DMBP bit is asserted. MB89560H Series ■ PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SEG06 SEG05 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC P46/UI/SI1 P45/UO/SO1 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 P44/UCK/SCK1 P43/PWM2/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P07/AN7 P06/AN6 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 RST X0A SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P64/SEG22 P67/SEG23 AVR AVcc (FPT-80P-M05) (FPT-80P-M11) 5 MB89560H Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 FPT-80P-M06 6 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST MB89560H Series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG04 SEG03 SEG02 SEG01 SEG00 COM3 COM2 COM1 COM0 V3 V2 V1 V0 C0 C1 P47/PWC (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 100 99 98 97 96 95 94 *1 93 92 91 90 89 88 87 86 85 110 111 112 81 82 83 84 101 102 103 104 105 106 107 108 109 P46/UI/SI1 P45/UO/SO1 P44/UCK/SCK1 P43/PWM/PPG2 P42/PWM1/EC1 P41/HCK/TO12 P40/WTO/TO11 P31/SDA P30/SCL Vcc P27/INT23 P26/INT22 P25/INT21 P24/INT20 P23/PPG1 P22/SCK P21/SO P20/SI X1 X0 MODA X1A X0A RST P05/AN5 P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 AVss P17/INT17 P16/INT16 P15/INT15 P14/INT14 P13/INT13 P12/INT12 P11/INT11 C P10/INT10 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SEG05 SEG06 SEG07 P50/SEG08 P51/SEG09 P52/SEG10 P53/SEG11 P54/SEG12 P55/SEG13 P56/SEG14 P57/SEG15 P60/SEG16 P61/SEG17 P62/SEG18 Vss P63/SEG19 P64/SEG20 P65/SEG21 P66/SEG22 P67/SEG23 AVR AVcc P07/AN7 P06/AN6 (MQP-80C-P01) *1 :Pin assignment on package top (MB89PV560 only) Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name 81 N.C. 89 AD2 97 N.C. 105 82 A15 90 AD1 98 04 106 OE N.C. 83 A12 91 AD0 99 O5 107 A11 84 AD7 92 N.C. 100 O6 108 A9 85 AD6 93 O1 101 07 109 A8 86 AD5 94 O2 102 O8 110 A13 87 AD4 95 O3 103 CE 111 A14 88 AD3 96 VSS 104 A10 112 VCC N.C.: Internally connected. Do not use. 7 MB89560H Series ■ PIN DESCRIPTION Pin no. LQFP*1 LQFP*2 MQFP*3 QFP*4 Pin name 43 45 X0 44 46 X1 42 44 MODA 39 41 RST 49 to 52 51 to 54 P24/INT20 to P27/INT23 30 to 36 ,38 32 to 38,40 P10/INT10 to P17/INT17 60 61 62 63 P44/UCK/ SCK1 P45/UO/SO1 I/O circuit type Function A Crystal or other resonator connector pins for the main clock. The external clock can be connected to X0. When this is done, be sure to leave X1 open. CR oscillation selectability in model with a mask ROM only. C Memory access mode setting pins. Connect directly to VSS. Hysteresis input type. D Reset I/O pin This pin is a CMOS output type with a pull-up resistor, and a hysteresis input type. “L” is output from this pin by an internal reset request (optional). The internal circuit is initialized by the input of “L”. E General-purpose CMOS I/O ports Also serve as an external interrupt 2 input (wake-up function). External interrupt 2 input is hysteresis input. Selectable pull-up resistor. E General-purpose CMOS I/O ports Also serve as input for external interrupt 1 input. External interrupt 1 input is hysteresis input. Selectable pull-up resistor. E General-purpose CMOS I/O ports Also serve as the clock I/O for the High-speed UART and Serial IO. The peripheral is a hysteresis input type. Selectable pull-up resistor. F General-purpose CMOS I/O ports Also serves as the data output for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. 62 64 P46/UI/SI1 G N-ch open drain general-purpose I/O ports Also serves as the data input for the High-speed UART and Serial I/O. The peripheral is a hysteresis input type. 63 65 P47/PWC G N-ch open drain general-purpose I/O port Also serve as the external clock input for PWC. The peripheral is a hysteresis input. 56 58 P40/WTO/ TO11 F General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output and PWC output. (Continued) *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 8 MB89560H Series (Continued) Pin no. LQFP*1 LQFP*2 57 MQFP*3 QFP*4 59 Pin name P41/HCK/ TO12 I/O circuit type F General-purpose CMOS I/O port Also serves as an 8/16-bit timer/counter output. and half of main clock output Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the data input for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. 45 47 P20/SI E 46 48 P21/SO F 47 49 P22/SCK E 48 50 P23/PPG1 F 54 56 P30/SCL G 55 57 P31/SDA G 65 67 C0 — 64 66 C1 — 59 61 P43/PWM2/ PPG2 F 58 60 P42/PWM1/ EC1 E 21 to 28 23 to 30 P00/AN0 to P07/AN7 J 10 to 12 14 to 18 12 to 14 16 to 20 2 to 9 4 to 11 P60/SEG16 to P67/SEG23 P50/SEG8 to P57/SEG15 Function General-purpose CMOS I/O port Also serves as the data output for the serial I/O. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the clock I/O for the serial I/O. The peripheral is a hysteresis input type. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the 6 bit programmable pulse generator. Selectable pull-up resistor. N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface N-ch open-drain general-purpose I/O port Data I/O pin for I2C interface Function as capacitor connection pin in the products with a booster. Function as capacitor connection pin in the products with a booster. General-purpose CMOS I/O port Also serves PWM wave output for the 8-bit PWM timer 1 and as 12 bit programmable pulse generator output. Selectable pull-up resistor. General-purpose CMOS I/O port Also serves as the PWM wave output and external clock for the 8/16 bit timer counter. Selectable pull-up resistor. General-purpose CMOS I/O ports Also serve as the analog input for the A/D converter. Selectable pull-up resistor. H/I N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. H/I N-ch open-drain general-purpose output ports Also serve as an LCD controller/driver segment output. (Continued) *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 9 MB89560H Series (Continued) Pin no. LQFP*1 LQFP*2 MQFP*3 QFP*4 Pin name I/O circuit type 74 to 80, 1 1 to 3 76 to 80 SEG0 to SEG7 I LCD controller/driver segment output-only pins 70 to 73 72 to 75 COM0 to COM3 I LCD controller/driver common output-only pins 68 to 71 70 to 73 V0 to V3 — LCD driving power supply pins. 42 44 X0A B 43 45 X1A Crystal or other resonator connector pins for the subclock (Subclock: 32.768 kHz) The external clock can be connected to X0A. When this is done, Be sure to leave X1A open. 55 57 Vcc — Power supply pin 39 41 C — Capacitor connection pin *5 15 17 Vss — Power supply (GND) pin 22 24 AVcc — A/D converter power supply pin 21 23 AVR — A/D converter reference voltage input pin 31 33 AVss — A/D converter power supply pin Use this pin at the same voltage as VSS. Function *1: FPT-80P-M05 *2: FPT-80P-M11 *3: MQP-80C-P01 *4: FPT-80P-M06 *5: When MB89PV560-101 or MB89PV560-102 is used, this pin will become a NC pin without internal connection. When MB89P568-101 or MB89P568-102 is used, this pin will be select a regulator stabilization delay time. If 5V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vss. If 3V used in MB89P568-101 or MB89P568-102, this pin must be connected to Vcc. If MB89567H or MB89567HC is used, 0.1µF capacitor should connect to this pin. 10 MB89560H Series ■ PIN DESCRIPTION FOR EXTERNAL EPROM SOCKET (MB89PV560 ONLY) Pin no. Pin name I/O Function 82 83 84 85 86 87 88 89 90 91 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O Address output pins 93 94 95 O1 O2 O3 I Data input pins 96 Vss O Power supply (GND) pin 98 99 100 101 102 O4 O5 O6 O7 O8 I Data input pins 103 CE O ROM chip enable pin Outputs “H” during standby. 104 A10 O Address output pin 105 OE/Vpp O ROM output enable pin Outputs “L” at all times. 107 108 109 A11 A9 A8 O 110 A13 O 111 A14 O 112 Vcc O EPROM power supply pin 81 92 97 106 N.C. — Internally connected pins Be sure to leave them open. Address output pins 11 MB89560H Series ■ I/O CIRCUIT TYPE Type Circuit Remarks X1 N-ch P-ch A P-ch X0 N-ch N-ch Main clock (main clock crystal oscillator) • At an oscillation feedback resistor of approximately 1 MΩ/5.0 V • CR oscillation is selectable (mask products only) X1A N-ch P-ch B P-ch X0A N-ch N-ch C Subclock (subclock crystal oscillator) • At an oscillation feedback resistor of approximately 4.5 MΩ/5.0 V • Hysteresis input R • CMOS output P-ch • Hysteresis input • At an output pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V D N-ch R P-ch Pull up resistor register P-ch E N-ch • CMOS output • CMOS input • The peripheral is a hysteresis input type. • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V Port Peripheral (Continued) 12 MB89560H Series (Continued) Type Circuit R P-ch Remarks Pull up resistor register P-ch F N-ch • CMOS output • CMOS input • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V Port N-ch G Port Peripheral H • N-ch open-drain input/output • CMOS input • The peripheral is a hysteresis input type. • N-ch open-drain output • CMOS input N-ch Port P-ch N-ch • LCD controller/driver common/segment output I P-ch N-ch R P-ch Pull up resistor register P-ch J N-ch ADEN Port Analog input • General CMOS I/O • Analog input (A/D converter) • Selectable pull-up resistor (P-ch) of approximately 50 kΩ/5.0 V • Pull-up resistors must be disabled when used as an analog input). 13 MB89560H Series ■ HANDLING DEVICES 1. Preventing Latchup Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum Ratings” in “■ Electrical Characteristics” is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AV CC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off. 2. Treatment of Unused Input Pins Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor. 3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use. 4. Treatment of N.C. Pins Be sure to leave (internally connected) N.C. pins open. 5. Power Supply Voltage Fluctuations Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched. 6. Precautions when Using an External Clock Even when an external clock is used, oscillation stabilization time is required for power-on reset and wake-up from stop mode. 14 MB89560H Series ■ PROGRAMMING TO THE EPROM ON THE MB89P568 The MB89P568 is an OTPROM version of the MB89567H and MB89567HC. 1. Features • 48-Kbyte PROM on chip • Equivalency to the MBM271001A in EPROM mode (when programmed with the EPROM programmer) 2. Memory Space Memory space in EPROM mode is diagrammed below. Normal operation 0000H I/O 0080H RAM 0480H Not available 4000H EPROM mode (Corresponding addresses on the EPROM programmer 4000H Program area (PROM) FFFFH Program area (PROM) FFFFH 3. Programming to the EPROM In EPROM mode, the MB89P568 functions equivalent to the MBM27C1001A. This allows the PROM to be programmed with a general-purpose EPROM programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. • Programming procedure (1) Set the EPROM programmer to the MBM27C1001A. (2) Load program data into the EPROM programmer at 4000H to FFFFH (3) Program with the EPROM programmer. 15 MB89560H Series 4. Recommended Screening Conditions High-temperature aging is recommended as the pre-assembly screening procedure. Program, verify Aging +150°C, 48 Hrs. Data verification Assembly 5. Programming Yield All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times. 6. EPROM Programmer Socket Adapter Package Compatible socket adapter FPT-80P-M05 ROM-80SQF-32DP-8LA FPT-80P-M06 ROM-80QF-32DP-8LA2 FPT-80P-M11 ROM-80SQF-32DP-8LA Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-3802-5760 16 MB89560H Series ■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE 1. EPROM for Use MBM27C512-20TV 2. Programming Socket Adaptor To program to the PROM using an EPROM programmer, use the socket adaptor (manufacturer: Sun Hayato Co., Ltd.) listed below. Package Adaptor socket part number LCC-32 (Rectangle) ROM-32LC-28DP-YG Inquiry: Sun Hayato Co., Ltd.: TEL 81-3-5396-9106 3. Memory Space Normal operation 0000H (Corresponding addresses on the EPROM programmer) I/O 0080H RAM 0480H Not available 2000H 2000H Program area (PROM) Program area (PROM) FFFFH FFFFH 4. Programming to EPROM (1) Set the EPROM programmer to the MBM27C512. (2) Load program data into the EPROM programmer at 2000H to FFFFH. (3) Program to 2000H to FFFFH with the EPROM programmer. 17 MB89560H Series ■ BLOCK DIAGRAM Oscillator N-ch open drain I/O port Low-power oscillator (32.768 kHz) Watch prescaler 8 8 External interrupt 1 CMOS I/O port 6 bit PPG P24/INT20 to P27/INT23 P20/SI P21/SO P22/SCK 4 Port 2 P23/PPG1 4 External interrupt 2 (wake-up function) 12 bit PPG P42/PWM1/EC1 P41/HCK*1/TO12 P43/PWM2/PPG2 Port 4 *4 8-bit timer/counter 1 (Timer 1) Internal data bus P10/INT10 to P17/INT17 Port 1 21-bit Time-base timer P40/WTO/TO11 PWC Reset circuit (Watchdog timer) RST High-speed UART P46/UI/SI1 8-bit PWM timer 1 CMOS I/O port (P46 and P47 are N-ch Open-diran I/O Type) P47/PWC 4 N-ch open-drain I/O port LCD controller/ driver 8 CMOS I/O port 1K Byte RAM P45/UO/SO1 8-bit PWM timer 2 8 UART/SIO P44/UCK/SCK1 *4 8-bit timer/counter 2 (Timer 2) Port 5 & Port 6 Subclock P31/SDA SIO Clock controller X0A X1A P30/SCL Port 3 I2C*2 Main clock X0 X1 4 4 4 8 Display RAM (12 bytes) 4 4 F2MC-8L CPU 10-bit A/D converter Port 0 8 *1: Output of Main clock/2. *2 : I2C is not available in MB89567 and MB89567H. *3 : Selected by mask option *4 : Can be used as a 16-bit timer/counter by connecting Timer 1 output to Timer 2 input. 18 COM0 to COM3 V0 to V3 Option CMOS I/O port 48K Byte ROM Other pins MODA, C, VCC, VSS SEG0 to SEG7 C0*3 C1*3 Booster Wild register P60/SEG16 to P63/SEG19 P64/SEG20 to P67/SEG23 P50/SEG8 to P53/SEG11 P54/SEG12 to P57/SEG15 8 P00/AN0 to P07/AN7 AVCC AVSS AVR MB89560H Series ■ CPU CORE 1. Memory Space The microcontrollers of the MB89560H series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/ O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. The memory space of the MB89560H series is structured as illustrated below. Memory Space MB89PV560-101,102 0000H MB89P568-101,102 0000H I/O 0080H I/O 0080H RAM 0100H *2 I/O RAM RAM 0100H Registers 0200H 0480H 0492H Access prohibited *2 Registers 0200H 0480H 0492H Access prohibited 2000H MB89567H, MB89567HC 0080H 0100H Registers 0200H 0480H 0492H 0000H *2 Access prohibited 4000H 8000H External*1 ROM FFC0H FFFFH External*1 ROM FFC0H FFFFH ROM FFC0H FFFFH *1: MB89P568-101,102 has OTP ROM inside *2 : Wild register setting registers 19 MB89560H Series 2. Registers The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): A 16-bit register for indicating specifies instruction storage positions. Accumulator (A): A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. Index register (IX): A 16-bit register for index modification Extra pointer (EP): A 16-bit pointer for indicating a memory address Stack pointer (SP): A 16-bit register for indicating a stack area Program status (PS): A 16-bit register for storing a register pointer, a condition code Initial value 16 bits PC : Program counter FFFDH A : Accumulator Undefined T : Temporary accumulator Undefined IX : Index register Undefined EP : Extra pointer Undefined SP : Stack pointer Undefined PS : Program status I-flag = 0, IL1, 0 = 11 Other bits are undefined. The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) 15 PS 14 13 12 10 9 8 Vacancy Vacancy Vacancy RP RP 20 11 7 6 H I 5 4 IL1, 0 3 2 1 0 N Z V C CCR MB89560H Series The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. Rule for Conversion of Actual Addresses of the General-purpose Register Area RP Lower OP codes “0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ b1 b0 ↓ ↓ Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared otherwise. This flag is for decimal adjustment instructions. I-flag: Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0 when reset. IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 IL0 Interrupt level 0 0 0 1 1 0 2 1 1 3 1 High-low High Low = no interrupt N-flag: Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0. Z-flag: Set when an arithmetic operation results in 0. Cleared otherwise. V-flag: Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does not occur. C-flag: Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise. Set to the shift-out value in the case of a shift instruction. 21 MB89560H Series The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers. Up to a total of 32 banks can be used on MB89567H and MB89567HC. The bank currently in use is indicated by the register bank pointer (RP). Register Bank Configuration This address = 0100H + 8 ´ (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks (MB89567H/567HC) Memory area 22 MB89560H Series ■ I/O MAP Address Register name Register Description 00H PDR0 Port 0 data register 01H DDR0 Port 0 data direction register 02H PDR1 Port 1 data register 03H DDR1 Port 1 data direction register 04H - 06H Read/Write Initial value R/W XXXXXXXXB W 00000000B R/W XXXXXXXXB W 00000000B (Vacancy) 07H SYCC System clock control register R/W XXXMM100B 08H STBC Standby control register R/W 00010XXXB 09H WDTC Watchdog timer control register W 0XXXXXXXB 0AH TBTC Timebase timer control register R/W 00XXX000B 0BH WPCR Watch prescaler control register R/W 00XX0000B 0CH PDR2 Port 2 data register R/W XXXXXXXXB 0DH DDR2 Port 2 data direction register R/W 00000000B 0EH PDR3 Port 3 data register R/W XXXXXX11B 0FH PDR4 Port 4 data register R/W XXXXXXXXB 10H DDR4 Port 4 direction register R/W 00000000B 11H PDR5 Port 5 data register R/W 00000000B R/W 00000000B 12H 13H (Vacancy) PDR6 Port 6 data register 14H - 19H (Vacancy) 1AH T2CR Timer2 control register R/W X000XXX0B 1BH T2DR Timer2 data register R/W XXXXXXXXB 1CH T1CR Timer1 control register R/W X000XXX0B 1DH T1DR Timer1 data register R/W XXXXXXXXB UART1 mode control register 1 R/W 00000000B 1EH - 21H (Vacancy) 22H SMC11 23H SRC1 UART1 mode data register R/W XX011000B 24H SSD1 UART1 status/data register R/W 00100X1XB R/W XXXXXXXXB XX100001B 25H SIDR1/SODR1 UART1 data register 26H SMC12 UART1 mode control register 2 R/W 27H CNTR1 PWM control register 1 R/W 00000000B 28H CNTR2 PWM control register 2 R/W 000X0000B 29H CNTR3 PWM control register 3 R/W X000XXXXB 2AH COMR1 PWM compare register 1 W XXXXXXXXB 2BH COMR2 W XXXXXXXXB 2CH PCR1 PWC pulse width control register 1 PWM compare register 2 R/W 000XX000B 2DH PCR2 PWC pulse width control register 2 R/W 00000000B 2EH RLBR PWC reload buffer register R/W XXXXXXXXB 2FH SMC21 UART2/SIO mode control register R/W 00000000B 30H SMC22 UART2/SIO mode control register 2 R/W 00000000B (Continued) 23 MB89560H Series (Continued) Address 31H 32H Register name SSD2 Register Description UART2/SIO status/data register SIDR2/SODR2 UART2/SIO data register Read/Write Initial value R/W 00001XXXB R/W XXXXXXXXB 33H SRC2 UART2/SIO rate control register R/W XXXXXXXXB 34H ADC1 A/D control register 1 R/W X00000X0B 35H ADC2 A/D control register 2 R/W X0000001B 36H ADDL A/D data register L R/W XXXXXXXXB 37H ADDH A/D data register H R/W XXXXXXXXB 38H RCR21 PPG control register 1(PPG2) R/W 00000000B 39H RCR23 PPG control register 2(PPG2) R/W 0X000000B 3AH RCR22 PPG control register 3(PPG2) R/W XX000000B 3BH RCR24 PPG control register 4(PPG2) R/W XX000000B 3CH - 3EH (Vacancy) 3FH EIC1 External interrupt 1 control register 1 R/W 00000000B 40H EIC2 External interrupt 1 control register 2 R/W 00000000B 41H EIC3 External interrupt 1 control register 3 R/W 00000000B 42H EIC4 External interrupt 1 control register 4 R/W 00000000B 2 R 00000000B 2 43H - 50H (Vacancy) 51H IBSR 52H IBCR I C bus control register R/W 00000000B 53H ICCR I2C clock control register R/W 000XXXXXB 54H IADR I2C address register R/W XXXXXXXXB I C bus status register 2 55H IDAR I C data register R/W XXXXXXXXB 56H EIE2 External interrupt 2 enable register R/W XXXX0000B 57H EIF2 External interrupt 2 flag register R/W XXXXXXX0B 58H RCR1 PPG control register 1(PPG1) R/W 00000000B 59H RCR2 PPG control register 2(PPG1) R/W 0X000000B 5AH CKR Clock Output control register R/W 00000000B 5BH LCR1 LCD controller/driver control register 1 R/W 00010000B 5CH LCR2 LCD controller/driver control register 1 R/W 00000000B 5DH LCR3 LCD controller/driver control register 1 R/W XX000000B 5EH LDR1 LCD data register 1 R/W XXXXXXXXB 60H - 6FH VRAM Display RAM R/W XXXXXXXXB 70H SMR Serial I/O mode register R/W 00000000B 71H SDR Serial I/O data register R/W XXXXXXXXB 72H PURR0 Pull-up resister register 0 R/W 11111111B 73H PURR1 Pull-up resister register 1 R/W 11111111B 74H PURR2 Pull-up resister register 2 R/W 11111111B 75H PURR4 Pull-up resister register 4 R/W XX111111B 5FH 76H (Vacancy) (Vacancy) (Continued) 24 MB89560H Series (Continued) Address Read/Write Initial value 77H Register name WREN Wild register enable register Register Description R/W XX000000B 78H WROR Wild register data test register R/W XX000000B 79H ADEN A/D port input enable register R/W 11111111B 7AH (Vacancy) 7BH ILR1 Interrupt level setting register 1 W 11111111B 7CH ILR2 Interrupt level setting register 2 W 11111111B 7DH ILR3 Interrupt level setting register 3 W 11111111B 7EH ILR4 Interrupt level setting register 4 W 11111111B Access Prohibited 11111111B 7FH ITR Interrupt test register ■ EXTEND I/O MAP Address Register name Register description Read/Write Initial value 480H WRARH1 Wild register high-byte address register1 R/W XXXXXXXXB 481H WRARL1 Wild register low-byte address register1 R/W XXXXXXXXB 482H WRDR1 Wild register data register1 R/W XXXXXXXXB 483H WRARH2 Wild register high-byte address register2 R/W XXXXXXXXB 484H WRARL2 Wild register low-byte address register2 R/W XXXXXXXXB 485H WRDR2 Wild register data register2 R/W XXXXXXXXB 486H WRARH3 Wild register high-byte address register3 R/W XXXXXXXXB 487H WRARL3 Wild register low-byte address register3 R/W XXXXXXXXB 488H WRDR3 Wild register data register3 R/W XXXXXXXXB 489H WRARH4 Wild register high-byte address register4 R/W XXXXXXXXB 48AH WRARL4 Wild register low-byte address register4 R/W XXXXXXXXB 48BH WRDR4 Wild register data register4 R/W XXXXXXXXB 48CH WRARH5 Wild register high-byte address register5 R/W XXXXXXXXB 48DH WRARL5 Wild register low-byte address register5 R/W XXXXXXXXB 48EH WRDR5 Wild register data register5 R/W XXXXXXXXB 48FH WRARH6 Wild register high-byte address register6 R/W XXXXXXXXB 490H WRARL6 Wild register low-byte address register6 R/W XXXXXXXXB 491H WRDR6 Wild register data register6 R/W XXXXXXXXB ● Read/write access symbols R/W: Readable and writable R: Read-only W: Write-only ● Initial value symbols 0: The initial value of this bit is “0”. 1: The initial value of this bit is “1”. X: The initial value of this bit is undefined. M: The initial value of this bit is determined by mask option. Note:Do not use vacancies. 25 MB89560H Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (AVSS = VSS = 0.0 V) Parameter Symbol Value Unit Remarks Min. Max. VCC AVCC VSS – 0.3 VSS + 6.0 V AVR VSS – 0.3 VSS + 6.0 V Program voltage VPP VSS – 0.6 VSS +13.0 V Only for the MB89P568 Input voltage VI VSS – 0.3 VCC + 0.3 V For pins other than P30 and P31 VSS – 0.3 VSS + 6.0 V For P30 and P31 Output voltage VO VSS – 0.3 VCC + 0.3 V For pins other than P30 and P31 VSS – 0.3 VSS + 6.0 V For P30 and P31 “H” level maximum output current IOL 15 mA “L” level average output current IOLAV 4 mA “L” level total maximum output current ∑IOL 100 mA “L” level total average output current ∑IOLAV 40 mA “H” level maximum output current IOH –15 mA “H” level average output current IOHAV –4 mA “H” level total maximum output current ∑IOH –50 mA “H” level total average output current ∑IOHAV –20 mA Power consumption PD 300 mW Operating temperature TA –40 +85 °C Storage temperature Tstg –55 +150 °C Power supply voltage MB89567H, MB89567HC, MB89P568 and MB89PV560 Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) Average value (operating current × operating rate) * : Use AVCC and VCC set at the same voltage. Take care so that AVR and AVCC + 0.3V does not exceed VCC, such as when power is turned on. Precautions: Permanent device damage may occur if the above “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 26 MB89560H Series 2. Recommended Operating Conditions (AVSS = VSS = 0.0 V) Symbol Parameter VCC AVCC Power supply voltage Value Unit Remarks Min. Max. 3.5* 5.5* V For MB89567H and MB89567HC 3.0 5.5 V Retains the RAM state in stop mode for MB89567H and MB89567HC 2.7* 5.5* V For MB89PV560 and MB89P568 1.5 5.5 V Retains the RAM state in stop mode for MB89PV560 and MB89P568 A/D converter reference input voltage AVR 3.5 AVCC V Operating temperature TA –40 +85 °C * : These values depend on the operating conditions and the analog assurance range. See Figure 1, Figure 2, Figure 3 and “5. A/D Converter Electrical Characteristics.” : MB89P568, MB89PV560 Operating Voltage (V) : MB89567H, MB89P567HC A/D Converter accuracy assurance range : Vcc = AVcc =3.5V~5.5V 5.5 5.0 Operation assurance range 4.0 3.5 3.0 2.7 2.0 Main clock operating Freq. (MHz) 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 12.0 11.0 12.5 Min execution time (inst. cycle) (µs) 4.0 2.0 Figure 1 0.8 0.4 0.32 Operating Voltage vs. Main Clock Operating Frequency 27 MB89560H Series 3. DC Characteristics Parameter “H” level input voltage Symbol Pin (AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Value Condition Unit Remarks Min. Typ. Max. VIH P00 to P07, P10 to P17, P20 to P27, P30 to P37 P40 to P45 — 0.7 VCC — VCC + 0.3 V VIHS RST, MODA INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC — 0.8 VCC — VCC + 0.3 V — VSS +1.4 — VSS + 5.5 V SMB input buffer selected — 0.7 VCC — VCC + 0.3 V I2C input buffer selected VIHSMB SDL, SDA VIHI2C “L” level input voltage VIL P00 to P07, P10 to P17, P20 to P27, P40 to P45 — VSS − 0.3 — 0.3 VCC V VILS RST, MODA INT10 to INT17, INT20 to INT23, SI,SCK,EC1,UCK, SCK1,UI,SI1,PWC — VSS − 0.3 — 0.2 VCC V — VSS - 0.3 — VSS + 0.6 V SMB input buffer selected — VSS − 0.3 — 0.3 VCC V I2C input buffer selected P60 to P67 P50 to P57 P46, P47 P30, P31 — VSS − 0.3 — VCC + 0.3 V P00 to P07, P10 to P17, P40 to P45 IOH = –2.0 mA 4.0 — — V — — 0.4 V VILSMB SCL, SDA VILI2C Open-drain output pin application voltage “H” level output voltage “L” level output voltage VD VOH P20 to P27 VOL P00 to P07, P10 to P17, P30 to P31, P40 to P47, P50 to P57, P60 to P67, RST P20 to P27 IOH = –15.0 mA IOL = 4.0 mA IOL = 15.0 mA (Continued) 28 MB89560H Series (Continued) (AVCC = VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Value Unit Remarks Min. Typ. Max. — 15 20 6 10 MB89567H MB89567HC 5 8.5 MB89PV560 MB89P568 1.5 3 MB89567H MB89567HC — 5 7 MB89PV560 MB89P568 — 2 4 MB89567H MB89567HC — 1.5 3 MB89PV560 MB89P568 — 1 2 FCL = 32.768 kHz VCC = 5.0 Subclock mode — 3 7 mA MB89PV560 MB89P568 — 20 50 µA MB89567H MB89567HC FCL = 32.768 kHz VCC = 5.0 V Subclock sleep mode — 30 50 — 15 30 ICCT FCL = 32.768 kHz VCC = 3.0 V • Watch mode • Main clock stop mode — 5 15 µA ICCH TA = +25°C • Subclock stop mode — 3 10 µA IA FCH = 10.0 MHz, — 4 6 mA when A/D conversion is activated FCH = 10.0 MHz, TA = +25°C, — 1 5 µA when A/D conversion is stopped FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 0.4 µs Main clock run mode ICC1 FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 6.4 µs Main clock run mode ICC2 FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 0.4 µs Main clock sleep mode ICCS1 ICCS2 VCC ‘ Power supply current Condition ICCL ICCLS FCH = 10.0 MHz VCC = 5.0 V tinst*3 = 6.4 µs Main clock sleep mode — — — MB89PV560 MB89P568 mA mA mA mA µA AVCC IAH MB89567H MB89567HC MB89PV560 MB89P568 MB89567H MB89567HC (Continued) 29 MB89560H Series (Continued) (AVCC = VCC = 5.0V, , AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Input leakage current Symbol ILI Pin P00 to P07, P10 to P17, P20 to P27, P40 to P45, P50 to P57, P60 to P67 Condition 30 P30, P32 P46, P47 Pull-up resistance RPULL P00 to P07, P10 to P17, P20 to P27, P30 to P31, P40 to P45, RST LCD divided resistance RLCD — Unit Min. Typ. Max. -5 — +5 µA -10 — +10 µA — — +5 µA 0.0V < VI < VCC MODA Open-drain output ILIOD leakage current Value 0.0V < VI < Vss + 5.5V VI = 0.0 V 25 50 100 kΩ Between VCC and VSS 300 500 750 kΩ — — 2.5 kΩ — — 15 kΩ — — +1 µA — 10 — pF COM0 to COM3 RVCOM output impedance COM0 to 3 SEG0 to 23 output RVSEG impedance SEG0 to 23 LCD controller/ driver leakage current ILCDL V0 to V3, COM0 to 3 SEG0 to 23 Input capacitance CIN Other than AVCC, AVSS, VCC, f = 1 MHz and VSS V1 to V3 = 5.0V — Remarks Without pull-up Resister When pullup resistor selected except RST MB89560H Series 4. AC Characteristics (1) Reset Timing (VCC = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter RST “L” pulse width Value Condition tZLZH — Min. Max. 48 tHCYL* — Unit Remarks ns * : tHCYL is the oscillation cycle (1/FC) to input to the X0 pin. tZLZH RST 0.2 VCC 0.2 VCC (2) Power-on Reset (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Power supply rising time tR Power supply cut-off time tOFF Condition — Value Unit Min. Max. 0.5 50 ms 1 — ms Remarks Due to repeated operations Note: Make sure that power supply rises within the selected oscillation stabilization time. For example, when the main clock is operating at 10 MHz (FCH) and the oscillation stabilization time select option has been set to 218/FCH, the oscillation stabilization delay time is 26.2 ms. Therefore, the maximum value of power supply rising time is about 26.2 ms. Rapid changes in power supply voltage may cause a power-on reset. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. tR tOFF 3.5 V VCC 0.2 V 0.2 V 0.2 V 31 MB89560H Series (3) Clock Timing (AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rising/falling time Value Pin Min. Typ. Max. Unit FCH X0, X1 1 — 12.5 MHz Main clock FCL X0A, X1A — 32.768 — kHz Subclock tHCYL X0, X1 80 — 1000 ns Main clock tLCYL X0A, X1A — 30.5 — µs Subclock PWH PWL X0 20 — — ns External clock PWH PWL X0A — 15.2 — µs External clock tCR tCF X0 — — 10 ns External clock X0 and X1 Timing and Conditions tHCYL PWH PWL tCR tCF 0.8 VCC 0.8 VCC X0 0.2 VCC 0.2 VCC 0.2 VCC Main Clock Conditions When a crystal or ceramic reasonator is used X0 When an external clock is used X1 X0 X1 Open FCH C1 32 Remarks C2 FCH MB89560H Series X0A and X1A Timing and Conditions tLCYL PWLL PWLH tCR tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC Subclock Conditions When a crystal or ceramic reasonator is used X0A When an external clock is used X0A X1A X1A Open FCL FCL C1 C2 (4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value Unit 4/FCH, 8/FCH, 16/FCH, 64/FCH µs tinst = 0.32µs when operating at FCH = 12.5 MHz (4/FCH) 2/FCL µs tinst = 61.036 µs when operating at FCL = 32.768 kHz tinst Remarks 33 MB89560H Series (5) Serial I/O Timing (Vcc = 5.0V, AVSS = VSS= 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Condition Serial clock cycle time tSCYC SCK, SCK1, UCK SCK ↓ → SO time tSLOV SCK, SO, SCK1, SO1, UCK, UO Valid SI → SCK ↑ tIVSH SI, SCK, SI1, SCK1, UI, UCK SCK ↑ → valid SI hold time tSHIX SCK, SI, SCK1, SI1, UCK, UI Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCK ↓ → SO time tSLOV SCK, SO, SCK1, SO1, UCK, UO Valid SI → SCK ↑ tIVSH SI, SCK, SI1, SCK1, UI, UCK SCK ↑ → valid SI hold time tSHIX SCK, SI, SCK1, SI1, UCK, UI Internal shift clock mode SCK, SCK1, UCK External shift clock mode Value Max. 2 tinst* — µs –200 200 ns 200 — ns 200 — ns 1 tinst* — µs 1 tinst* — µs 0 200 ns 200 — ns 200 — ns * : For information on tinst, see “(4) Instruction Cycle.” Internal Shift Clock Mode tSCYC SCK SCK1 UCK 2.4 V 0.8 V 0.8 V tSLOV SO SO1 UO 2.4 V 0.8 V tIVSH SI SI1 U1 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC External Shift Clock Mode tSLSH SCK SCK1 UCK tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV SO SO1 UO 2.4 V 0.8 V tIVSH SI SI1 UI 34 tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC Unit Min. Remarks MB89560H Series (6) Peripheral Input Timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Peripheral input “H” pulse width 1 tILIH1 Peripheral input “L” pulse width 1 tIHIL1 Pin Condition INT10 to INT17, INT20 to INT23, EC, PWC — Value Unit Remarks Min. Max. 2 tinst* — µs 2 tinst* — µs * : For information on tinst, see “(4) Instruction Cycle.” t IHIL1 INT10 to 17, INT20 to INT23 EC, PWC t ILIH1 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC 35 MB89560H Series (7) I2C timing (Vcc = 5.0V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Symbol Parameter Pin Value Condition Min. Max. Unit Start condition output tSTA SCL SDA 1/4tINST x m x n - 20 1/4tINST x m x n + 20 ns master mode Stop condition output tSTO SCL SDA 1/4tINST x (m x n + 8) - 20 1/4tINST x (m x n + 8) + 20 ns master mode Start condition detect tSTA SCL SDA 1/4tINST x 6 + 40 — ns Stop condition detect tSTO SCL SDA 1/4tINST x 6 + 40 — ns Re-start condition output tSTASU SCL SDA 1/4tINST x (m x n + 8) - 20 1/4tINST x (m x n + 8) + 20 ns Re-start condition detect tSTASU SCL SDA 1/4tINST x 4 + 40 — ns SCL output LOW width tLOW SCL 1/4tINST x m x n - 20 1/4tINST x m x n + 20 ns master mode SCL output HIGH width tHIGH SCL 1/4tINST x (m x n + 8) - 20 1/4tINST x (m x n + 8) + 20 ns master mode SDA output delay tDO SDA 1/4tINST x 4 - 20 1/4tINST x 4 + 20 ns SDA output setup time after interrupt tDOSU SDA 1/4tINST x 4 - 20 — ns SCL input LOW pulse width tLOW SCL 1/4tINST x 6 + 40 — ns SCL input HIGH pulse width tHIGH SCL 1/4 tINST x 2 + 40 — ns SDA input setup time tSU SDA 40 — ns SDA hold time SDA 0 — ns tHO • For information in tINST, see "(4) Instruction Cycle". • m is defined in the ICCR CS4 and CS3 (bit 4 to bit 3) • n is defined in the ICCR CS2 to CS0 (bit 2 to bit 0) Data transmit (master/slave) tDO tSU tDO SDA tHO tDOSU ACK tSTASU tSTA tLOW tHO SCL 1 9 Data receive (master/slave) tSU tHO tDO SDA SCL tDO tDOSU ACK tHIGH 36 Remarks 6 7 tLOW tSTO 8 9 master mode MB89560H Series 5. A/D Converter Electrical Characteristics (1) For MB89567H A/D Converter (AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Resolution Condition Max. — — 10 bit — — ±5.0 LSB — — ±2.5 LSB 1LSB = AVR/1024 — — ±1.9 LSB AVR 3.5 LSB AVR + 0.5 LSB AVR + 4.5 LSB mV AVR – 6.5 LSB AVR – 1.5 LSB AVR + 1.5 LSB mV — — 4 — 60 tinst*1 — — 16 tinst*1 — — — 10 µA AVss — AVR V AVss+3.5 — AVCC V A/D is Activated — 400 — µA A/D is Stopped — — 5 µA — Differential linearity error AVR=AVCC Full-scale transition voltage — VFST Interchannel disparity A/D mode conversion time *3 — A/D Sampling time Analog port input current IAIN Analog input voltage VAIN Reference voltage Reference voltage supply current AN0 to AN7 — — IR IRH AVR Remarks Typ. Total error Zero transition voltage VOT Unit Min. — Non-linearity error Value LSB 1LSB = AVR/1024 µs *2 * : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” * : 2 When A/D conversion is not in operation, and the CPU is in STOP mode. * : 3 Included sampling time 37 MB89560H Series (2) For MB89P568 A/D Converter (AVcc=3.5~5.5V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C) Parameter Symbol Pin Resolution Condition Max. — — 10 bit — — ±3.0 LSB — — ±2.5 LSB 1LSB = AVR/1024 — — ±1.9 LSB AVR 1.5 LSB AVR + 0.5 LSB AVR + 2.5 LSB mV AVR – 3.5 LSB AVR – 1.5 LSB AVR + 1.5 LSB mV — — 4 — 60 tinst*1 — — 16 tinst*1 — — — 10 µA AVss — AVR V AVss+3.5 — AVCC V A/D is Activated — 400 — µA A/D is Stopped — — 5 µA — Differential linearity error AVR=AVCC Full-scale transition voltage — VFST Interchannel disparity A/D mode conversion time *3 — A/D Sampling time Analog port input current IAIN Analog input voltage VAIN Reference voltage Reference voltage supply current AN0 to AN7 — — IR IRH AVR * : 1 For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.” * : 2 When A/D conversion is not in operation, and the CPU is in STOP mode. * : 3 Included sampling time *: 38 Remarks Typ. Total error Zero transition voltage VOT Unit Min. — Non-linearity error Value LSB 1LSB = AVR/1024 µs *2 MB89560H Series (3) Precautions • The smaller the | AVR–AVSS |, the greater the error would become relatively. • The output impedance of the external circuit for the analog input must satisfy the following conditions: Output impedance of the external circuit < Approx. 10 kΩ • If the output impedance of the external circuit is too high, an analog voltage sampling time might be insufficient (sampling time = 6 µs at 10MHz oscillation.) Analog Input Circuit Model Sample hold circuit . C =. 33 pF Analog input pin Comparator If the analog input impedance is higher than 10 kW, it is recommended to connect an external capacitor of approx. 0.1 mF. . R =. 6 kW Close for 8 instruction cycles after activating A/D conversion. Analog channel selector (4) A/D Converter Glossary • Resolution Analog changes that are identifiable with the A/D converter. • Linearity error The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics • Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value • Total error (unit: LSB) The difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise Theoretical I/O characteristics 3FF Total error 3FF VFST 3FE 3FE 3FD 1.5 LSB Digital output Digital output 3FD 004 003 Actual conversion value {1 LSB × N + 0.5 LSB} 004 VNT 003 VOT 002 Actual conversion value 002 1 LSB Theoretical value 001 001 0.5 LSB AVR AVSS Analog input 1 LSB = VFST – VOT 1022 AVR AVSS Analog input (V) Digital output N total error = VNT – {1 LSB × N + 0.5 LSB} 1 LSB (Continued) 39 MB89560H Series (Continued) Zero transition error Full-scale transition error 004 Theoretical value Actual conversion value 3FF Actual conversion value Digital output Digital output 003 002 3FE VFST (Actual measurement) 3FD Actual conversion value 001 Actual conversion value 3FC VOT (Actual measurement) AVR AVSS Analog input Analog input Differential linearity error Linearity error 3FF Theoretical value Actual conversion value 3FE N+1 {1 LSB × N + VOT} Actual conversion value VNT VFST (Actual measurement) 004 Digital output Digital output 3FD V(N + 1)T N N–1 003 VNT Actual conversion value Actual conversion value 002 Theoretical value 001 N–2 VOT (Actual measurement) AVR AVSS Analog input Digital output N linearity error = 40 VNT – {1 LSB × N + VOT} 1 LSB AVR AVSS Analog input Digital output N differential linearity error = V(N + 1)T – VNT 1 LSB –1 MB89560H Series ■ INSTRUCTIONS Execution instructions can be divided into the following four groups: • • • • Transfer Arithmetic operation Branch Others Table 1 lists symbols used for notation of instructions. Table 1 Instruction Symbols Symbol Meaning dir Direct address (8 bits) off Offset (8 bits) ext Extended address (16 bits) #vct Vector table number (3 bits) #d8 Immediate data (8 bits) #d16 Immediate data (16 bits) dir: b Bit direct address (8:3 bits) rel Branch relative address (8 bits) @ Register indirect (Example: @A, @IX, @EP) A Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) AH Upper 8 bits of accumulator A (8 bits) AL Lower 8 bits of accumulator A (8 bits) T Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) TH Upper 8 bits of temporary accumulator T (8 bits) TL Lower 8 bits of temporary accumulator T (8 bits) IX Index register IX (16 bits) (Continued) 41 MB89560H Series (Continued) Symbol Meaning EP Extra pointer EP (16 bits) PC Program counter PC (16 bits) SP Stack pointer SP (16 bits) PS Program status PS (16 bits) dr Accumulator A or index register IX (16 bits) CCR Condition code register CCR (8 bits) RP Register bank pointer RP (5 bits) Ri General-purpose register Ri (8 bits, i = 0 to 7) × Indicates that the very × is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (×) Indicates that the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) (( × )) The address indicated by the contents of × is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Columns indicate the following: Mnemonic: Assembler notation of an instruction ~: Number of instructions #: Number of bytes Operation: Operation of an instruction TL, TH, AH: A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: • “–” indicates no change. • dH is the 8 upper bits of operation description data. • AL and AH must become the contents of AL and AH immediately before the instruction is executed. • 00 becomes 00. N, Z, V, C: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. OP code: Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F ← This indicates 48, 49, ... 4F. 42 MB89560H Series Table 2 Transfer Instructions (48 instructions) Mnemonic ~ # Operation TL TH AH NZVC OP code MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 – – – – – AL AL AL AL AL AL AL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –––– –––– –––– –––– –––– ++–– ++–– ++–– ++–– ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off 5 4 2 3 4 5 3 1 1 3 2 2 – – – AL AL AL – – – AH AH AH – – – dH dH dH –––– –––– –––– ++–– ++–– ++–– D4 D7 E3 E4 C5 C6 MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ← (A) ( (IX) +off ) ← (A) (ext) ← (A) ( (EP) ) ← (A) (Ri) ← (A) (A) ← d8 (A) ← (dir) (A) ← ( (IX) +off) (A) ← (ext) (A) ← ( (A) ) (A) ← ( (EP) ) (A) ← (Ri) (dir) ← d8 ( (IX) +off ) ← d8 ( (EP) ) ← d8 (Ri) ← d8 (dir) ← (AH),(dir + 1) ← (AL) ( (IX) +off) ← (AH), ( (IX) +off + 1) ← (AL) (ext) ← (AH), (ext + 1) ← (AL) ( (EP) ) ← (AH),( (EP) + 1) ← (AL) (EP) ← (A) (A) ← d16 (AH) ← (dir), (AL) ← (dir + 1) (AH) ← ( (IX) +off), (AL) ← ( (IX) +off + 1) (AH) ← (ext), (AL) ← (ext + 1) (AH) ← ( (A) ), (AL) ← ( (A) ) + 1) (AH) ← ( (EP) ), (AL) ← ( (EP) + 1) (A) ← (EP) (EP) ← d16 (IX) ← (A) (A) ← (IX) (SP) ← (A) (A) ← (SP) ( (A) ) ← (T) ( (A) ) ← (TH),( (A) + 1) ← (TL) (IX) ← d16 (A) ← (PS) (PS) ← (A) (SP) ← d16 (AH) ↔ (AL) (dir): b ← 1 (dir): b ← 0 (AL) ↔ (TL) (A) ↔ (T) (A) ↔ (EP) (A) ↔ (IX) (A) ↔ (SP) (A) ← (PC) AL AL AL – – – – – – – – – – – – – – – AL AL – – – – AH AH AH – – – – – – – – – – – – – – – – AH – – – – dH dH dH dH – – dH – dH – – – dH – – AL – – – dH dH dH dH dH ++–– ++–– ++–– –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– ++++ –––– –––– –––– –––– –––– –––– –––– –––– –––– –––– C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0 Notes: • During byte transfer to A, T ← A is restricted to low bytes. • Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F 2MC-8 family) 43 MB89560H Series Table 3 Mnemonic ~ # ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ROLC A 2 1 CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation TL TH AH NZVC OP code (A) ← (A) + (Ri) + C (A) ← (A) + d8 + C (A) ← (A) + (dir) + C (A) ← (A) + ( (IX) +off) + C (A) ← (A) + ( (EP) ) + C (A) ← (A) + (T) + C (AL) ← (AL) + (TL) + C (A) ← (A) − (Ri) − C (A) ← (A) − d8 − C (A) ← (A) − (dir) − C (A) ← (A) − ( (IX) +off) − C (A) ← (A) − ( (EP) ) − C (A) ← (T) − (A) − C (AL) ← (TL) − (AL) − C (Ri) ← (Ri) + 1 (EP) ← (EP) + 1 (IX) ← (IX) + 1 (A) ← (A) + 1 (Ri) ← (Ri) − 1 (EP) ← (EP) − 1 (IX) ← (IX) − 1 (A) ← (A) − 1 (A) ← (AL) × (TL) (A) ← (T) / (AL),MOD → (T) (A) ← (A) ∧ (T) (A) ← (A) ∨ (T) (A) ← (A) ∀ (T) (TL) − (AL) (T) − (A) → C→A – – – – – – – – – – – – – – – – – – – – – – – dL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 00 – – – – – – – – – – – dH – – – – – – dH – – – – dH – – – dH dH 00 dH dH dH – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++– –––– –––– ++–– +++– –––– –––– ++–– –––– –––– ++R– ++R– ++R– ++++ ++++ ++–+ 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 C ← A← – – – ++–+ 02 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65 (A) − d8 (A) − (dir) (A) − ( (EP) ) (A) − ( (IX) +off) (A) − (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) ← (AL) ∀ (TL) (A) ← (AL) ∀ d8 (A) ← (AL) ∀ (dir) (A) ← (AL) ∀ ( (EP) ) (A) ← (AL) ∀ ( (IX) +off) (A) ← (AL) ∀ (Ri) (A) ← (AL) ∧ (TL) (A) ← (AL) ∧ d8 (A) ← (AL) ∧ (dir) (Continued) 44 MB89560H Series (Continued) Mnemonic ~ # AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) ← (AL) ∧ ( (EP) ) (A) ← (AL) ∧ ( (IX) +off) (A) ← (AL) ∧ (Ri) (A) ← (AL) ∨ (TL) (A) ← (AL) ∨ d8 (A) ← (AL) ∨ (dir) (A) ← (AL) ∨ ( (EP) ) (A) ← (AL) ∨ ( (IX) +off) (A) ← (AL) ∨ (Ri) (dir) – d8 ( (EP) ) – d8 ( (IX) + off) – d8 (Ri) – d8 (SP) ← (SP) + 1 (SP) ← (SP) – 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ # 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI ~ # 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++R– ++++ ++++ ++++ ++++ –––– –––– 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1 Branch Instructions (17 instructions) Operation If Z = 1 then PC ← PC + rel If Z = 0 then PC ← PC + rel If C = 1 then PC ← PC + rel If C = 0 then PC ← PC + rel If N = 1 then PC ← PC + rel If N = 0 then PC ← PC + rel If V ∀ N = 1 then PC ← PC + rel If V ∀ N = 0 then PC ← PC + reI If (dir: b) = 0 then PC ← PC + rel If (dir: b) = 1 then PC ← PC + rel (PC) ← (A) (PC) ← ext Vector call Subroutine call (PC) ← (A),(A) ← (PC) + 1 Return from subrountine Return form interrupt Table 5 TL TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – dH – – –––– –––– –––– –––– –––– –––– –––– –––– –+–– –+–– –––– –––– –––– –––– –––– –––– Restore FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30 Other Instructions (9 instructions) Operation TL TH AH NZVC OP code – – – – – – – – – – – – – – – – – – – dH – – – – – – – –––– –––– –––– –––– –––– –––R –––S –––– –––– 40 50 41 51 00 81 91 80 90 45 46 MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel 8 9 A B C D E F A A A SUBC A XCH A, T XOR A AND A OR ADDC A,@IX +d SUBC A,@IX +d MOV @IX +d,A A A AND XOR @A,IX A,@IX +d +d OR A,@IX +d CMP @EP,#d 8 DAS R7 R6 R5 R4 R3 R2 R1 R0 DEC DEC DEC DEC DEC DEC DEC DEC R7 R6 R5 R4 R3 R2 R1 R0 rel rel rel rel rel CALLV BLT #7 rel CALLV BGE #6 rel CALLV BZ #5 CALLV BNZ #4 CALLV BN #3 CALLV BP #2 CALLV BC #1 CALLV BNC #0 rel CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX XOR AND OR DAA A,#d8 A,#d8 A,#d8 ADDCW SUBCW XCHW XORW ANDW ORW A A A, T A A ADDC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d 8 CMP A,@IX +d CMPW CMP SETC 7 F MOVW XCHW MOVW CLRB BBC MOVW CMP MOV A,IX @IX IX,#d16 dir: 6 dir: 6,rel A,@IX @IX @IX +d,A +d +d,#d8 +d,#d8 E MOV A,@IX +d D 6 C MOV CMP ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP B CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC A 5 A A JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A SETI 9 MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8 8 4 7 RORC 6 3 A 5 PUSHW POPW MOV MOVW CLRI A A A,ext A,PS 4 ROLC DIVU RETI 3 2 A RET 2 MULU SWAP 1 1 0 NOP H 0 L MB89560H Series ■ INSTRUCTION MAP MB89560H Series ■ MASK OPTION Model NO. Specification method MB89567H MB89567HC MB89P568 Specify when ordering mask. Setting unavailable. 1 Main clock oscillation stabilization delay time initial value* selection (FCH = 10 MHz) Selectable • 01: 212/FCH (Approx. 0.41 ms) • 10: 216/FCH (Approx. 6.55 ms) • 11: 218/FCH (Approx. 26.2 ms) 2 LCD driving power supply • On-chip voltage booster • Internal voltage divider (external divider resistors can be used) Internal voltage booster 218/FCH (Approx. 26.2 ms) Selectable by version number MB89PV560 Setting unavailable. 218/FCH (approx. 26.2ms) -101 Internal voltage divider -102 On-chip voltage booster 47 MB89560H Series ■ ORDERING INFORMATION Part number MB89567HPFV MB89567HCPFV MB89P568PFV-101 MB89567HPFV MB89567HCPFV MB89P568PFV-102 MB89567HPF MB89567HCPF MB89P568PF-101 MB89567HPF MB89567HCPF MB89P568PF-102 MB89567HPFM MB89567HCPFM MB89P568PFM-101 MB89567HPFM MB89567HCPFM MB89P568PFM-102 Package 80-pin Plastic LQFP (FPT-80P-M05) 48 Without Booster Resistor divider With Booster 80-pin Plastic QFP (FPT-80P-M06) Without Booster Resistor divider With Booster 80-pin Plastic LQFP (FPT-80P-M11) Without Booster Resistor divider With Booster MB89PV560CF-101 MB89PV560CF-102 Remarks 80-pin Ceramic MQFP (MQP-80C-P01) Without Booster Resistor divider With Booster MB89560H Series ■ PACKAGE DIMENSIONS 80-pin Plastic LQFP (FPT-80P-M05) +0.20 14.00±0.20(.551±.008)SQ 1.50 –0.10 +.008 .059 –.004 12.00±0.10(.472±.004)SQ 60 (Mounting height) 41 61 40 9.50 (.374) REF 13.00 (.512) NOM INDEX 80 21 LEAD No. 1 20 Details of "A" part "A" +0.08 0.50±0.08 (.0197±.0031) +0.05 0.18 –0.03 +.003 .007 –.001 0.127 –0.02 +.002 .005 –.001 0.10±0.10 (STAND OFF) (.004±.004) 0.50±0.20(.020±.008) 0.10(.004) 0 C 1994 FUJITSU LIMITED F80008S-2C-4 10˚ Dimension in mm (inches) 80-pin Plastic QFP (FPT-80P-M06) 23.90±0.40(.941±.016) 64 20.00±0.20(.787±.008) 3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF) 41 65 40 14.00±0.20 (.551±.008) 17.90±0.40 (.705±.016) 12.00(.472) REF 16.30±0.40 (.642±.016) INDEX 80 25 "A" LEAD No. 1 24 0.80(.0315)TYP 0.35±0.10 (.014±.004) 0.16(.006) 0.15±0.05(.006±.002) M Details of "A" part Details of "B" part 0.25(.010) "B" 0.10(.004) 18.40(.724)REF 22.30±0.40(.878±.016) C 1994 FUJITSU LIMITED F80010S-3C-2 0.30(.012) 0.18(.007)MAX 0.58(.023)MAX 0 10˚ 0.80±0.20 (.031±.008) Dimension in mm (inches) 49 MB89560H Series 80-pin Plastic LQFP (FPT-80P-M11) +0.20 1.50 0.10 +.008 .059 .004 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 60 41 61 (Mounting height) 40 12.35 (.486) REF 15.00 (.591) NOM 1 PIN INDEX 80 LEAD No. 21 1 Details of "A" part "A" 0.65(.0256)TYP 20 0.30±0.10 (.012±.004) 0.13(.005) M 0.127 .005 0.10(.004) C 0.10±0.10 (STAND OFF) (.004±.004) +0.05 0.02 +.002 .001 0 1995 FUJITSU LIMITED F80016S-1C-3 10˚ 0.50±0.20 (.020±.008) Deminsion in mm (inches) 80-pin Ceramic MQFP (MQP-80C-P01) 18.70(.736)TYP 12.00(.472)TYP INDEX AREA 16.30±0.33 (.642±.013) 15.58±0.20 (.613±.008) 1.50(.059)TYP 1.00(.040)TYP 4.50(.177) TYP 1.27±0.13 (.050±.005) 22.30±0.33 (.878±.013) 24.70(.972) TYP 0.30(.012) TYP 0.80±0.25 (.0315±.010) 0.80±0.25 (.0315±.010) +0.40 1.20 –0.20 +.016 .047 –.008 INDEX AREA 18.12±0.20 12.02(.473) (.713±.008) TYP 10.16(.400) 14.22(.560) TYP TYP 18.40(.724) REF INDEX 1.27±0.13 (.050±.005) 6.00(.236) TYP 0.30(.012)TYP 7.62(.300)TYP 9.48(.373)TYP 11.68(.460)TYP 0.40±0.10 (.016±.004) 1.50(.059) TYP 1.00(.040) TYP 0.40±0.10 (.016±.004) +0.40 1.20 –0.20 +.016 .047 –.008 0.15±0.05 8.70(.343) (.006±.002) MAX C 50 1994 FUJITSU LIMITED M80001SC-4-2 Dimension in mm (inches) MB89560H Series MEMO 51 MB89560H Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 1250 East Arques Avenue Sunnyvale, CA 94088-3470, USA Tel: (408) 737-5600 Fax: (408) 737-5999 Mon. - Fri.: 7 am - 5 pm (PST) Toll Free: (800) 866-8608 http://www.fma.fujitsu.com/ All Rights Reserved. Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9806 FUJITSU LIMITED Printed in Japan 52 Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.