TM SPANSION Flash Memory Data Sheet September 2003 TM This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary. TM product. Future routine Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions. TM memory FUJITSU SEMICONDUCTOR DATA SHEET DS05-20846-6E FLASH MEMORY CMOS 16M (2M × 8/1M × 16) BIT MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ GENERAL DESCRIPTION The MBM29LV160T/B is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29LV160T/B is offered in a 48-pin TSOP (1), 48-pin CSOP and 48-ball FBGA packages. The device is designed to be programmed in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. The standard MBM29LV160T/B offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29LV160T/B is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29LV160T/B is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins. (Continued) ■ PRODUCT LINE UP Part No. MBM29LV160T/160B VCC = 3.3 V +0.3 V –0.3 V -80 — — VCC = 3.0 V +0.6 V –0.3 V — -90 -12 Max Address Access Time (ns) 80 90 120 Max CE Access Time (ns) 80 90 120 Max OE Access Time (ns) 30 35 50 Ordering Part No. MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (Continued) Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. ■ FEATURES • Single 3.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (1) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 80 ns maximum access time • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded programTM* Algorithms Automatically programs and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion (Continued) 2 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (Continued) • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Low VCC write inhibit ≤ 2.5 V • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector protection Hardware method disables any combination of sectors from program or erase operations • Sector Protection set function by Extended sector Protect command • Fast Programming Function by Extended Command • Temporary sector unprotection Temporary sector unprotection via the RESET pin • In accordance with CFI (Common Flash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. ■ PACKAGES 48-pin plastic TSOP (1) Marking Side Marking Side (FPT-48P-M19) (FPT-48P-M20) 48-pin plastic CSOP 48-pin plastic FBGA (LCC-48P-M03) (BGA-48P-M13) 3 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ PIN ASSIGNMENTS TSOP(1) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. N.C. RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) Reverse Bend (FPT-48P-M20) (Continued) 4 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (Continued) (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY N.C. N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 CSOP-48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (LCC-48P-M03) FBGA (TOP VIEW) Marking side A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 C1 C2 C3 C4 C5 C6 D1 D2 D3 D4 D5 D6 E1 E2 E3 E4 E5 E6 F1 F2 F3 F4 F5 F6 G1 G2 G3 G4 G5 G6 H1 H2 H3 H4 H5 H6 (BGA-48P-M13) A1 A3 A2 A7 A3 RY/BY A4 WE A5 A9 A6 A13 B1 A4 B2 A17 B3 N.C. B4 RESET B5 A8 B6 A12 C1 A2 C2 A6 C3 A18 C4 N.C. C5 A10 C6 A14 D1 A1 D2 A5 D3 N.C. D4 A19 D5 A11 D6 A15 E1 A0 E2 DQ0 E3 DQ2 E4 DQ5 E5 DQ7 E6 A16 F1 CE F2 DQ8 F3 DQ10 F4 DQ12 F5 DQ14 F6 BYTE G1 OE G2 DQ9 G3 DQ11 G4 VCC G5 DQ13 G6 DQ15/A-1 H1 VSS H2 DQ1 H3 DQ3 H4 DQ4 H5 DQ6 H6 VSS 5 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ PIN DESCRIPTIONS Pin Name 6 Function A19 to A0, A-1 Address Inputs DQ15 to DQ0 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Unprotection BYTE Selects 8-bit or 16-bit mode N.C. Pin Not Connected Internally VSS Device Ground VCC Device Power Supply MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ BLOCK DIAGRAM DQ15 to DQ0 RY/BY Buffer RY/BY VCC VSS WE BYTE RESET Input/Output Buffers Erase Voltage Generator State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic CE OE STB Low VCC Detector Timer for Program/Erase Address Latch STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A19 to A0 A-1 ■ LOGIC SYMBOL A-1 20 A19 to A0 16 or 8 DQ15 to DQ0 CE OE WE RESET RY/BY BYTE 7 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ DEVICE BUS OPERATION MBM29LV160T/B User Bus Operation Table (BYTE = VIH) CE OE WE A0 A1 A6 A9 L L H L L L VID Code H Auto-Select Device Code *1 L L H H L L VID Code H Read *3 L L H A0 A1 A6 A9 DOUT H Standby H X X X X X X High-Z H Output Disable L H H X X X X High-Z H Write (Program/Erase) L H L A0 A1 A6 A9 DIN H Enable Sector Protection *2, *4 L VID L H L VID X H L L H L H L VID Code H Temporary Sector Unprotection * X X X X X X X X VID Reset (Hardware)/Standby X X X X X X X High-Z L Operation Auto-Select Manufacture Code * 1 Verify Sector Protection *2, *4 5 Legend: L = VIL, H = VIH, X = VIL or VIH. DQ15 to DQ0 RESET = pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29LV160T/B Standard Command Definitions Table”. *2 : Refer to the section on Sector Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 3.3 V ±10% *5 : It is also used for the extended sector protection. MBM29LV160T/B User Bus Operation Table (BYTE = VIL) CE OE A0 A1 A6 A9 DQ15 to DQ0 RESET L L H L L L L VID Code H L L H L H L L VID Code H L L H A-1 A0 A1 A6 A9 DOUT H Standby H X X X X X X X High-Z H Output Disable L H H X X X X X High-Z H L H L A-1 A0 A1 A6 A9 DIN H Enable Sector Protection * * L VID L L H L VID X H Verify Sector Protection *2, *4 L L H L L H L VID Code H Temporary Sector Unprotection *5 X X X X X X X X X VID Reset (Hardware)/Standby X X X X X X X X High-Z L Operation Auto-Select Manufacture Code * Auto-Select Device Code * Read * 1 1 3 Write (Program/Erase) 2, 4 Legend: L = VIL, H = VIH, X = VIL or VIH. WE DQ15/A-1 = pulse input. See “■DC CHARACTERISTICS” for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29LV160T/B Standard Command Definitions Table”. *2 : Refer to the section on Sector Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC = 3.3 V ±10% *5 : It is also used for the extended sector protection. 8 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 MBM29LV160T/B Standard Command Definitions Table Command Sequence *1, *2, *3, *5 Read/Reset *6 Word /Byte Word Read/Reset *6 Byte Word Autoselect Byte Byte/Word Program *3, *4 Word Byte Word Chip Erase Byte Word Sector Erase *3 Byte Bus Write Cycles Req'd 1 3 3 4 6 6 Second Bus Fifth Bus First Bus Third Bus Fourth Sixth Bus Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data XXXh F0h 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh AAh AAh AAh AAh AAh — 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h — 55h 55h 55h 55h 55h — 555h AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh — — — — — — — F0h RA RD — — — — 90h — — — — — — A0h PA PD — — — — 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAh 10h 55h SA 30h Sector Erase Suspend Word /Byte 1 XXXh B0h — — — — — — — — — — Sector Erase Resume Word /Byte 1 XXXh — — — — — — — — — — 30h *1: Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and Sector Address (SA). *2: Bus operations are defined in “MBM29LV160T/B User Bus Operation Tables (BYTE = VIH and BYTE = VIL)”. *3: RA= Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA= Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. *4: RD= Data read from location RA during read operation. PD= Data to be programmed at location PA. Data is latched on the rising edge of WE. *5: The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A10 to A0 Byte Mode: AAAh or 555h to addresses A10 to A-1 *6: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Note: The command combinations not described in “MBM29LV160T/B Standard Command Definitions” and “MBM29LV160T/B Extended Command Definitions” are illegal. 9 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 MBM29LV160T/B Extended Command Definitions Table Bus Write Cycles Req'd Command Sequence Set to Fast Mode Fast Program *1 Word Byte Word Byte Reset from Fast Mode *1 Word Query Command *2 Word Byte Byte Extended Sector Word Protect *3 Byte 3 2 2 First Bus Write Cycle Addr 555h AAAh XXXh XXXh XXXh XXXh 55h 2 4 AAh XXXh Data AAh A0h 90h Second Bus Write Cycle Addr 2AAh 555h PA XXXh XXXh Data 55h Third Bus Write Cycle Addr 555h AAAh Fourth Bus Read Cycle Data Addr Data 20h — — PD — — — — F0h *4 — — — — 98h — — — — — — 60h SPA 60h SPA 40h SPA SD SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD : Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. *1 : This command is valid during fast mode. *2 : The valid addresses are A6 to A0. The other addresses are “Don’t care”. *3 : This command is valid while VID = RESET. *4 : The data “00h” is also acceptable. 10 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 MBM29LV160T/B Sector Protection Verify Autoselect Code Table Type A19 to A12 A6 A1 A0 A-1*1 Code (HEX) X VIL VIL VIL VIL 04h X VIL VIL VIH VIL C4h X 22C4h X VIL VIL VIH VIL 49h X 2249h Sector Addresses VIL VIH VIL VIL 01h*2 Manufacture’s Code Byte MBM29LV160T Word Device Code Byte MBM29LV160B Word Sector Protection *1: A-1 is for Byte mode. At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. *2: Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. Extended Autoselect Code Table Type Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Manufacture’s Code 04h A-1/0 (B)* 0 0 0 0 0 1 0 0 C4h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 1 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 49h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 1 0 0 1 MBM29LV160T (W) 22C4h Device Code (B)* 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 MBM29LV160B (W) 2249h Sector Protection 0 01h A-1/0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 (B): Byte mode (W): Word mode HI-Z : High-Z * : At Byte mode, DQ14 to DQ8 are High-Z and DQ15 is A-1, the lowest address. 11 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE • • • • One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode. One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode. Individual-sector, multiple-sector, or bulk-erase capability. Individual or multiple-sector protection is user definable. MBM29LV160T Top Boot Sector Architecture 12 Sector Sector Size (× 8) Address Range (× 16) Address Range SA0 64 Kbytes or 32 Kwords 00000h to 0FFFFh 00000h to 07FFFh SA1 64 Kbytes or 32 Kwords 10000h to 1FFFFh 08000h to 0FFFFh SA2 64 Kbytes or 32 Kwords 20000h to 2FFFFh 10000h to 17FFFh SA3 64 Kbytes or 32 Kwords 30000h to 3FFFFh 18000h to 1FFFFh SA4 64 Kbytes or 32 Kwords 40000h to 4FFFFh 20000h to 27FFFh SA5 64 Kbytes or 32 Kwords 50000h to 5FFFFh 28000h to 2FFFFh SA6 64 Kbytes or 32 Kwords 60000h to 6FFFFh 30000h to 37FFFh SA7 64 Kbytes or 32 Kwords 70000h to 7FFFFh 38000h to 3FFFFh SA8 64 Kbytes or 32 Kwords 80000h to 8FFFFh 40000h to 47FFFh SA9 64 Kbytes or 32 Kwords 90000h to 9FFFFh 48000h to 4FFFFh SA10 64 Kbytes or 32 Kwords A0000h to AFFFFh 50000h to 57FFFh SA11 64 Kbytes or 32 Kwords B0000h to BFFFFh 58000h to 5FFFFh SA12 64 Kbytes or 32 Kwords C0000h to CFFFFh 60000h to 67FFFh SA13 64 Kbytes or 32 Kwords D0000h to DFFFFh 68000h to 6FFFFh SA14 64 Kbytes or 32 Kwords E0000h to EFFFFh 70000h to 77FFFh SA15 64 Kbytes or 32 Kwords F0000h to FFFFFh 78000h to 7FFFFh SA16 64 Kbytes or 32 Kwords 100000h to 10FFFFh 80000h to 87FFFh SA17 64 Kbytes or 32 Kwords 110000h to 11FFFFh 88000h to 8FFFFh SA18 64 Kbytes or 32 Kwords 120000h to 12FFFFh 90000h to 97FFFh SA19 64 Kbytes or 32 Kwords 130000h to 13FFFFh 98000h to 9FFFFh SA20 64 Kbytes or 32 Kwords 140000h to 14FFFFh A0000h to A7FFFh SA21 64 Kbytes or 32 Kwords 150000h to 15FFFFh A8000h to AFFFFh SA22 64 Kbytes or 32 Kwords 160000h to 16FFFFh B0000h to B7FFFh SA23 64 Kbytes or 32 Kwords 170000h to 17FFFFh B8000h to BFFFFh SA24 64 Kbytes or 32 Kwords 180000h to 18FFFFh C0000h to C7FFFh SA25 64 Kbytes or 32 Kwords 190000h to 19FFFFh C8000h to CFFFFh SA26 64 Kbytes or 32 Kwords 1A0000h to 1AFFFFh D0000h to D7FFFh SA27 64 Kbytes or 32 Kwords 1B0000h to 1BFFFFh D8000h to DFFFFh SA28 64 Kbytes or 32 Kwords 1C0000h to 1CFFFFh E0000h to E7FFFh SA29 64 Kbytes or 32 Kwords 1D0000h to 1DFFFFh E8000h to EFFFFh SA30 64 Kbytes or 32 Kwords 1E0000h to 1EFFFFh F0000h to F7FFFh SA31 32 Kbytes or 16 Kwords 1F0000h to 1F7FFFh F8000h to FBFFFh SA32 8 Kbytes or 4 Kwords 1F8000h to 1F9FFFh FC000h to FCFFFh SA33 8 Kbytes or 4 Kwords 1FA000h to 1FBFFFh FD000h to FDFFFh SA34 16 Kbytes or 8 Kwords 1FC000h to 1FFFFFh FE000h to FFFFFh MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 MBM29LV160B Bottom Boot Sector Architecture Sector Sector Size (× 8) Address Range (× 16) Address Range SA0 16 Kbytes or 8 Kwords 00000h to 03FFFh 00000h to 01FFFh SA1 8 Kbytes or 4 Kwords 04000h to 05FFFh 02000h to 02FFFh SA2 8 Kbytes or 4 Kwords 06000h to 07FFFh 03000h to 03FFFh SA3 32 Kbytes or 16 Kwords 08000h to 0FFFFh 04000h to 07FFFh SA4 64 Kbytes or 32 Kwords 10000h to 1FFFFh 08000h to 0FFFFh SA5 64 Kbytes or 32 Kwords 20000h to 2FFFFh 10000h to 17FFFh SA6 64 Kbytes or 32 Kwords 30000h to 3FFFFh 18000h to 1FFFFh SA7 64 Kbytes or 32 Kwords 40000h to 4FFFFh 20000h to 27FFFh SA8 64 Kbytes or 32 Kwords 50000h to 5FFFFh 28000h to 2FFFFh SA9 64 Kbytes or 32 Kwords 60000h to 6FFFFh 30000h to 37FFFh SA10 64 Kbytes or 32 Kwords 70000h to 7FFFFh 38000h to 3FFFFh SA11 64 Kbytes or 32 Kwords 80000h to 8FFFFh 40000h to 47FFFh SA12 64 Kbytes or 32 Kwords 90000h to 9FFFFh 48000h to 4FFFFh SA13 64 Kbytes or 32 Kwords A0000h to AFFFFh 50000h to 57FFFh SA14 64 Kbytes or 32 Kwords B0000h to BFFFFh 58000h to 5FFFFh SA15 64 Kbytes or 32 Kwords C0000h to CFFFFh 60000h to 67FFFh SA16 64 Kbytes or 32 Kwords D0000h to DFFFFh 68000h to 6FFFFh SA17 64 Kbytes or 32 Kwords E0000h to EFFFFh 70000h to 77FFFh SA18 64 Kbytes or 32 Kwords F0000h to FFFFFh 78000h to 7FFFFh SA19 64 Kbytes or 32 Kwords 100000h to 10FFFFh 80000h to 87FFFh SA20 64 Kbytes or 32 Kwords 110000h to 11FFFFh 88000h to 8FFFFh SA21 64 Kbytes or 32 Kwords 120000h to 12FFFFh 90000h to 97FFFh SA22 64 Kbytes or 32 Kwords 130000h to 13FFFFh 98000h to 9FFFFh SA23 64 Kbytes or 32 Kwords 140000h to 14FFFFh A0000h to A7FFFh SA24 64 Kbytes or 32 Kwords 150000h to 15FFFFh A8000h to AFFFFh SA25 64 Kbytes or 32 Kwords 160000h to 16FFFFh B0000h to B7FFFh SA26 64 Kbytes or 32 Kwords 170000h to 17FFFFh B8000h to BFFFFh SA27 64 Kbytes or 32 Kwords 180000h to 18FFFFh C0000h to C7FFFh SA28 64 Kbytes or 32 Kwords 190000h to 19FFFFh C8000h to CFFFFh SA29 64 Kbytes or 32 Kwords 1A0000h to 1AFFFFh D0000h to D7FFFh SA30 64 Kbytes or 32 Kwords 1B0000h to 1BFFFFh D8000h to DFFFFh SA31 64 Kbytes or 32 Kwords 1C0000h to 1CFFFFh E0000h to E7FFFh SA32 64 Kbytes or 32 Kwords 1D0000h to 1DFFFFh E8000h to EFFFFh SA33 64 Kbytes or 32 Kwords 1E0000h to 1EFFFFh F0000h to F7FFFh SA34 64 Kbytes or 32 Kwords 1F0000h to 1FFFFFh F8000h to FFFFFh 13 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Sector Address Table (MBM29LV160T) 14 Sector Address A19 A18 A17 A16 A15 A14 A13 A12 (× 8) Address Range (× 16) Address Range SA0 0 0 0 0 0 X X X 00000h to 0FFFFh 00000h to 07FFFh SA1 0 0 0 0 1 X X X 10000h to 1FFFFh 08000h to 0FFFFh SA2 0 0 0 1 0 X X X 20000h to 2FFFFh 10000h to 17FFFh SA3 0 0 0 1 1 X X X 30000h to 3FFFFh 18000h to 1FFFFh SA4 0 0 1 0 0 X X X 40000h to 4FFFFh 20000h to 27FFFh SA5 0 0 1 0 1 X X X 50000h to 5FFFFh 28000h to 2FFFFh SA6 0 0 1 1 0 X X X 60000h to 6FFFFh 30000h to 37FFFh SA7 0 0 1 1 1 X X X 70000h to 7FFFFh 38000h to 3FFFFh SA8 0 1 0 0 0 X X X 80000h to 8FFFFh 40000h to 47FFFh SA9 0 1 0 0 1 X X X 90000h to 9FFFFh 48000h to 4FFFFh SA10 0 1 0 1 0 X X X A0000h to AFFFFh 50000h to 57FFFh SA11 0 1 0 1 1 X X X B0000h to BFFFFh 58000h to 5FFFFh SA12 0 1 1 0 0 X X X C0000h to CFFFFh 60000h to 67FFFh SA13 0 1 1 0 1 X X X D0000h to DFFFFh 68000h to 6FFFFh SA14 0 1 1 1 0 X X X E0000h to EFFFFh 70000h to 77FFFh SA15 0 1 1 1 1 X X X F0000h to FFFFFh 78000h to 7FFFFh SA16 1 0 0 0 0 X X X 100000h to 10FFFFh 80000h to 87FFFh SA17 1 0 0 0 1 X X X 110000h to 11FFFFh 88000h to 8FFFFh SA18 1 0 0 1 0 X X X 120000h to 12FFFFh 90000h to 97FFFh SA19 1 0 0 1 1 X X X 130000h to 13FFFFh 98000h to 9FFFFh SA20 1 0 1 0 0 X X X 140000h to 14FFFFh A0000h to A7FFFh SA21 1 0 1 0 1 X X X 150000h to 15FFFFh A8000h to AFFFFh SA22 1 0 1 1 0 X X X 160000h to 16FFFFh B0000h to B7FFFh SA23 1 0 1 1 1 X X X 170000h to 17FFFFh B8000h to BFFFFh SA24 1 1 0 0 0 X X X 180000h to 18FFFFh C0000h to C7FFFh SA25 1 1 0 0 1 X X X 190000h to 19FFFFh C8000h to CFFFFh SA26 1 1 0 1 0 X X X 1A0000h to 1AFFFFh D0000h to D7FFFh SA27 1 1 0 1 1 X X X 1B0000h to 1BFFFFh D8000h to DFFFFh SA28 1 1 1 0 0 X X X 1C0000h to 1CFFFFh E0000h to E7FFFh SA29 1 1 1 0 1 X X X 1D0000h to 1DFFFFh E8000h to EFFFFh SA30 1 1 1 1 0 X X X 1E0000h to 1EFFFFh F0000h to F7FFFh SA31 1 1 1 1 1 0 X X 1F0000h to 1F7FFFh F8000h to FBFFFh SA32 1 1 1 1 1 1 0 0 1F8000h to 1F9FFFh FC000h to FCFFFh SA33 1 1 1 1 1 1 0 1 1FA000h to 1FBFFFh FD000h to FDFFFh SA34 1 1 1 1 1 1 1 X 1FC000h to 1FFFFFh FE000h to FEFFFh MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Sector Address Table (MBM29LV160B) Sector Address A19 A18 A17 A16 A15 A14 A13 A12 (× 8) Address Range (× 16) Address Range SA0 0 0 0 0 0 0 0 X 00000h to 03FFFh 00000h to 01FFFh SA1 0 0 0 0 0 0 1 0 04000h to 05FFFh 02000h to 02FFFh SA2 0 0 0 0 0 0 1 1 06000h to 07FFFh 03000h to 03FFFh SA3 0 0 0 0 0 1 0 X 08000h to 0FFFFh 04000h to 07FFFh SA4 0 0 0 0 1 X X X 10000h to 1FFFFh 08000h to 0FFFFh SA5 0 0 0 1 0 X X X 20000h to 2FFFFh 10000h to 17FFFh SA6 0 0 0 1 1 X X X 30000h to 3FFFFh 18000h to 1FFFFh SA7 0 0 1 0 0 X X X 40000h to 4FFFFh 20000h to 27FFFh SA8 0 0 1 0 1 X X X 50000h to 5FFFFh 28000h to 2FFFFh SA9 0 0 1 1 0 X X X 60000h to 6FFFFh 30000h to 37FFFh SA10 0 0 1 1 1 X X X 70000h to 7FFFFh 38000h to 3FFFFh SA11 0 1 0 0 0 X X X 80000h to 8FFFFh 40000h to 47FFFh SA12 0 1 0 0 1 X X X 90000h to 9FFFFh 48000h to 4FFFFh SA13 0 1 0 1 0 X X X A0000h to AFFFFh 50000h to 57FFFh SA14 0 1 0 1 1 X X X B0000h to BFFFFh 58000h to 5FFFFh SA15 0 1 1 0 0 X X X C0000h to CFFFFh 60000h to 67FFFh SA16 0 1 1 0 1 X X X D0000h to DFFFFh 68000h to 6FFFFh SA17 0 1 1 1 0 X X X E0000h to EFFFFh 70000h to 77FFFh SA18 0 1 1 1 1 X X X F0000h to FFFFFh 78000h to 7FFFFh SA19 1 0 0 0 0 X X X 100000h to 1FFFFFh 80000h to 87FFFh SA20 1 0 0 0 1 X X X 110000h to 11FFFFh 88000h to 8FFFFh SA21 1 0 0 1 0 X X X 120000h to 12FFFFh 90000h to 97FFFh SA22 1 0 0 1 1 X X X 130000h to 13FFFFh 98000h to 9FFFFh SA23 1 0 1 0 0 X X X 140000h to 14FFFFh A0000h to A7FFFh SA24 1 0 1 0 1 X X X 150000h to 15FFFFh A8000h to 8FFFFh SA25 1 0 1 1 0 X X X 160000h to 16FFFFh B0000h to B7FFFh SA26 1 0 1 1 1 X X X 170000h to 17FFFFh B8000h to BFFFFh SA27 1 1 0 0 0 X X X 180000h to 18FFFFh C0000h to C7FFFh SA28 1 1 0 0 1 X X X 190000h to 19FFFFh C8000h to CFFFFh SA29 1 1 0 1 0 X X X 1A0000h to 1AFFFFh D0000h to D7FFFh SA30 1 1 0 1 1 X X X 1B0000h to 1BFFFFh D8000h to DFFFFh SA31 1 1 1 0 0 X X X 1C0000h to 1CFFFFh E0000h to E7FFFh SA32 1 1 1 0 1 X X X 1D0000h to 1DFFFFh E8000h to EFFFFh SA33 1 1 1 1 0 X X X 1E0000h to 1EFFFFh F0000h to F7FFFh SA34 1 1 1 1 1 X X X 1F0000h to 1FFFFFh F8000h to FFFFFh 15 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Common Flash Memory Interface Code Table A6 to A0 DQ15 to DQ0 Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Erase Block Region 1 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z×256 bytes) 2Dh 2Eh 2Fh 30h 0000h 0000h 0040h 0000h Primary OEM Command Set 02h: AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Erase Block Region 2 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z×256 bytes) 31h 32h 33h 34h 0001h 0000h 0020h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min (write/erase) DQ7 to DQ4 : 1 V DQ3 to DQ0 : 100 mV 1Bh 0027h Erase Block Region 3 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z×256 bytes) 35h 36h 37h 38h 0000h 0000h 0080h 0000h VCC Max (write/erase) DQ7 to DQ4 : 1 V DQ3 to DQ0 : 100 mV 1Ch 0036h Erase Block Region 4 Information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z×256 bytes) 39h 3Ah 3Bh 3Ch 001Eh 0000h 0000h 0001h VPP Min voltage 1Dh 0000h VPP Max voltage 1Eh 0000h Typical timeout per single byte/word write 2N µs 1Fh 0004h Typical timeout for Min size buffer write 2N µs 20h 0000h Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Typical timeout per individual sector erase 2N ms 21h 000Ah Major version number, ASCII 43h 0031h Typical timeout for full chip erase 2N ms 22h 0000h Minor version number, ASCII 44h 0030h Max timeout for byte/word write 2N times typical 0000h 0005h Address Sensitive Unlock 00h = Required 45h 23h 0002h 24h 0000h Erase Suspend 02h = To Read & Write 46h Max timeout for buffer write 2N times typical 47h 0001h Max timeout per individual sector erase 2N times typical 25h 0004h Max timeout for full chip erase 2N times typical 26h 0000h Sector Protect 00h = Not Supported X = Number of sectors in per group 48h 0001h Device Size = 2N byte 27h 0015h Sector Temporary Unprotect 01h = Supported Flash Device Interface description 02h : ×8/×16 28h 29h 0002h 0000h Sector Protection Algorithm 49h 0004h Max number of bytes in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0004h Description 16 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ FUNCTIONAL DESCRIPTION Read Mode The MBM29LV160T/B has two control functions which must be satisfied in order to obtain data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses have been stable for at least tACC - tOE time.) See “(1) AC Waveforms for Read Operations” in ■TIMING DIAGRAM for timing specifications. Standby Mode There are two ways to implement the standby mode on the MBM29LV160T/B devices. One is by using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ±0.3 V. Under this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC Active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with the RESET input held at VSS ±0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires tRH of wake up time before outputs are valid for read access. In the standby mode, the outputs are in the high-impedance state, independent of the OE input. Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29LV160T/B data. This mode can be used effectively with an application requesting low power consumption such as handy terminals. To activate this mode, MBM29LV160T/B automatically switches itself to low power mode when addresses remain stable for 150 ns. It is not necessary to control CE, WE, and OE in this mode. During such mode, the current consumed is typically 1 µA (CMOS Level). Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Output Disable If the OE input is at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state. Autoselect The Autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command may also be used to check the status of write-protected sectors. (See “MBM29LV160T/B Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION.) This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1). (See “MBM29LV160T/B User Bus Operation Tables (BYTE = VIH or BYTE = VIL) ” in ■DEVICE BUS OPERATION.) The manufacturer and device codes may also be read via the command register, for instances when the MBM29LV160T/B is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “MBM29LV160T/B Standard Command Definitions Table” in ■DEVICE BUS OPERATION. 17 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Byte 0 (A0 = VIL) represents the manufacture’s code and byte 1 (A0 = VIH) represents the device identifier code. For the MBM29LV160T/B these two bytes are given in “Extended Autoselect Code Table” (in ■DEVICE BUS OPERATION). All identifiers for manufactures and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. (See “MBM29LV160T/B User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATION.) For device indentification in word mode (BYTE = VIH), DQ9 and DQ13 are equal to ‘1’ and DQ15, DQ14, DQ12 to DQ10 and DQ8 are equal to ‘0’. If BYTE = VIL (for byte mode), the device code is C4h (for top boot block) or 49h (for bottom boot block). If BYTE = VIH (for word mode), the device code is 22C4h (for top boot block) or 2249h (for bottom boot block). In order to determine which sectors are write protected, A1 must be at VIH while running through the sector addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ0 (DQ0 =1). Write Device erasure and programming are accomplished via the command register. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first. Standard microprocessor write timings are used. See “(3) AC Waveforms for Alternate WE Controlled Program Operations” and “(4) AC Waveforms for Alternate CE Controlled Program Operations” and “(5) AC Waveforms for Chip/Sector Erase Operations” in ■TIMING DIAGRAM. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Protection The MBM29LV160T/B features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 34). The sector protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29LV160T/B)” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the thirty five (35) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE pulse. See “(13) AC Waveforms for Sector Protection Timing Diagram” in ■TIMING DIAGRAM and “(5) Sector Protection Algorithm” in ■FLOW CHART for sector protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. Otherwise the device will read 00h for an unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to VIL in byte mode. It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See “MBM29LV160T/B Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION for Autoselect codes. Temporary Sector Unprotection This feature allows temporary unprotection of previously protected sectors of the MBM29LV160T/B devices in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage (12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. (See “(15) Temporary Sector Unprotection Timing Diagram” in ■TIMING DIAGRAM and “(6) Temporary Sector Unprotection Algorithm” in ■FLOW CHART.) 18 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. “MBM29LV160T/B Standard Command Definitions” in ■DEVICE BUS OPERATION defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. (See “(1) AC Waveforms for Read Operations” in ■TIMING DIAGRAM.) Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read cycle from address XX01h for ×16 (XX02h for ×8) retrieves the device code (MBM29LV160T = C4h and MBM29LV160B = 49h for ×8 mode; MBM29LV160T = 22C4h and MBM29LV160B = 2249h for ×16 mode). (See “MBM29LV160T/B Sector Protection Verify Autoselect Code Table” and “Extended Autoselect Code Table” in ■DEVICE BUS OPERATION.) All manufactures and device codes will exhibit odd parity with DQ7 defined as the parity bit. The sector state (protection or unprotection) will be indicated by address XX02h for ×16 (XX04h for ×8). Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode verification on the protected sector. (See “MBM29LV160T/B User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” in ■DEVICE BUS OPERATION.) To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by executing it after writing the Read/Reset command sequence. Word/Byte Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See “(3) AC Waveforms for Alternate WE Controlled Program Operations” and “(4) AC Waveforms for Alternate CE Controlled Program Operations” in ■TIMING DIAGRAM.) 19 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags Table”.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during this period will be ignored. If hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “(1) Embedded ProgramTM Algorithm” in ■FLOW CHART illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Chip Erase Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (Preprogram Function.) The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device returns to read mode. (See “(5) AC Waveforms for Chip/Sector Erase Operations” in ■TIMING DIAGRAM.) “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (Data = 30h) is latched on the rising edge of WE. After a time-out of 50 µs from the rising edge of the last sector erase command, the sector erase operation will begin. Multiple sectors may be erased concurrently by writing six-bus cycle operations on “MBM29LV160T/B Standard Command Definitions” in ■DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE will initiate the execution of the Sector Erase command(s). If another falling edge of the WE occurs within the 50 µs timeout window the timer is reset. Monitor DQ3 to determine if the sector erase timer window is still open. (See section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. (See “(5) AC Waveforms for Chip/Sector Erase Operations” in ■TIMING DIAGRAM.) 20 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 The automatic sector erase begins after the 50 µs time out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section) at which time the device returns to the read mode. Data polling must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogramming) + Sector Erase Time] × Number of Sector Erase. “(2) Embedded EraseTM Algorithm” in ■FLOW CHART illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Erase Suspend/Resume The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands. When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or the Toggle Bit (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address. To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Extended Command (1) Fast Mode MBM29LV160T/B has Fast Mode function. This mode dispenses with the initial two unlock cycles required in the standard program command sequence writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. The read operation is also executed after exiting this mode. During the Fast mode, do not write any command other than the Fast program/Fast mode reset command. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to “(7) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to “(7) Embedded Programming Algorithm for Fast Mode” in ■FLOW CHART.) 21 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail. The operation is initiated by writing the query command (98h) into the command register. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to “Common Flash Memory Interface Code Table” in ■FLEXIBLE SECTOR-ERASE ARCHITECTURE. To terminate operation, it is necessary to write the read/reset command sequence into the register. (4) Extended Sector Protect In addition to normal sector protection, the MBM29LV160T/B has Extended Sector Protection as extended function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write extended sector protect command (60h). A sector is typically protected in 150 µs. To verify programming of the protection circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. Write Operation Status Hardware Sequence Flags Table Status DQ7 DQ6 DQ5 DQ3 DQ2 Embedded Program Algorithm DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle 1 1 0 0 Toggle Data Data Data Data Data DQ7 Toggle*1 0 0 1*2 DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A Embedded/Erase Algorithm In Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspend (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Exceeded Time Limits Embedded/Erase Algorithm Erase Suspend Program (Non-Erase Suspended Sector) *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. Notes : • DQ0 and DQ1 are reserve pins for future use. • DQ4 is Fujitsu internal use only. 22 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 DQ7 Data Polling The MBM29LV160T/B device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in “(3) Data Polling Algorithm” in ■FLOW CHART. For chip erase and sector erase, Data Polling is valid after the rising edge of the sixth WE pulse in the six-write pulse sequence. Data Polling must be performed at a sector address within any of the sectors being erased and not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29LV160T/B data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Program Algorithm operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will be read on successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See “(6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■TIMING DIAGRAM for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The MBM29LV160T/B also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data can be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the sixwrite pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 200 µs and then drop back into read mode, having changed none of the data. Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause the DQ6 to toggle. See “(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■TIMING DIAGRAM and “(4) Toggle Bit Algorithm” in ■FLOW CHART for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will control the output disable functions as described in “MBM29LV160T/B User Bus Operation Tables (BYTE = VIH and BYTE = VIL)” (in ■DEVICE BUS OPERATION). 23 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ7 and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used. If this occurs, reset the device with command sequence. DQ3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags Table”. DQ2 Toggle Bit II This Toggle Bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ2. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status Table” and “(16) DQ2 vs. DQ6” in ■TIMING DIAGRAM. Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. Toggle Bit Status Table DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle Erase Suspend Read (Erase Suspended Sector)*1 1 1 Toggle DQ7 Toggle*1 1 *2 Mode Program Erase-Suspend Program *1 : Performing successive read operations from any address will cause DQ6 to toggle. *2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 24 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 RY/BY Ready/Busy Pin The MBM29LV160T/B provides a RY/BY open-drain output pin as a way to indicate to the host system that the Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase commands with the exception of the Erase Suspend command. If the MBM29LV160T/B is placed in an Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC. During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a busy condition during the RESET pulse. See “(8) RY/BY Timing Diagram during Program/Erase Operations” and “(9) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode. Since this is an open-drain output, the pull-up resistor needs to be connected to VCC; multiples of devices may be connected to the host system via more than one RY/BY pin in parallel. RESET Hardware Reset Pin The MBM29LV160T/B device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode tREADY after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional tRH before it allows read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. Refer to “(9) RESET, RY/BY Timing Diagram” in ■TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality. If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s) will need to be erased again before they can be programmed. Word/Byte Configuration The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV160T/B device. When this pin is driven high, the device operates in the word (16-bit) mode. The data is read and programmed at DQ15 to DQ0. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin becomes the lowest address bit and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Refer to “(10) Timing Diagram for Word Mode Configuration” and “(11) Timing Diagram for Byte Mode Configuration” in ■TIMING DIAGRAM for the timing diagrams. Data Protection The MBM29LV160T/B is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting form VCC power-up and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until 25 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 2.3 V. If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not change the command registers. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE is a logical one. Power-up Write Inhibit Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up. Sector Protection Device user is able to protect each sector individually to store and protect data. Protection circuit voids both program and erase commands that are addressed to protect sectors. Any command to program or erase addressed to protected sector are ignored (see “Sector Protection” in ■FUNCTIONAL DESCRIPTION). 26 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC+0.5 V A9, OE and RESET*1, *3 VIN −2.0 +13.0 V Power Supply Voltage*1 VCC −0.5 +5.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, RESET*1, *2 *1: Voltage is defined on the basis of VSS = GND = 0 V. *2: Minimum DC voltage on input or l/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or l/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on A9, OE, and RESET pins is –0.5 V. During voltage transitions, A9, OE, and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE, and RESET pins are +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ambient Temperature TA Power Supply Voltage* VCC Part number Value Unit Min Max MBM29LV160T/B-80 −20 +70 °C MBM29LV160T/B-90/-12 −40 +85 °C MBM29LV160T/B-80 +3.0 MBM29LV160T/B-90/-12 +2.7 +3.6 V * : Voltage is defined on the basis of VSS = GND = 0 V. Note : Operating ranges define those limits between which the functionality of the devices are guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 27 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT +0.6 V 20 ns 20 ns –0.5 V –2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC +2.0 V VCC +0.5 V +2.0 V 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +14.0 V +13.0 V VCC +0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 28 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ DC CHARACTERISTICS Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max –1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max –1.0 +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max, A9, OE, RESET = 12.5 V — 35 µA 1 VCC Active Current * CE = VIL, OE = VIH, f = 10 MHz Byte CE = VIL, OE = VIH, f = 5 MHz Byte ICC1 Word Word 30 — 35 15 — 17 mA mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH — 35 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ±0.3 V, RESET = VCC ±0.3 V — 5 µA VCC Current (Standby, RESET) ICC4 VCC = VCC Max, RESET = VSS ±0.3 V — 5 µA VCC Current (Automatic Sleep Mode) *3 ICC5 VCC = VCC Max, CE = VSS ±0.3 V, RESET = VCC ±0.3 V, VIN = VCC ±0.3 V or VSS ±0.3 V — 5 µA Input Low Voltage VIL — –0.5 0.6 V Input High Voltage VIH — 2.0 VCC + 0.3 V Voltage for Autoselect,Sector Protection, and Temporary Sector Unprotection (A9, OE, RESET) *4, *5 VID — 11.5 12.5 V Output Low Voltage VOL IOL = 4.0 mA, VCC = VCC Min — 0.45 V VOH1 IOH = –2.0 mA, VCC = VCC Min 2.4 — V VOH2 IOH = –100 µA VCC – 0.4 — V 2.3 2.5 V Output High Voltage Low VCC Lock-Out Voltage VLKO — *1 : The lCC current listed includes both the DC operating current and the frequency dependent component. *2 : lCC active while Embedded Erase or Embedded Program is in progress. *3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : The timing is only for Sector Protection operation and Autoselect mode. *5 : (VID – VCC) do not exceed 9 V. 29 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Symbol Parameter JEDEC Standard Test Setup -80* -90* -12* Min Max Min Max Min Max Read Cycle Time tAVAV tRC — 80 90 120 ns Address to Output Delay tAVQV tACC CE = VIL OE = VIL 80 90 120 ns Chip Enable to Output Delay tELQV tCE OE = VIL 80 90 120 ns Output Enable to Output Delay tGLQV tOE — 30 35 50 ns Chip Enable to Output High-Z tEHQZ tDF — 25 30 30 ns Output Enable to Output High-Z tGHQZ tDF — 25 30 30 ns Output Hold Time From Address, CE or OE, Whichever Occurs First tAXQX tOH — 0 0 0 ns RESET Pin Low to Read Mode — tREADY — 20 20 20 µs CE to BYTE Switching Low or High — tELFL tELFH — 5 5 5 ns * : Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29LV160T/B-80/-90) 1 TTL gate and 100 pF (MBM29LV160T/B-12) Input rise and fall times: 5 ns Input pulse levels: 0.0 V or 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V 3.3 V Diode = 1N3064 or Equivalent 2.7 kΩ Device Under Test 6.2 kΩ CL Diode = 1N3064 or Equivalent Notes: CL = 30 pF including jig capacitance (MBM29LV160T/B-80/-90) CL = 100 pF including jig capacitance (MBM29LV160T/B-12) Test Conditions 30 Unit MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 • Write (Erase/Program) Operations Symbol Parameter JEDEC Standard Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Output Enable Hold Toggle and Time Data Polling tAVAV tAVWL tWLAX tDVWH tWHDX — tWC tAS tAH tDS tDH tOES — tOEH Read Recover Time Before Write tGHWL Read Recover Time Before Write (OE High to CE Low) CE Setup Time WE Setup Time CE Hold Time WE Hold Time Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Byte Programming Operation Word Sector Erase Operation *1 Delay Time from Embedded Output Enable VCC Setup Time Voltage Transition Time * 2 -90 Typ Max Min 120 0 50 50 0 0 0 -12 Unit Typ Max ns ns ns ns ns ns ns 10 10 10 ns tGHWL 0 0 0 ns tGHEL tGHEL 0 0 0 ns tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tWHWH2 8 16 1 0 0 0 0 45 45 25 25 8 16 1 0 0 0 0 50 50 30 30 8 16 1 ns ns ns ns ns ns ns ns tWHWH1 0 0 0 0 35 35 25 25 — tEOE 80 90 120 ns — — tVCS tVLHT 50 4 50 4 50 4 µs µs µs s — tWPP 100 100 100 µs 2 — tOESP 4 4 4 µs 2 — — — tCSP tRB tRH 4 0 200 4 0 200 4 0 200 µs ns ns — tBUSY 90 90 90 ns — tFLQZ 25 30 30 ns — tFHQV 80 90 120 ns — — tVIDR tRP 500 500 500 500 500 500 ns ns Write Pulse Width *2 OE Setup Time to WE Active * CE Setup Time to WE Active * Recover Time From RY/BY RESET Hold Time Before Read Program/Erase Valid to RY/BY Delay BYTE Switching Low to Output High-Z BYTE Switching High to Output Active Rise Time to VID *2 RESET Pulse Width -80 Min Typ Max Min 80 90 0 0 45 45 35 45 0 0 0 0 0 0 *1 : This does not include the preprogramming time. *2 : This timing is for Sector Protection operation. 31 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Min Typ Max Sector Erase Time — 1 10 Byte Programming Time — 8 360 Unit Comments s Excludes programming time prior to erasure µs Excludes system-level overhead Excludes system-level overhead Word Programming Time — 16 300 Chip Programming Time — 16.8 50 s 100,000 — — cycle Erase/Program Cycle — ■ TSOP (1) PIN CAPACITANCE Parameter Symbol Test Setup Input Capacitance CIN VIN = 0 Output Capacitance COUT Control Pin Capacitance CIN2 Typ (f = 1.0 MHz, TA = +25 °C) Max Unit 7.5 9.5 pF VOUT = 0 8 10 pF VIN = 0 10 13 pF Note : DQ15/A-1 pin capacitance is stipulated by output capacitance. ■ CSOP PIN CAPACITANCE Parameter Symbol Test Setup Input Capacitance CIN VIN = 0 Output Capacitance COUT Control Pin Capacitance CIN2 Typ (f = 1.0 MHz, TA = +25 °C) Max Unit 7.5 9.5 pF VOUT = 0 8 10 pF VIN = 0 10 13 pF Note : DQ15/A-1 pin capacitance is stipulated by output capacitance. ■ FBGA PIN CAPACITANCE Parameter Symbol Test Setup Input Capacitance CIN VIN = 0 Output Capacitance COUT Control Pin Capacitance CIN2 (f = 1.0 MHz, TA = +25 °C) Max Unit 7.5 9.5 pF VOUT = 0 8 10 pF VIN = 0 10 13 pF Note : DQ15/A-1 pin capacitance is stipulated by output capacitance. 32 Typ MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Be Change from H to L May Change from L to H Will Be Change from L to H “H” or “L”: Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State (1) AC Waveforms for Read Operations tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tCE Outputs High-Z tOH Output Valid High-Z 33 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (2) AC Waveforms for Hardware Reset/Read Operations tRC Address Address Stable tACC tRH RESET tOH High-Z Outputs Output Valid (3) AC Waveforms for Alternate WE Controlled Program Operations 3rd Bus Cycle Data Polling 555h Address PA tWC tAS PA tRC tAH CE tCH tCS tCE OE tGHWL tWP tWPH tOE tWHWH1 WE tDS Data A0h tDF tDH PD DQ7 DOUT tOH DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 34 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (4) AC Waveforms for Alternate CE Controlled Program Operations 3rd Bus Cycle Address Data Polling PA 555h tWC tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data A0h tDH PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at word address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 35 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (5) AC Waveforms for Chip/Sector Erase Operations Address 2AAh 555h tWC tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh Data 10h for Chip Erase 55h 80h AAh 55h 10h/ 30h tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAAh (Byte) for Chip Erase. Note: These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.) 36 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (6) AC Waveforms for Data Polling during Embedded Algorithm Operations CE tCH tDF tOE OE tOEH WE tCE * DQ7 Data DQ7 = Valid Data DQ7 High-Z tWHWH1 or 2 DQ6 to DQ0 = Output Flag Data DQ6 to DQ0 tBUSY DQ6 to DQ0 High-Z Valid Data (tEOE) RY/BY * : DQ7 = Valid Data (The device has completed the Embedded operation.) (7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations CE tOEH WE tOES OE * tDH DQ6 DQ6 = Toggle Data tBUSY DQ6 = Toggle DQ6 = Stop Toggling DQ7 to DQ0 Data Valid tOE RY/BY * : DQ6 = Stops toggling. (The device has completed the Embedded operation.) 37 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (8) RY/BY Timing Diagram during Program/Erase Operations CE Rising edge of the last WE signal WE Entire programming or erase operations RY/BY tBUSY (9) RESET, RY/BY Timing Diagram WE RESET tRP tRB RY/BY tREADY (10) Timing Diagram for Word Mode Configuration CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH DQ15/A-1 38 Data Output (DQ14 to DQ0) tFHQV A-1 DQ15 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (11) Timing Diagram for Byte Mode Configuration CE BYTE tELFL Data Output (DQ7 to DQ0) Data Output (DQ14 to DQ0) DQ14 to DQ0 tACC A -1DQ15 DQ15/A-1 A-1 tFLQZ (12) BYTE Timing Diagram for Write Operations CE Falling edge of the last WE signal WE Input Valid BYTE tAS tAH 39 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (13) AC Waveforms for Sector Protection Timing Diagram A19, A18, A17 A16, A15, A14 A13, A12 SPAX SPAY A0 A1 A6 VID VIH A9 tVLHT VID VIH OE tVLHT tVLHT tWPP WE tOESP tVLHT tCSP CE 01h Data tVCS VCC SPAX = Sector Address for initial sector SPAY = Sector Address for next sector Note : A-1 is VIL on byte mode. 40 tOE MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (14) Extended Sector Protection Timing Diagram VCC RESET tVCS tVIDR tVLHT tWC Address tWC SPAX SPAX SPAY A0 A1 A6 CE OE tWP TIME OUT WE Data 60h 60h 40h 01h 60h tOE SPAX : Sector Address to be protected SPAY : Next Sector Address to be protected TIME-OUT : Time-out Window = 150 µs (Min) 41 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (15) Temporary Sector Unprotection Timing Diagram VCC tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection period (16) DQ2 vs. DQ6 Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program DQ6 DQ2* Toggle DQ2 and DQ6 with OE or CE * : DQ2 is read from the erase-suspended sector. 42 Erase Resume Erase Suspend Read Erase Erase Complete MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ FLOW CHART (1) Embedded ProgramTM Algorithm EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling NO Verify Data ? Embedded Program Algorithm in progress YES Increment Address NO Last Address ? YES Programming Completed Program Command Sequence (Address/Command) : 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : • The sequence is applied for ×16 mode. • The addresses differ from ×8 mode. 43 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (2) Embedded EraseTM Algorithm EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling NO Embedded Erase Algorithm in Progress Data = FFh ? YES Erasure Completed Chip Erase Command Sequence (Addresss/Command) : Individual Sector/Multiple Sector Erase Command Sequence (Address/Command) : 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Note : The sequence is applied for ×16 mode. The addresses differ from ×8 mode. 44 Additional sector erase commands are optional. MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (3) Data Polling Algorithm Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes VA =Address for programming =Any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. =Any of the sector addresses within the sector not being protected during chip erases operation. No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * Yes No Fail Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 45 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (4) Toggle Bit Algorithm Start Read (DQ7 to DQ0) Addr. = “H” or “L” Read (DQ7 to DQ0) Addr. = “H” or “L” DQ6 = Toggle ? *1 *1 No Yes No DQ5 = 1 ? Yes *1, *2 Read (DQ7 to DQ0) Addr. = “H” or “L” *1, *2 Read (DQ7 to DQ0) Addr. = “H” or “L” DQ6 = Toggle ? YES Program/Erase Operation Not Complete. Write Reset Command NO Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. 46 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (5) Sector Protection Algorithm Start Setup Sector Addr. (A19, A18, A17, A16, A15, A14, A13, A12) PLSCNT = 1 OE = VID, A9 = VID A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector ( A1 = VIH, A0 = VIL, Addr. = SA, A6 = VIL)* No No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command Data = 01h? Yes Protect Another Sector? No Device Failed Remove VID from A9 Write Reset Command Sector Protection Completed * : A-1 is VIL on byte mode. 47 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (6) Temporary Sector Unprotection Algorithm Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. 48 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (7) Embedded Programming Algorithm for Fast Mode FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXXh/A0h Program Address/Program Data In Fast Program Data Polling Verify Data? No Yes No Increment Address Last Address ? Yes Programming Completed XXXXh/90h Reset Fast Mode XXXXh/F0h Notes : • The sequence is applied for ×16 mode. • The addresses differ from ×8 mode. 49 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (8) Extended Sector Protect Algorithm FAST MODE ALGORITHM Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Unprotect No Mode Extended Sector Protect Entry? Yes To Setup Sector Protect Write XXXh/60h PLSCNT = 1 To Sector Protect Write 60h to Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) Time out 150 µs To Verify Sector Protect Write 40h to Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) Increment PLSCNT Read from Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) No Setup Next Sector Address No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01h? Yes Yes Protect Other Sector ? No Remove VID from RESET Write Reset Command Device Failed Sector Protection Completed 50 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ ORDERING INFORMATION MBM29LV160 T -80 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP (1) ) Normal Bend PFTR = 48-Pin Thin Small Outline Package (TSOP (1) ) Reverse Bend PCV = 48-Pin C- leaded Small Outline Package (CSOP) PBT- SF2= 48-Pin Fine Pitch Ball Grid Array Package (FBGA:BGA-48P-M13) SPEED OPTION See Product Selector Guide BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29LV160 16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Flash Memory 3.0 V-only Read, Write, and Erase 51 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Part No. 52 Package Access Time (ns) MBM29LV160T-80PFTN MBM29LV160T-90PFTN MBM29LV160T-12PFTN 48-pin plastic TSOP(1) (FPT-48P-M19) (Normal Bend) 80 90 120 MBM29LV160T-80PFTR MBM29LV160T-90PFTR MBM29LV160T-12PFTR 48-pin plastic TSOP(1) (FPT-48P-M20) (Reverse Bend) 80 90 120 MBM29LV160T-80PCV MBM29LV160T-90PCV MBM29LV160T-12PCV 48-pin plastic CSOP (LCC-48P-M03) 80 90 120 MBM29LV160T-80PBT MBM29LV160T-90PBT MBM29LV160T-12PBT 48-ball plastic FBGA (BGA-48P-M13) 80 90 120 MBM29LV160B-80PFTN MBM29LV160B-90PFTN MBM29LV160B-12PFTN 48-pin plastic TSOP(1) (FPT-48P-M19) (Normal Bend) 80 90 120 MBM29LV160B-80PFTR MBM29LV160B-90PFTR MBM29LV160B-12PFTR 48-pin plastic TSOP(1) (FPT-48P-M20) (Reverse Bend) 80 90 120 MBM29LV160B-80PCV MBM29LV160B-90PCV MBM29LV160B-12PCV 48-pin plastic CSOP (LCC-48P-M03) 80 90 120 MBM29LV160B-80PBT MBM29LV160B-90PBT MBM29LV160B-12PBT 48-ball plastic FBGA (BGA-48P-M13) 80 90 120 Sector Architecture Top Sector Bottom Sector MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" 0.10(.004) (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) +0.03 0.17 –0.08 +.001 .007 –.003 C 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.22±0.05 (.009±.002) 0.10(.004) M 2003 FUJITSU LIMITED F48029S-c-6-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 53 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15 (.006) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP (1) (FPT-48P-M20) LEAD No. 1 48 Details of "A" part INDEX 0.60±0.15 (.024±.006) 0~8˚ 0.25(.010) 24 25 +0.03 0.17 –0.08 +.001 0.10(.004) .007 –.003 0.50(.020) 0.22±0.05 (.009±.002) M 0.10±0.05 (.004±.002) (Stand off height) +0.10 "A" 1.10 –0.05 +.004 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) C 0.10(.004) .043 –.002 (Mounting height) * 12.00±0.20(.472±.008) 2003 FUJITSU LIMITED F48030S-c-6-7 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 54 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max) . Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width includes plating thickness. Note 4) Pins width do not include tie bar cutting remainder. 48-pin plastic CSOP (LCC-48P-M03) "A" 25 48 10.00±0.20 (.394±.008) *2 9.50±0.10 (.374±.004) INDEX INDEX 0.05 +0.05 –0 +.002 –.0 .002 (Stand off) LEAD No. 1 24 *1 10.00±0.10(.394±.004) 0.95±0.05(.037±.002) (Mounting height) 0.22±0.035 (.009±.001) Details of "A" part 0˚~10˚ 0.40(.016) 0.08(.003) 0.65(.026) 1.15(.045) 9.20(.362)REF C 2003 FUJITSU LIMITED C48056S-c-2-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. (Continued) 55 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 (Continued) 48-ball plastic FBGA (BGA-48P-M13) +0.15 9.00±0.20(.354±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) 5.60(.220) 0.80(.031)TYP 6 5 8.00±0.20 (.315±.008) 4 4.00(.157) 3 INDEX 2 1 H C0.25(.010) G F E D 48-ø0.45±0.10 (48-ø.018±.004) C B A ø0.08(.003) M 0.10(.004) C 2001 FUJITSU LIMITED B48013S-c-3-2 Dimensions in mm (inches) Note : The values in parentheses are reference values. 56 MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0306 FUJITSU LIMITED Printed in Japan