SEMICONDUCTOR TECHNICAL DATA The MC10138 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set–reset master–slave flip–flops. Clock inputs trigger on the positive going edge of the clock pulse. Set or reset input override the clock, allowing asynchronous “set” or “clear.” Individual set and common reset inputs are provided, as well as complementary outputs for the first and fourth bits. L SUFFIX CERAMIC PACKAGE CASE 620–10 PD = 370 mW typ/pkg (No Load) ftog = 150 MHz typ tr, tf = 2.5 ns typ (20%–80%) P SUFFIX PLASTIC PACKAGE CASE 648–08 LOGIC DIAGRAM S0 Q0 11 S1 15 S D1 12 Clock C1 Q1 10 13 S2 Q2 6 S S3 4 Q3 5 S 2 S Q D1 Q D1 Q D1 Q’ Q’ D2 Q’ C1 Q’ D2 Q Q C2 Q C2 Q C2 Q R R R FN SUFFIX PLCC CASE 775–02 DIP PIN ASSIGNMENT R 9 Reset 14 Q0 C2 7 3 VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8 BCD (Clock connected to C1 and Q0 connected to C2) COUNT Q1 Q2 Q3 Q0 COUNT Q0 Q1 Q2 Q3 0 1 2 3 L H L H L L H H L L L L L L L L 0 1 2 3 L H L H L L H H L L L L L L L L 4 5 6 7 L L H L L L L H H L L L L H H H 4 5 6 7 L H L H L L H H H H H H L L L L 8 9 H L H L L H H H 8 9 L H L L L L H H Q0 CONNECTED TO C2 0 4 0 7 1 5 1 2 3 14 10 11 15 12 13 8 7 6 4 6 3 9 2 5 3/93 Motorola, Inc. 1996 3–41 16 VCC2 Q3 2 15 Q0 Q3 3 14 Q0 Q2 4 13 Q1 S3 5 12 C1 S2 6 11 S0 C2 7 10 S1 VEE 8 9 RESET Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). COUNTER STATE DIAGRAM — POSITIVE LOGIC CLOCK CONNECTED TO C2 1 Q3 COUNTER TRUTH TABLES BI–QUINARY (Clock connected to C2 and Q3 connected to C1) VCC1 REV 5 MC10138 ELECTRICAL CHARACTERISTICS Test Limits Characteristic Power Supply Drain Current Input Current Symbol Pin Pi Under Test IE 8 97 IinH 12 5,6,10,11 7 9 350 390 460 650 –30°C Min +25°C Max Min +85°C Max Unit 88 97 mAdc 220 245 290 410 220 245 290 µAdc Typ Max 70 µAdc IinL All 0.5 Output Voltage Logic 1 VOH 3,14 (3.) 2,4,13,15 (2.) –1.060 –1.060 –0.890 –0.890 –0.960 –0.960 –0.810 –0.810 –0.890 –0.890 –0.700 –0.700 Vdc Output Voltage Logic 0 VOL 3,14 (2.) 2,4,13,15 (3.) –1.890 –1.890 –1.675 –1.675 –1.850 –1.850 –1.650 –1.650 –1.825 –1.825 –1.615 –1.615 Vdc Threshold Voltage Logic 1 VOHA 2,4,13,15 (2.) 3,14 (3.) 13,15 (2.) –1.080 –1.080 –1.080 Threshold Voltage Logic 0 VOLA 2,4,13,15 (3.) 3,14 (2.) 13,15 (3.) Switching Times Propagation Delay 0.5 Min 0.3 –0.980 –0.980 –0.980 –0.910 –0.910 –0.910 –1.655 –1.655 –1.655 –1.630 –1.630 –1.630 Vdc –1.595 –1.595 –1.595 (50Ω Load) Clock Delays ns t12+15+ t12+14+ t7+13+ t7+4+ t7+2+ t7+3+ 15 14 13 4 2 3 1.4 1.4 1.4 1.4 1.4 1.4 5.0 5.0 5.2 5.2 5.2 5.2 1.5 1.5 1.5 1.5 1.5 1.5 3.5 3.5 3.5 3.5 3.5 3.5 4.8 4.8 5.0 5.0 5.0 5.0 1.5 1.5 1.5 1.5 1.5 1.5 5.3 5.3 5.5 5.5 5.5 5.5 t12+15– t12+14– t7+13– t7+4– t7+2– t7+3– 15 14 13 4 2 3 1.4 1.4 1.4 1.4 1.4 1.4 5.0 5.0 5.2 5.2 5.2 5.2 1.5 1.5 1.5 1.5 1.5 1.5 3.5 3.5 3.5 3.5 3.5 3.5 4.8 4.8 5.0 5.0 5.0 5.0 1.5 1.5 1.5 1.5 1.5 1.5 5.3 5.3 5.5 5.5 5.5 5.5 Set Delay t11+15+ t11+14– 15 14 1.4 1.4 5.2 5.2 1.5 1.5 5.0 5.0 1.5 1.5 5.5 5.5 Reset Delay t9+14+ t9+15– 14 15 1.4 1.4 5.2 5.2 1.5 1.5 5.0 5.0 1.5 1.5 5.5 5.5 Rise Time (20 to 80%) t14+ t15+ 14 15 1.1 1.1 4.7 4.7 1.1 1.1 2.5 2.5 4.5 4.5 1.1 1.1 5.0 5.0 Fall Time (20 to 80%) t14– t15– 14 15 1.1 1.1 4.7 4.7 1.1 1.1 2.5 2.5 4.5 4.5 1.1 1.1 5.0 5.0 fcount 2 15 125 125 125 125 150 150 Counting Frequency Vdc 1. Individually test each input; apply VILmin to pin under test. VIHmax 2. Set all four flip–flops by applying pulse 3. Reset all four flip–flops by applying pulse VILmin VIHmax 125 125 MHz to pins 5, 6, 10, and 11 prior to applying test voltage indicated. to pin 9 prior to applying test voltage indicated. VILmin MOTOROLA 3–42 MECL Data DL122 — Rev 6 MC10138 ELECTRICAL CHARACTERISTICS (continued) NOTE: Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. O Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test p procedures are shown for only one gate. gate The other gates are tested in the same manner. Characteristic TEST VOLTAGE VALUES (Volts) @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Power Supply Drain Current Input Current TEST VOLTAGE APPLIED TO PINS LISTED BELOW Pin Under Test VIHmax VILmin VIHAmin VILAmax VEE (VCC) Gnd IE 8 9 8 1, 16 IinH 12 5,6,10,11 7 9 12 5,6,10,11 7 9 8 8 8 8 1, 16 1, 16 1, 16 1, 16 IinL All 8 1, 16 Note 1. Output Voltage Logic 1 VOH 3,14 (3.) 2,4,13,15 (2.) 9 5,6,10,11 8 8 1, 16 1, 16 Output Voltage Logic 0 VOL 3,14 (2.) 2,4,13,15 (3.) 5,6,10,11 9 8 8 1, 16 1, 16 Threshold Voltage Logic 1 VOHA 2,4,13,15 (2.) 3,14 (3.) 13,15 (2.) 8 8 8 1, 16 1, 16 1, 16 Threshold Voltage Logic 0 VOLA 2,4,13,15 (3.) 3,14 (2.) 13,15 (3.) 5,6,10,11 9 7,12 8 8 8 1, 16 1, 16 1, 16 Pulse In Pulse Out –3.2 V +2.0 V Switching Times Propagation Delay 5,6,10,11 9 7,12 (50Ω Load) Clock Delays t12+15+ t12+14+ t7+13+ t7+4+ t7+2+ t7+3+ 15 14 13 4 2 3 12 12 7 7 7 7 15 14 13 4 2 3 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 t12+15– t12+14– t7+13– t7+4– t7+2– t7+3– 15 14 13 4 2 3 12 12 7 7 7 7 15 14 13 4 2 3 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 Set Delay t11+15+ t11+14– 15 14 11 11 15 14 8 8 1, 16 1, 16 Reset Delay t9+14+ t9+15– 14 15 9 9 14 15 8 8 1, 16 1, 16 Rise Time (20 to 80%) t14+ t15+ 14 15 11 11 14 15 8 8 1, 16 1, 16 Fall Time (20 to 80%) t14– t15– 14 15 9 9 14 15 8 8 1, 16 1, 16 fcount 2 15 7 12 2 15 8 8 1, 16 1, 16 Counting Frequency 1. Individually test each input; apply VILmin to pin under test. VIHmax 2. Set all four flip–flops by applying pulse 3. Reset all four flip–flops by applying pulse VILmin VIHmax to pins 5, 6, 10, and 11 prior to applying test voltage indicated. to pin 9 prior to applying test voltage indicated. VILmin MECL Data DL122 — Rev 6 3–43 MOTOROLA MC10138 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C 0.007 (0.180) M T L–M B Y BRK –N– U N S 0.007 (0.180) M T L–M S S N S D –L– –M– Z W 20 D 1 V 0.010 (0.250) G1 X S T L–M N S S VIEW D–D A 0.007 (0.180) M T L–M S N S R 0.007 (0.180) M T L–M S N S Z C H –T– SEATING PLANE F VIEW S G1 0.010 (0.250) S T L–M S 0.007 (0.180) M T L–M S N S VIEW S S N S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA N K 0.004 (0.100) J S K1 E G 0.007 (0.180) M T L–M 3–44 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10 _ 0.310 0.330 0.040 ––– MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10 _ 7.88 8.38 1.02 ––– MECL Data DL122 — Rev 6 MC10138 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M –A– 9 1 8 B F C L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R 16 S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 T A M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 ◊ MECL Data DL122 — Rev 6 3–45 *MC10138/D* MC10138/D MOTOROLA