MOTOROLA MC74HC165N

SEMICONDUCTOR TECHNICAL DATA
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High–Performance Silicon–Gate CMOS
The MC54/74HC165 is identical in pinout to the LS165. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 286 FETs or 71.5 Equivalent Gates
D SUFFIX
SOIC PACKAGE
CASE 751B–05
16
1
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
LOGIC DIAGRAM
A
B
PARALLEL
DATA
INPUTS
C
11
PIN ASSIGNMENT
12
9
13
D 14
E 3
7
QH
SERIAL
DATA
OUTPUTS
QH
SERIAL SHIFT/
PARALLEL LOAD
CLOCK
1
16
VCC
2
15
CLOCK INHIBIT
E
3
14
D
F
4
13
C
G
5
12
B
H
6
11
A
QH
7
10
SA
GND
8
9
QH
F 4
G 5
SERIAL
DATA
INPUT
H 6
SA 10
SERIAL SHIFT/PARALLEL LOAD
PIN 16 = VCC
PIN 8 = GND
1
CLOCK 2
15
CLOCK INHIBIT
Serial Shift/
Parallel Load
L
FUNCTION TABLE
Inputs
Clock
Inhibit
Clock
X
H
H
Internal Stages
SA
X
A–H
QA
QB
QH
X
a…h
a
b
h
L
L
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock
Operation
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock Inhibit
Asynchronous Parallel Load
H
H
L
L
H
H
X
H
H
X
X
X
X
X
No Change
Inhibited Clock
H
L
L
X
X
No Change
No Clock
X = don’t care
QAn – QGn = Data shifted from the preceding stage
10/95
 Motorola, Inc. 1995
Output
1
REV 6
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MC54/74HC165
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
09
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
6.0
± 0.1
± 1.0
± 1.0
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
Maximum Input Leakage Current
4.0 mA
5.2 mA
Vin = VCC or GND
4.0 mA
5.2 mA
µA
Vin = VCC or GND
6.0
8
80
160
µA
Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ICC
MOTOROLA
Maximum Quiescent Supply
Current (per Package)
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HC165
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH
(Figures 1 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH
(Figures 2 and 8)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
Maximum Propagation Delay, Input H to QH or QH
(Figures 3 and 8)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Cin
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
85
pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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MC54/74HC165
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
85_C
125_C
tsu
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tsu
Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
tw
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tw
Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
Symbol
trec
tr, tf
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip–flops when the
Serial Shift/Parallel Load input is low.
Clock, Clock Inhibit (Pins 2, 15)
Serial Data input. When the Serial Shift/Parallel Load input
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.
Clock inputs. These two clock inputs function identically.
Either may be used as an active–high clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock input is high.
The shift register is completely static, allowing Clock rates
down to DC in a continuous or intermittent mode.
CONTROL INPUTS
OUTPUTS
Serial Shift/Parallel Load (Pin 1)
QH, QH (Pins 9, 7)
Data–entry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is
Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.
SA (Pin 10)
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC165
SWITCHING WAVEFORMS
tr
CLOCK
OR CLOCK INHIBIT
tf
VCC
90%
50%
10%
tw
GND
SERIAL SHIFT/
PARALLEL LOAD
tw
1/fmax
tPLH
GND
QH OR QH
tTLH
tPHL
tPLH
tPHL
90%
50%
10%
QH OR QH
VCC
50%
50%
50%
tTHL
Figure 1. Serial–Shift Mode
Figure 2. Parallel–Load Mode
VALID
tr
VCC
tf
90%
50%
10%
INPUT H
INPUTS A–H
VCC
50%
GND
GND
tPLH
tsu
tPHL
90%
50%
10%
QH OR QH
th
VCC
SERIAL SHIFT/
PARALLEL LOAD
tTLH
GND
tTHL
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)
Figure 3. Parallel–Load Mode
Figure 4. Parallel–Load Mode
VALID
SERIAL SHIFT/
PARALLEL LOAD
VCC
INPUT SA
50%
VCC
50%
GND
GND
tsu
tsu
th
VCC
CLOCK
OR CLOCK INHIBIT
VCC
CLOCK
OR CLOCK INHIBIT
50%
th
50%
GND
GND
Figure 5. Serial–Shift Mode
Figure 6. Serial–Shift Mode
TEST POINT
CLOCK 2 INHIBITED
CLOCK INHIBIT
OUTPUT
VCC
DEVICE
UNDER
TEST
50%
GND
tsu
CLOCK
CL*
trec
VCC
50%
GND
* Includes all probe and jig capacitance
Figure 7. Serial–Shift, Clock–Inhibit Mode
High–Speed CMOS Logic Data
DL129 — Rev 6
Figure 8. Test Circuit
5
MOTOROLA
MC54/74HC165
EXPANDED LOGIC DIAGRAM
A
B
11
C
12
F
13
G
4
H
5
6
SERIAL SHIFT/
1
PARALLEL LOAD
9 Q
H
SERIAL DATA 10
INPUT SA
D QA
D QB
D QC
D QF
D QG
D QH
C C
C C
C C
C C
C C
C C
7 Q
H
CLOCK 2
CLOCK 15
INHIBIT
TIMING DIAGRAM
CLOCK
CLOCK INHIBIT
SA
SERIAL SHIFT/
PARALLEL LOAD
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
PARALLEL
DATA
INPUTS
QH
QH
H H
L
H
L
H
L
H
L L
H
L
H
L
H
L
CLOCK
INHIBIT
MODE
SERIAL–SHIFT MODE
PARALLEL LOAD
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC165
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
ISSUE V
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
–B
–
L
C
DIM
A
B
C
D
E
F
G
J
K
L
M
N
–T
K
N
SEATING
–
PLANE
E
M
F
J 16 PL
0.25 (0.010)
G
D 16 PL
0.25 (0.010)
T A
M
9
1
8
T B
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
M
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A
–
16
1
P 8 PL
0.25 (0.010)
8
M
B
M
G
K
F
R X 45°
C
–T
SEATING
–
PLANE
J
M
D 16 PL
0.25 (0.010)
High–Speed CMOS Logic Data
DL129 — Rev 6
M
T
B
S
A
S
7
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B
–
MILLIMETERS
MIN
MAX
19.05 19.93
6.10
7.49
—
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
15°
0°
1.01
0.51
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
S
S
INCHES
MIN
MAX
0.750 0.785
0.240 0.295
—
0.200
0.015 0.020
0.050 BSC
0.055 0.065
0.100 BSC
0.008 0.015
0.125 0.170
0.300 BSC
15°
0°
0.020 0.040
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80 10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019
MOTOROLA
MC54/74HC165
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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*MC54/74HC165/D*
MC54/74HC165/D
High–Speed CMOS Logic Data
DL129 — Rev 6