SEMICONDUCTOR TECHNICAL DATA #*#!' ' ' " %"& )% ' #!%"' "$('& " ('$('& '' #"")%' " The MC74LCX16543 is a high performance, non–inverting 16–bit latching transceiver operating from a 2.7 to 3.6V supply. The device is byte controlled. Each byte has separate control inputs which can be tied together for full 16–bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX16543 inputs to be safely driven from 5V devices. The MC74LCX16543 is suitable for memory address driving and all TTL level bus oriented transceiver applications. LOW–VOLTAGE CMOS 16–BIT LATCHING TRANSCEIVER For data flow from A to B with the EAB LOW, the A–to–B Output Enable (OEAB) must be LOW in order to enable data to the B bus, as indicated in the Function Table. With EAB LOW, a LOW signal on the A–to–B Latch Enable (LEAB) input makes the A–to–B latches transparent; a subsequent LOW–to–HIGH transition of the LEAB signal will latch the A latches, and the outputs no longer change with the A inputs. With EAB and OEAB both LOW, the 3–State B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is symetric to that above, but uses the EBA, LEBA, and OEBA inputs. • • • • • • • • • DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1202–01 Designed for 2.7 to 3.6V VCC Operation 5.2ns Maximum tpd 5V Tolerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible PIN NAMES LVCMOS Compatible Pins Function 24mA Balanced Output Sink and Source Capability OExxn Exxn LExxn A0–A15 B0–B15 Output Enable Inputs Enable Inputs Latch Enable Inputs 3–State Inputs/Outputs 3–State Inputs/Outputs Near Zero Static Supply Current in All Three Logic States (20µA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500mA • ESD Performance: Human Body Model >2000V; Machine Model >200V This document contains information on a new product. Specifications and information herein are subject to change without notice. 11/96 Motorola, Inc. 1996 1 REV 0.2 MC74LCX16543 LOGIC DIAGRAM Pinout: 56-Lead TSSOP (Top View) DETAIL A D 52 B0 Q LE D 5 A0 Q LE DETAIL A x 7 1 54 OEAB1 EAB1 3 LEAB1 LEBA1 55 2 DETAIL B D 42 B8 Q LE 15 A8 LEBA2 LEAB1 2 55 LEBA1 EAB1 3 54 EBA1 GND 4 53 GND A0 5 52 B0 A1 6 51 B1 50 VCC A2 8 49 B2 A3 9 48 B3 A4 10 47 B4 GND 11 46 GND A5 12 45 B5 A6 13 44 B6 A7 14 43 B7 A8 15 42 B8 A9 16 41 B9 A10 17 40 B10 GND 18 39 GND D A11 19 38 B11 LE A12 20 37 B12 A13 21 36 B13 VCC 22 35 VCC A14 23 34 B14 A15 24 33 B15 Q DETAIL Bx 7 OEBA2 EBA2 56 OEBA1 VCC 7 56 OEBA1 EBA1 OEAB1 1 29 28 31 26 30 27 OEAB2 EAB2 GND 25 32 GND EAB2 26 31 EBA2 LEAB2 27 30 LEBA2 OEAB2 28 29 OEBA2 LEAB2 MOTOROLA 2 LCX DATA BR1339 — REV 3 MC74LCX16543 FUNCTION TABLE Inputs OEABn OEBAn H H L EABn Data Ports EBAn LEBAn An Bn Input Input Operating Mode X X X X X X Disable Outputs L L L L X X Transparent Data; Outputs Disabled H H l h l h Latch and Outputs Disabled Input Output H H X* L H LEABn X* L X l h Z Z Load and B Outputs Disabled H X X Z Hold; B Outputs Disabled L X L H L H Transparent A to B H X l h L H Latch and Display B Outputs Output Input X L Z Z l h Load and A Outputs Disabled X H Z X Hold; A Outputs DIsabled X L L H L H Transparent B to A X H L H l h Latch and Display A Outputs L X* H X* L H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; L = Low Voltage Level; l = Low Voltage Level One Setup Time Prior to the Latch Enable or Enable Low–to–High Transition; X = Don’t Care; * = The latches are not internally gated with the Output Enables. Therefore, data at the A or B ports may enter the latches at any time, provided that the LExx and Exx pins are set accordingly. For ICC reasons, Do Not Float Inputs. ABSOLUTE MAXIMUM RATINGS* Symbol Parameter VCC DC Supply Voltage VI VO Value Condition Unit –0.5 to +7.0 V DC Input Voltage –0.5 ≤ VI ≤ +7.0 V DC Output Voltage –0.5 ≤ VO ≤ +7.0 Output in 3–State V –0.5 ≤ VO ≤ VCC + 0.5 Note 1. V IIK DC Input Diode Current –50 VI < GND mA IOK DC Output Diode Current –50 VO < GND mA +50 VO > VCC mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range –65 to +150 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. 1. Output in HIGH or LOW State. IO absolute maximum rating must be observed. LCX DATA BR1339 — REV 3 3 MOTOROLA MC74LCX16543 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Operating Data Retention Only Min Typ Max Unit 2.0 1.5 3.3 3.3 3.6 3.6 V 0 5.5 V 0 0 VCC 5.5 V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH HIGH Level Output Current, VCC = 3.0V – 3.6V –24 mA IOL LOW Level Output Current, VCC = 3.0V – 3.6V 24 mA IOH HIGH Level Output Current, VCC = 2.7V – 3.0V –12 mA IOL LOW Level Output Current, VCC = 2.7V – 3.0V 12 mA TA Operating Free–Air Temperature –40 +85 °C ∆t/∆V Input Transition Rise or Fall Rate, VIN from 0.8V to 2.0V, VCC = 3.0V 0 10 ns/V (HIGH or LOW State) (3–State) DC ELECTRICAL CHARACTERISTICS TA = –40°C to +85°C Symbol Characteristic Condition Min 2.0 VIH HIGH Level Input Voltage (Note 2.) 2.7V ≤ VCC ≤ 3.6V VIL LOW Level Input Voltage (Note 2.) 2.7V ≤ VCC ≤ 3.6V VOH HIGH Level Output Voltage VOL LOW Level Output Voltage Max V 0.8 2.7V ≤ VCC ≤ 3.6V; IOH = –100µA VCC – 0.2 VCC = 2.7V; IOH = –12mA 2.2 VCC = 3.0V; IOH = –18mA 2.4 VCC = 3.0V; IOH = –24mA 2.2 Unit V V 2.7V ≤ VCC ≤ 3.6V; IOL = 100µA 0.2 VCC = 2.7V; IOL= 12mA 0.4 VCC = 3.0V; IOL = 16mA 0.4 VCC = 3.0V; IOL = 24mA 0.55 V II Input Leakage Current 2.7V ≤ VCC ≤ 3.6V; 0V ≤ VI ≤ 5.5V ±5.0 µA IOZ 3–State Output Current 2.7 ≤ VCC ≤ 3.6V; 0V ≤ VO ≤ 5.5V; VI = VIH or V IL ±5.0 µA IOFF Power–Off Leakage Current VCC = 0V; VI or VO = 5.5V 10 µA ICC Quiescent Supply Current 2.7 ≤ VCC ≤ 3.6V; VI = GND or VCC 20 µA 2.7 ≤ VCC ≤ 3.6V; 3.6 ≤ VI or VO ≤ 5.5V ±20 µA 500 µA ∆ICC Increase in ICC per Input 2.7 ≤ VCC ≤ 3.6V; VIH = VCC – 0.6V 2. These values of VI are used to test DC electrical characteristics only. MOTOROLA 4 LCX DATA BR1339 — REV 3 MC74LCX16543 AC CHARACTERISTICS (Note 3.; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω) Limits TA = –40°C to +85°C VCC = 3.0V to 3.6V Symbol Parameter VCC = 2.7V Waveform Min Max Min Max Unit tPLH tPHL Propagation Delay An to Bn or Bn to An 1 1.5 1.5 5.2 5.2 1.5 1.5 6.0 6.0 ns tPLH tPHL Propagation Delay LEBAn to An or LEABn to Bn 4 1.5 1.5 6.5 6.5 1.5 1.5 7.5 7.5 ns tPZH tPZL Output Enable Time OEBAn to An or OEABn to Bn 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 ns tPHZ tPLZ Output Disable Time OEBAn to An or OEABn to Bn 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 ns tPZH tPZL Output Enable Time EBAn to An or EABn to Bn 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 ns tPHZ tPLZ Output Disable Time EBAn to An or EABn to Bn 2 1.5 1.5 6.5 6.5 1.5 1.5 7.0 7.0 ns ts Setup Time, HIGH to LOW Data to LExxn 4 2.5 2.5 ns th Hold Time, HIGH to LOW Data to LExxn 4 1.5 1.5 ns ts Setup Time, HIGH to LOW Data to Exxn 4 2.5 2.5 ns th Hold Time, HIGH to LOW Data to Exxn 4 1.5 1.5 ns tw Latch Enable or Enable Pulse Width, LOW 4 3.0 3.0 ns tOSHL tOSLH Output–to–Output Skew (Note 4.) 1.0 1.0 ns 3. These AC parameters are preliminary and may be modified prior to release. The maximum AC limits are design targets. Actual performance will be specified upon completion of characterization. 4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (tOSHL) or LOW–to–HIGH (tOSLH); parameter guaranteed by design. DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol Characteristic Condition VOLP Dynamic LOW Peak Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V Min Typ 0.8 Max Unit V VOLV Dynamic LOW Valley Voltage (Note 5.) VCC = 3.3V, CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V 5. Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state. CAPACITIVE CHARACTERISTICS Symbol Parameter Condition Typical Unit CIN Input Capacitance VCC = 3.3V, VI = 0V or VCC 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance 10MHz, VCC = 3.3V, VI = 0V or VCC 20 pF LCX DATA BR1339 — REV 3 5 MOTOROLA MC74LCX16543 2.7V An or Bn 1.5V 0V tPLH, tPHL VOH Bn or An 1.5V VOL WAVEFORM 1 – A/B to B/A PROPAGATION DELAYS tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns 2.7V OExxn or Exxn 1.5V 1.5V 0V tPZH tPHZ VOH – 0.3V An or Bn 1.5V ≈ 0V tPZL An or Bn tPLZ ≈ 3.0V 1.5V VOL + 0.3V WAVEFORM 2 – OExx/Exx to A or B OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns Figure 1. AC Waveforms MOTOROLA 6 LCX DATA BR1339 — REV 3 MC74LCX16543 2.7V An or Bn 1.5V 0V tw NEGATIVE PULSE ts th 1.5V 1.5V 2.7V Exxn or LExxn tw 1.5V 1.5V 0V tPLH, tPHL POSITIVE PULSE VOH 1.5V 1.5V An or Bn tw 1.5V VOL WAVEFORM 3 – INPUT PULSE DEFINITION tR = tF = 2.5ns, 10% to 90% of 0V to 2.7V WAVEFORM 4 – Enable to A or B PROPAGATION DELAYS, Enable MINIMUM PULSE WIDTH, A or B to Enable SETUP AND HOLD TIMES tR = tF = 2.5ns, 10% to 90%; f = 1MHz; tW = 500ns except when noted Figure 2. AC Waveforms (continued) VCC PULSE GENERATOR R1 DUT CL RT TEST 6V OPEN GND RL SWITCH tPLH, tPHL Open tPZL, tPLZ 6V Open Collector/Drain tPLH and tPHL tPZH, tPHZ 6V GND CL = 50pF or equivalent (Includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 3. Test Circuit LCX DATA BR1339 — REV 3 7 MOTOROLA MC74LCX16543 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 1202–01 ISSUE A 56X K REF 0.12 (0.005) M T U S V K K1 S T U S J J1 29 0.254 (0.010) M 56 SECTION N–N B –U– L ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ 1 N 28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. A –V– PIN 1 IDENT. N F DETAIL E D C 0.25 (0.010) –W– 0.076 (0.003) –T– SEATING PLANE M DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 13.90 14.10 6.00 6.20 ––– 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.12 ––– 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0_ 8_ INCHES MIN MAX 0.547 0.555 0.236 0.244 ––– 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.005 ––– 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0_ 8_ H G Motorola reserves the right to make changes without further notice to any products herein. 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