MIC2150/MIC2151 2-Phase Dual Output PWM Synchronous Buck Control IC General Description Features The MIC2150/1 are simple 2-phase dual-output synchronous buck control ICs featuring small size and high efficiency. The ICs implement PWM control at 500kHz (MIC2150) or 300kHz (MIC2151), with the outputs switching 180° out of phase. The result of the out-of-phase operation is 1MHz input ripple frequency with ripple current cancellation, minimizing the required input filter capacitance. A 1% output voltage tolerance allows the maximum level of system performance. Internal drivers with adaptive gate drive allow the highest efficiency with the minimum external components. A dual threshold enable pin, matched soft-start pins, and a power good output are provided, allowing a high level of control. The MIC2150/1 are available in the small size 4mm×4mm 24-pin MLF® package. The MIC2150/1 has a junction operating range from –40°C to +125°C. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. • Dual Synchronous Buck Control IC with outputs switching 180 degree out-of-phase • 4.5V to 14.5V input voltage range • Adjustable output voltages down to 0.7V • 1% output voltage accuracy • MIC2150: 500kHz PWM operation • MIC2151: 300kHz PWM operation • Adaptive gate drive allows efficiencies over 95% • Adjustable current limit with no sense resistor - Senses low-side MOSFET current • Internal drivers allow 20A per phase • Power Good output allow simple sequencing • Dual threshold enable pin • Independent programmable soft-start pins • Output over-voltage protection • Input UVLO • Works with ceramic output capacitors • Tiny 4mm×4mm 24-Pin MLF® package • Junction temperature range of -40°C to +125°C Applications • • • • Multi-output power supplies with sequencing DSP, FPGA, CPU and ASIC power supplies Telecom and Networking equipment Servers _________________________________________________________________________________________________________________________ Typical Application MicroLead Frame and MLF are registered trademarks of Amkor Technology, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com August 2009 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Ordering Information Part Number Frequency Voltage Junction Temp. Range Lead Finish Package MIC2150YML 500kHz Adj. –40°C to +125°C Pb-Free 4mm×4mm 24-pin MLF MIC2151YML 300kHz Adj. –40°C to +125°C Pb-Free 4mm×4mm 24-pin MLF® ® Pin Configuration 24-Pin MLF® (ML) Pin Description Pin Number Pin Name Pin Function 1 BS1 2 HSD1 High-Side Drive 1 (Output): High current output-driver for ext. high-side MOSFET. 3 SW1 Switch Node 1(Output): High current output driver return for HSD1. 4 CS1 Current Sense 1 (Input): Current-limit comparator non-inverting input. The current limit is sensed across the low-side FET during the ON-time. Current limit is set by the resistor in series with the CS1 pin. 5 SS1 Soft-start, Output 1(Input): Controls the turn-on time of the output voltage. Active at power-up, Enable and Current Limit recovery. 6 COMP1 7 AGND 8 FB1 9 AVDD Boost 1(Input): Provides voltage for high-side MOSFET driver 1. The gate drive voltage is higher than the source voltage by VDD minus a diode drop. Compensation 1 (Input): Pin for external compensation, Channel 1. Analog Ground (Signal): Signal path return for FB, EN, PGOOD, AVDD, SS and COMP. Feedback 1 (Input): Input to Channel 1 error amplifier. Regulates to 0.7V. Analog Supply Voltage (Input): Connect ext. bypass capacitor. 10 FB2 11 PGOOD Power Good (Output): Indicates Channel 1 output AND Channel 2 output > 90% Nominal. 12 COMP2 Compensation 2 (Input): Pin for external compensation, Channel 2. August 2009 Feedback 2 (Input): Input to Channel 2 error amplifier. Regulates to 0.7V. 2 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Pin Number Pin Name Pin Function 13 SS2 Soft-start, Output 2(Input): Controls the turn-on time of the output voltage. Active at power-up, Enable and Current Limit recovery. 14 CS2 Current Limit 2 (Input): Current-limit comparator non-inverting input. The current limit is sensed across the low-side FET during the ON time. Current limit is set by the resistor in series with the CS2 pin. 15 SW2 Switch node 2 (Output): High current output driver return for HSD2. 16 HSD2 High-Side Drive 2 (Output): High current output-driver for the high-side MOSFET. 17 BS2 18 PGND2 19 LSD2 Low-Side Drive 2 (Output): High-current driver output for external MOSFET. 20 VDD 5V Internal Linear Regulator from VIN (Output): VDD is the ext. MOSFET gate drive supply voltage and an internal supply bus for the IC. When VIN is <5V, this regulator operates in drop-out mode. Connect external bypass capacitor. 21 EN Boost 2 (Input): Provides voltage for high-side MOSFET driver 2. The gate drive voltage is higher than the source voltage by VDD minus a diode drop. Power Ground 2. High current return for low-side driver 2 & CS2. Enable (Input): Dual threshold enable pin. Logic low turns the IC off. Exceeding lower threshold enables Channel 1, exceeding higher threshold then enables Channel 2. The dual threshold function allows the option of power up sequencing from a single EN pin. Both channels must be turned on and off together. The enable pin must be driven higher than 2.8V for proper operation. 22 VIN 23 LSD1 24 PGND1 EPAD EP August 2009 Supply voltage Channel 1 (Input): 4.5V to 14V Low-Side Drive 1 (Output): High-current driver output for external MOSFET. Power Ground 1: High current return for low-side driver 1 & CS1. Exposed Pad (Power): Must make a full connection to the GND plane to maximize thermal performance of the package. 3 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VIN) ........................................ –0.3V to 15V Bootstrap Pin Voltage (BST & HSD) ....................... VIN + 6V FB, COMP, SS, VDD, LSD & AVDD .................... –0.3V to 6V CS, SW & EN .................................................. –0.3V to 15V Power Good (PGOOD) ........................................ AVDD + 0.3V Storage Temperature (TS).........................–65°C to +150°C Lead Temperature (Soldering 10 seconds) ............... 260°C ESD Rating(3) .............HBM = 2kV, MM = 200V, CDM = 2kV Supply Voltage (VIN)................................... +4.5V to +14.5V Output Voltage Range................................ 0.7V to 0.83×VIN Junction Temperature Range ............. –40°C ≤ TJ ≤ +125°C Package Thermal Resistance MLF® (θJA)..........................................................60°C/W MLF® (θJC)............................................................6°C/W Electrical Characteristics(4) TJ = 25°C; VEN = VIN = 12V; unless otherwise specified. Bold values indicate –40°C ≤ TJ ≤ +125°C Parameter Condition Min Typ Max Units VIN , VEN, VDD Supply Total Supply Current, PWM mode supply current VFB = 0.7V (both O/Ps) (Outputs switching but excluding external MOSFET gate current.) 4.2 10 mA Shutdown Current VEN = 0V 50 100 μA VIN UVLO Start Voltage VIN rising 1.5 2.03 2.4 V VIN UVLO Stop Voltage VIN falling 1.5 2 2.4 V VDD UVLO Start Voltage VDD rising 3.0 VDD UVLO Stop Voltage VDD falling 2.8 VIN UVLO Hysteresis 30 VIN UVLO Hysteresis mV 3.3 3.6 V 3.1 3.4 V 200 mV VEN Threshold 1 0.8 1 1.2 V VEN Threshold 2 1.7 2 2.3 V VEN Hysteresis (each threshold) Internal Bias Voltages (VDD) IVDD = -50mA VDD Load Current 30 4.5 5 mV 5.5 V VIN = 6V to 14.5V 75 mA VIN = 5.5V 50 mA Oscillator / PWM Section PWM Frequency See design note (Internal Oscillator = 2X PWM frequency) Maximum Duty Cycle (Each Channel) Minimum On-Time (5,6) MIC2150 450 500 550 kHz MIC2151 270 300 330 kHz MIC2150 80 % MIC2151 83 % (Each Channel) 30 50 ns Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 4. Specification for packaged product only. 5. Minimum on-time before automatic cycle skipping begins. See applications section. 6. Guaranteed by design. August 2009 4 M9999-082809-A (408) 944-0800 Micrel, Inc. Parameter MIC2150 Condition Min Typ Max Units Feedback Voltage Reference (Each Channel) 25oC (Each Channel) –40°C to +125°C 691 686 700 709 714 mV Feedback Bias Current (Each Channel) 35 500 nA Output Voltage Line Regulation (Each Channel) 0.03 %/V 70 dB Regulation Error Amplifier (Each Channel) DC Gain (6) Output Over voltage Protection (each channel) VFB threshold (Latches LSD High) 110 Delay Blanking time 115 120 %Nom μs 2 Soft-Start Internal Soft-Start source current (each channel) VSS = 1V Soft-Start source current matching between channels Internal Soft-Start discharge current (each channel) 1.25 1 2 2.75 3 μA –30 0 30 % During Soft Current Limit μA 18 Current Sense (Each Channel) CS Over Current Trip Point program current 170 200 230 μA CS comparator sense threshold –7 0 +7 mV 90 93 %Nom 0.1 0.3 V Power Good VFB threshold PGOOD voltage low 86 VIN = 4.5V, VFB = 0 V; IPGOOD = 1mA Output Dynamic Correction Thresholds Upper Threshold, VFB_OVT (6) (relative to VFB). +6.5 % Lower Threshold, VFB_UVT (6) (relative to VFB). –6.5 % Rise 23 ns Fall 16 ns Source 1.5 3 Ω Sink 1.5 2 Ω Source 1.5 3 Ω Sink 1.5 2 Ω Gate Drivers Rise/Fall Time Into 3000pF Low-Side Drive Resistance VIN = 5V High-Side Drive Resistance VIN = 5V Notes: 6. Guaranteed by design. August 2009 5 M9999-082809-A (408) 944-0800 Micrel, Inc. Parameter MIC2150 Condition Min Typ 10 20 ns MIC2150 40 60 ns MIC2151 70 100 ns Driver non-overlap time (adaptive)(6) Driver non-overlap time between low-side off and high-side on(6) Max Units Notes: 6. Guaranteed by design. August 2009 6 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Typical Characteristics CS Pin Source Current vs Temperature 1.90 1.80 1.70 0 95% 2 4 6 8 10 12 14 16 INPUT VOLTAGE (V) IN 90% 85% 75% 70% 65% V OUT = 1.8V 5 10 15 20 OUTPUT CURRENT (A) August 2009 20 140 116% 114% 112% 110% 1 95% 90% VIN = 12V 80% 60% 0 120% 118% = 5V VIN = 9V OVP Threshold vs. Reaction Time 126% 124% 122% Efficiency vs. Output Current V 1.00 CH1 Off 0.95 0.90 0.85 0.80 0 2 85% 10 100 TPULSE (µs) 1000 VIN = 11V 80% 75% 70% 65% 60% 0 VOUT = 3.3V 5 10 15 20 OUTPUT CURRENT (A) 7 Power Good Thresholds vs. Input Voltage 91% PG HIGH 89% 87% PG LOW 85% 83% 81% 0 2 4 6 8 10 12 14 16 INPUT VOLTAGE (V) Max. Duty Cycle vs. V Efficiency vs. Output Current VIN = 7V 93% 4 6 8 10 12 14 16 INPUT VOLTAGE (V) SS 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 2.2 CH2 Off 1.05 0.6 2.00 TRIP VOLTAGE (% of VREF) CH2 On 130% 128% EFFICIENCY (%) ENABLE THRESHOLD (V) 2.30 2.10 CH1 On 1.10 TEMPERATURE (°C) CH2 Enable Thresholds vs. Input Voltage 2.20 0 4.5 I = -50mA VDD 4.4 -20 4.6 1 5 10 15 20 INPUT VOLTAGE (V) 120 4.7 2 0 0 EFFICIENCY (%) VIN = 5V 4.8 1.15 0.4 EN = 1.5V 3 VIN = 6V 4.9 VFB FOR PG TRANSITION (% of VREF) 4 1.20 = 7V DUTY CYCLE (%) EN = 2.5V IN 15 2.0 5 V 1.8 6 5 CH1 Enable Thresholds vs. Input Voltage ENABLE THRESHOLD (V) 5.1 0 0 120 ENABLED 20 VDD Regulator vs. Temperature 5.2 7 40 5 10 INPUT VOLTAGE (V) 100 Input Current vs. Input Voltage 60 TEMPERATURE (°C) 80 10 12 14 16 VIN (V) 80 160 8 60 6 40 4 -40 INPUT CURRENT (mA) 8 2 -40 170 0 100 170 60 180 40 180 0 190 20 190 -20 200 80 1.6 200 1.4 210 EN = 0 100 1.2 210 120 VIN = 14.5V 1.0 220 Input Current vs. Input Voltage INPUT VOLTAGE (µA) 220 ICS (µA) 230 VDD (V) ICS (µA) IN 0.8 CS Pin Current Source vs V VSS (V) M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Functional Characteristics August 2009 8 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Functional Diagram August 2009 9 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Functional Description The MIC2150 is a dual channel, synchronous buck controller built with the latest BiCMOS process for optimum speed and efficiency. Both PWM channels operate 180o out of phase with each other to minimize input capacitor ripple current and input noise. The control loop has two stages of regulation. During steady state to medium output disturbances, the loop operates in fixed frequency, PWM mode while, during a large voltage disturbance (~±6.5% nominal), the loop becomes hysteretic; meaning that for a short period, the switching MOSFETs are switched on continuously until the output voltage returns to its nominal level. This maximizes transient response for large load steps, while operating nominally in fixed frequency PWM mode. Voltage mode control is used to allow for maximum flexibility and maintain good transient regulation. The operating voltage range is 4.5V to 14.5V and the output voltage can be set down to 0.7V. Start-up surges are prevented using built in soft-start circuitry as well as resistor-less current sensing for overload protection. August 2009 Other protection features include UVLO, dual level enable thresholds, over voltage latch off protection, power good signal and dual level over current protection. Theory of Operation The output voltage of the converter is sensed at the inverting input of the error amplifier. This is connected to VOUT via the two feedback resistors. The non-inverting input is connected to the internal 0.7V reference and the two are compared to produce an error voltage. This error voltage is then fed into the non-inverting input of the PWM comparator and compared to the 1.5V voltage ramp to create the PWM pulses. The PWM pulses propagate through to the MOSFET drivers which drive the external MOSFETs and create the power switching waveform at the set DC (duty cycle). This is then filtered by a power inductor and low ESR capacitor to produce the output voltage where VOUT ≈ DC×VIN. As an example, due to a load increase or an input voltage drop, the output voltage will instantaneously drop. This will cause 10 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 the error voltage to rise, resulting in wider pulses at the output of the PWM comparator. The higher Duty Cycle power switching waveform will cause an associated rise in output voltage and will continue to rise until the feedback voltage is equal to the reference and the loop is again in equilibrium. It is necessary to reduce the bandwidth of this feedback loop in order to keep the system stable. This can result in relatively poor transient regulation performance. However, the MIC2150 has a further hysteretic feedback loop which operates during large transients to reduce this effect. Hysteretic mode is invoked when output voltage is detected to be ±6.5% of its nominal level. If the input voltage step or output load step is large enough to cause a 6.5% deviation in VOUT, then the additional control loop functions to return the output voltage to its nominal set point in the fastest time possible. This is limited only by the time constant of the power inductor and output capacitor. This scheme is not used during normal operation because it creates a switching waveform whose frequency is dependant upon VIN, passive component values and the load current. Due to its large noise spectrum, it is only used during surges to keep switching noise at a known, fixed frequency. Soft-start Figure 3. Soft-Start At startup, the Soft-start MOSFET (SSFET) is released and CSS starts to charge at the rate dV SS dt = 2µA C SS . The PNP transistor’s emitter (COMP) starts to track VSS at that rate until it reaches the lower end of the PWM ramp waveform. This is around 950mV and is where switching pulses will begin to drive the power MOSFETs. This ramp continues on the COMP pin until the loop reaches it’s regulation point which is dependant upon the duty cycle required for regulation and can be anywhere from 1.4V to 2.9V. VSS will however, continue to rise as the PNP base-emitter junction becomes reverse biased. During large over current or short circuit conditions, i.e., where current limit is detected and VOUT is <75% of nominal, the SSFET is momentarily switched on. This discharges CSS to ~150mV at which point, it re-starts the soft-start cycle once again. During soft-start, hysteretic comparators are disabled until the −6.5% comparator has been set. Figure 1. Hysteretic Block Diagram Soft-start time = T1 + T2 Where T1 = 0.9×CSS/2µA And T2 = 1.5×VOUT×CSS/(VIN×2µA) If the value of CCOMP is in the same magnitude as CSS, then there may be an additional delay associated as the error amplifier charges the CCOMP capacitor. Current Limit The MIC2150 uses the RDSON of the low-side MOSFET to sense over current conditions. The lower MOSFET is used as it displays much lower parasitic oscillations during switching then the upper MOSFET. Using the MOSFET RDSON is not the most accurate method of current measurement, but is an adequate method for circuit protection without adding additional cost and board space that would be taken by discrete current sense resistors. Generally, the MIC2150 current limit Figure 2. Hysteretic Waveforms August 2009 11 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 circuit acts to provide a fixed maximum output current until the resistance of the load is so low that the voltage across it is no longer within regulation limits. At this point (75% of nominal output voltage), Hiccup current mode is initiated to protect down-stream loads from excessive current during hard short circuits and also reduces overall power dissipation in the PWM converter components during a fault. Before hiccup current mode occurs, ‘brick wall’ current limiting is provided to prevent system shutdown or disturbance if the overload is only marginal. pulse is missed and so on. Thus reducing the overall energy transferred to the output and VOUT starts to fall. As this successive missing of pulses results in an effectively lower switching frequency, power inductor ripple currents can get very high if left unlimited. The MIC2150 therefore limits Duty Cycle during current limit to prevent currents building up in the power inductor and output capacitors. Current-Limit Setting The current limit circuit responds to the peak inductor current flowing through the low-side FET. The value of RCS can be estimated with the “simple” method or can be more accurately calculated by taking the inductor ripple current into account. The Simple Method Current limit can be quickly estimated with the following equation: RCS = IOUT×RDSON(MAX)/200µA. Where: RDSON is the maximum on-resistance of the low side FET at the operating junction temperature Figure 4. Overcurrent Sensing During the normal operation of a synchronous Buck regulator, as the lower MOSFET is switched on, its drain voltage will become negative with respect to ground as the inductor current continues to flow from Source to Drain. This negative voltage is proportional to output load current, inductor ripple current and MOSFET RDSON. Accurate Method For designs where ripple current is significant when compared to IOUT or for low duty cycle operation, calculating the current setting resistor RCS should take into account that one is sensing the peak inductor current and that there is a blanking delay of approximately 100ns. Figure 5. Current Sensing Waveforms Figure 6. Overcurrent-Circuit Waveform The larger inductor current, the more negative VDS becomes. This is utilized for the detection of over current by passing a known fixed current source (200µA) through a resistor RCS which sets up an offset voltage (ICS×RCS). When ISD (Source to Drain current)×RDSON is equal to this voltage, the MIC2150’s over current trigger is set. This disables the next high-side gate drive pulse. After missing the high-side pulse, the over current (OC) trigger is reset. If, on the next low-side drive cycle, the current is still too high i.e., VCS is ≤ 0V, another high-side August 2009 Calculate peak switch current IPK = IOUT + IRIPPLE 2 Where: IRIPPLE = VOUT × (1 − D) FS × L Now calculate the actual set point to allow for the 100ns delay. 12 M9999-082809-A (408) 944-0800 Micrel, Inc. ISET = IPK − MIC2150 VOUT × TDLY L be low regardless of the state of CH1. If PG functionality is required for CH1 only, FB2 can be driven externally above 90% VREF to enable PG to operate on CH1 only. Rcs can now be calculated using: R CS = ISET × RDSON(MAX ) Enable Sometimes, at high currents, it is possible to see relatively large ground current peaks. These, in turn, can create voltage differentials between AGND points. In order to prevent these from affecting the converter operation, it is good practice to drive enable 0.5V higher than its maximum threshold i.e., >2.8V for both channels. ICS min Where: D = Duty Cycle FS = Switching Frequency L = Power inductor value TDLY = Current limit blanking time ~ 100ns ICS(min) = 180µA VDD Regulator The internal regulator provides a regulated 5V for supplying the analogue circuit power (AVDD) and the MOSFET driver power from the input supply (VIN). While this is designed to operate in dropout at input voltages down to 3V, driver current will be limited while the VDD regulator is in dropout. It is therefore recommended that for VIN ranges 5V to 7V, MOSFET gate current should be kept to less than 50mA. The AVDD supply should be connected to VDD through an RC filter to provide decoupling of the switching noise generated by the MOSFET drivers taking large current steps from the VDD regulator. Example Consider a 12V to 3.3V @ 5A converter with 0.5µH power inductor and 90% efficiency at full load. D≈ VOUT 3 .3 V = = 31% VIN × Efficiency 12V × 0.9 3.3 V × (1 − 0.31) = 9.11A 500kHz × 0.5µH 9.11 IPK = 5 + = 9.55 A 2 3.3v × 100ns ISET = 9.55 A − = 8.89 A 0.5µH 8.89 × 10mΩ = 494Ω R CS = 180µA IRIPPLE = Gate Drivers The MIC2150 is designed to drive both high-side and low-side N-Channel MOSFETs to enable high switching speeds and the lowest possible losses. The high-side MOSFET driver is supplied by bootstrapping the switching voltage at the Drain of the lower MOSFET to VDD. This provides the high-side MOSFET with a constant VGS drive voltage equal to VDD. Using the simple method here would result in a current limit point much lower than expected. This equation sets the minimum current limit point of the converter, but maximum will depend on the actual inductor value and RDSON of the MOSFET under current limit conditions. This could be in the region of 50% higher and should be considered to ensure that all the power components are within their thermal limits unless thermal protection is implemented separately. It is recommended to connect a 22pF capacitor from CS to AGND close to the pins of the IC to prevent adjacent channel switching noise from affecting the current limit behavior. Over Voltage Protection If the voltage at the FB pin is detected to be 15% higher than nominal for >2µs, the channel is stopped from switching immediately and latched off. Switching can be re-started by taking EN below the channel’s enable threshold and re-enabling or re-cycling power to the IC. Figure 7. High-Side Gate Drive Circuit and Waveform When HSD goes high, this turns on the high-side MOSFET and the SW node rises sharply. This is coupled through the bootstrap capacitor CBST and Diode DBST becomes reverse biased. The MOSFET Gate is held at VDD - 0.5V above the Source for as long as CBST remains charged. The bias current of the high-side driver is <10mA so 100nF is sufficient to hold the gate voltage with minimal droop for the power stroke (High-side Power Good Output The power good output (PG) will go high only when both Channel outputs are above 90% of their nominal set output voltage. If CH2 is disabled (EN<2V), then PG will August 2009 13 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 switching) cycle. There is a period when both driver outputs are held off (‘dead time’) to prevent shoot-through current flowing. Shoot-through current flows if both MOSFETS are on momentarily as the cycle’s crossover. This dead time must be kept to a minimum to reduce losses in the catch diode which could either be an external Schottky diode placed across the lower MOSFET or the internal Schottky diode implemented in some MOSFETs. It is not recommended for high current designs, to rely on the intrinsic body diode of the power MOSFET; these typically have large VF values and a slow reverse recovery characteristic which will add significant losses to the regulator. Dependent on the MOSFETs used, the dead time could be required to be 150ns or 20ns. The MIC2150 solves this variability issue by using an adaptive gate-drive scheme: When the high-side driver is turned off, naturally the inductor forces the voltage at the switching node (lowside MOSFET drain) towards ground to keep current flowing. When the SW pin is detected to have reached 1.5V, the top MOSFET can be assumed to be off and the low-side driver output is immediately turned on. There is also a short delay between the low-side drive turning off and the high-side driver turning on. This is fixed at ~60ns to 100ns to allow for large gate charge MOSFETs to be used. i.e., ΔBST = 10mA×1.6µs / 100nF = 160mV. For most applications, 220nF should be used to achieve an improved, lower droop. When the low-side driver turns on every switching cycle, any lost charge from CBST is replaced via DBST as it becomes forward biased. Therefore minimum BST voltage is VDD – 0.5V. The Low-side driver is supplied directly from VDD at nominal 5V. Adaptive Gate Drive Figure 8. Adaptive Gate Drive Diagram August 2009 14 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 IRIPPLE × t ON 2 × COUT Application Information VOUTPK −PK ≈ IRIPPLE × ESR + Passive Component Selection Guide If therefore, the need is for low output voltage noise (e.g., in low output voltage converters), VOUT ripple can be directly reduced by increasing inductor value, output capacitor value or reducing ESR. Inductor Selection The inductor value is responsible for the ripple current which causes some proportion of the resistive losses in the power components. These losses are proportional to IRIPPLE2. Minimizing inductor ripple current can therefore reduce the RMS current flowing in the power components and generally improve efficiency; this is achieved by choosing a larger value inductor. Having said this, the actual value of inductance is realistically defined by space limitations, RMS rating (IRMS) and saturation current (ISAT) of available inductors. If one looks at the newer flat wire inductors for example, these typically have higher ISAT ratings than the IRMS for lower values. Also, as inductance value increases, these figures tend to get closer in value. This mirrors what happens in the converter with ISAT analogous to the maximum peak switch current and IRMS analogous to output current. As inductance increases, so ISWITCH(PK) tends towards IOUT. This is a characteristic that makes these types of inductor optimal for use with high power buck converters such as MIC2150. To determine the ISAT and IRMS rating of the inductor, we should start with a nominal value of ripple current. This should typically be no more than IOUT(MAX)/2 to minimize MOSFET losses due to ripple current mentioned earlier. Therefore: LMIN ~ 2 × For tantalum capacitors, ESR is typically >40mΩ which usually makes loop stabilization easier by utilizing a pole-zero (type II) compensator. Due to many advantages of multi-layer ceramic capacitors, among them, cost, size, ripple rating and ESR, it can be useful to choose these in many cases. However, one disadvantage is the CV product. This is lower than tantalum. A mixture of one tantalum and one ceramic can be a good compromise which can still utilize the simple type II compensator. With ceramic output capacitors only, a double-pole, double-zero (type III) compensator is required to ensure system stability. Loop compensation is described in more detail later in the data sheet. Ensure the RMS ripple current rating of the capacitor is above IRIPPLE×0.6 to improve reliability. Input Capacitor Selection CIN ripple rating for a single phase converter is typically IOUT/2 under worst case duty cycle conditions of 50%. This increases ~10% for a ripple current of IOUT/2. When both cycles are switching 180° out of phase, the ripple can reduce at DC <50% to: VOUT VOUT ) × (1 − IOUT × FS VIN × Efficiency IRMSCIN = I12 × D1 × (1 − D1) + I22 × D2 × (1 − D2 ) − 2 × I1 × I2 × D1 × D2 ILRMS > 1.04×IOUT(MAX) ILSAT > 1.25×IOUT(MAX) Any value chosen above LMIN will ensure these ratings are not exceeded. In considering the actual value to choose, one needs to look at the effect of ripple on the other components in the circuit. The chosen inductor value will have a ripple current of: IRIPPLE ~ It is however, also advisable to closely decouple the Power MOSFETs with 2×10µF ceramic capacitors to reduce ringing and prevent noise related issues from causing problems in the layout of the regulator. The ripple rating of CIN may therefore, be satisfied by these decoupling capacitors; allowing the use of perhaps one more ceramic or tantalum input capacitor at the input voltage node to decouple input noise and localize high di/dt signals to the regulator input. (1 − D) VOUT × FS L Power MOSFET Selection The MIC2150 drives N-Channel MOSFETs in both the upper and lower positions. This is because the switching speed for a given RDSON in the N-Channel device is superior to the P-Channel device. There are different criteria for choosing the upper and lower MOSFETs and these criteria are more marked at lower duty cycles such as 12V to 1.8V conversion. In such an application, the upper MOSFET is required to switch as quickly as possible to minimize transition This value should ideally be kept to a minimum, within the cost and size constraints of the design, to reduce unnecessary heat dissipation. Output Capacitor Selection The output capacitor (COUT) will have the full inductor ripple current IRIPPLERMS flowing through it. This creates the output switching noise which consists of two main components: August 2009 15 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 losses (power dissipated during rise and fall times). Conversely, the lower MOSFET can switch slower, but must handle larger RMS currents. When duty cycle approaches 50%, then the current carrying capability of the upper MOSFET starts to become critical also and can sometimes benefit from external high current drivers to achieve the necessary switching speeds. MOSFET loss = Static loss + Transition loss Static loss (PS) = IFETRMS2×RDSON Transition loss (PT) = IOUT×(tr + tf)×VDSOFF×FS/2 Where: There are many MOSFET packages available which have various values of thermal resistance and therefore, can dissipate more power if there is sufficient airflow or heat sink externally to remove the heat. However, for this exercise, one can assume a maximum dissipation of 1.2W per MOSFET package. This can be altered if the final design has higher allowable package dissipation. Look at lower MOSFET first: 1.2W = PS + PT For the low-side FET, PT is small because VDSOFF is clamped to the forward voltage drop of the Schottky diode. Therefore: tr + tf = Rise time + Fall time Due to the worst case driver currents of the MIC2150, the value of tr + tf simplifies to: RDSON(MAX) ~1.2 / IFETRMS2 E.g. For 12V to 1.8V @ 10A RDSON(MAX) <14mΩ It is important to remember to use the RDSON(MAX) figure for the MOSFET at the maximum temperature to help prevent thermal runaway (as the temperature increases, the RDSON increases). tr + tf (ns) = ΔQg (nC) ΔQg can be found in the MOSFET characteristic curves ΔQgmax should be limited so that the low-side MOSFET is off within the fixed 80ns delay before the high-side driver turns on. High-side MOSFET: For the high-side FET, the losses should ideally be evenly spread between transition and static losses. Use the center of the VIN range to balance the losses. PT = 0.6 = IOUT×ΔQg×VINMID×FS/2 Therefore: ΔQgmax <0.6×2 / (IOUT x VINMID×FS) RDSON is calculated similarly for the high-side MOSFET: RDSON(MAX) ~0.6 / IFETRMS2 Using previous example: Figure 9. MOSFET Gate Charge Characteristic VDSOFF = Voltage across MOSFET when it is off IFETRMS = D× (lx 2 + lx + ly + ly 3 2 ΔQgmax < 20nC ) RDSON(MAX) < 35mΩ Note that these are maximum figures based upon thermal limits and are not targeted at the highest efficiency. Selection of lower values is recommended to achieve higher efficiency designs. Limits to watch out for: <1500 nC/VIN QgTOTAL (<2500nC/VIN for MIC2151) Ix = IOUT – IRIPPLE/2 Iy = IOUT + IRIPPLE/2 D = TON×FS D is not duty cycle (DC ~1.1×VOUT/VIN) since it changes depending upon which MOSFET one is calculating losses for. • Total of both high-side and low-side MOSFET Qg values at VGS = 5V for both channels. • E.g. @ VIN(MAX) = 13.2V: QgTOTAL < 1500 / 13.2 = 114nC ΔQgLOW <120nC (Per LSD output) Upper FET TON = DC/FS The lower MOSFET is not on for the whole time that the upper MOSFET is off due to the fixed 80ns high-side driver delay. Therefore, there is an 80ns term subtracted from the lower FET on time equation. Lower FET TON = (1 – DC)/FS – 80ns August 2009 16 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 • Maximum turn on gate charge for each separate lowside MOSFET to ensure proper turn off before highside MOSFET is switched on. Modulator This section turns the error signal from the error amplifier into a low impedance square wave with a pulse width proportional to the input. This section therefore includes the ramp, PWM comparator, drivers and MOSFETs. Usually, at the moderate frequencies of the control loop, the delays which appear as a phase lag between the error amplifier output and the power stage are small, but significant in allowing a loop to become unstable. The average gain of this stage can therefore be assumed to be linear with a gain of VIN/Ramp and a phase shift less than 10 degrees. Output Voltage Setting The internal reference of the MIC2150 is 0.7V nominal. Therefore: VOUT = 0.7×(R1 + R2)/R2 By setting R2 at <10k R1 = R2×(VOUT – 0.7)/0.7 The FB pin input offset current can be up to 500nA. It is therefore recommended to use resistor values of less than 10k to improve output accuracy Power Stage This section is essentially the inductor, output capacitors and load resistance. Unlike the Modulator, in the frequency range of the loop, this is a complex system and contains two poles (i.e., a –40dB/decade gain fall at 1/2.π√LC and a total 180° phase lag) and a zero ( i.e., a +20dB/Decade gain rise at 1/2πC.ESR and a total 90 degree phase lead). If the zero created by the output capacitor’s ESR is too high to affect the two poles of the LC, then it is possible to have the conditions for an unstable loop without compensation. In general, there are two types of compensators that give a good transient response (the measure of how fast the regulation loop responds to a load step and brings the output voltage back to its steady state voltage): Schottky Diode and Snubbing Components When the high-side switch turns on, there is usually an overshoot and ringing associated with this fast edge. This is induced by perturbation of the tank circuit made up of a combination of trace and lead inductances and MOSFET Drain and other parasitic capacitances. This can cause unwanted EMI and stress the driver circuitry if left un-damped. Snubbing is recommended to reduce this ringing and acts to critically damp the natural ringing frequency of the tank circuit. Technically, this can be achieved using a single resistance to dissipate the ringing energy. However, in practical terms, this would cause a DC power loss. Therefore a series RC is used to act only on the edges of the waveform. There are several methods of calculating the ideal values for the RC. The approach presented here is to estimate a value of C then calculate the R. This is best left until the final layout and components are available as it then accounts for all the parasitic contributors that cause the rising edge ringing. Estimating C: With no snubbing, measure the frequency of ringing. This is Fo. Now add a capacitor that results in a ring frequency of Fo/2. This is CSNUB. Calculating R: If 1/2π × COUT×ESR > ½ FS Use a Double pole-Double Zero, PID or Type III compensator. This is typically used for low ESR ceramic output capacitor designs. 2. If 1/2π × COUT×ESR < Fco < ½ FS. Use a Pole Zero pair, PI or Type II compensator. This is typically used for Tantalum or electrolytic output capacitor designs. Compensator This section consists of the feedback resistors, error amplifier, compensation network and reference. It acts to sample the output voltage and create a frequency compensated error signal proportional to the difference between the output voltage and the reference. As this is a negative feedback system, this stage introduces a DC phase shift of 180 degrees. The output of the compensator is then fed into the modulator. What is meant by frequency compensated is that it adds phase and gain where it is lost in the power stage and also acts to ensure gain is low at high frequencies to reduce susceptibility to switching noise. The goal of the compensation network is to achieve a closed loop system that has sufficient phase margin and/or gain margin to ensure system stability across all RSNUB = 1/π×CSNUB×Fo Loop compensation The loop of a voltage mode, PWM buck converter contains 3 main blocks to be considered; the modulator, the power stage and the compensator. Figure 10. Loop Compensation Block Diagram August 2009 1. 17 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 operating conditions. The detailed analysis for achieving this is covered in other texts and will not be covered here. The following is a method for calculating the correct values for stability. margin (typically 50 degrees will ensure system stability over all conditions). Fco < Fs/5 PM = 50 degrees Place the two phase boost break frequencies such that our maximum phase boost occurs at the desired crossover frequency Fco. Ceramic Output Capacitor Designs The closed loop Bode plot response for a correctly compensated ceramic output capacitor design is shown below. FZ2 = Fco × 1 − Sin(PM) 1 + Sin(PM) FP1 = Fco × 1 + Sin(PM) 1 − Sin(PM) FZ1 must be somewhere below or equal to FZ2. Placing it at one half FZ2 helps to spread the frequency range of the phase boost. FZ1 = FZ2 / 2 Finally, place the noise suppression pole at one half the switching frequency. FP2 = FS 2 The calculation of the required components to achieve FP1, FP2, FZ1 and FZ2 for this circuit is ideal for a spreadsheet which is available on the Micrel website. However, they can also be calculated using the following method: Figure 11. Ceramic Output Capacitor Bode Plot The power inductor and output capacitor create the resonant frequency at Fo. It is preferred to make the desired crossover frequency (loop bandwidth) greater than this at Fco with a phase margin (PM) of typically 50 degrees. The maximum phase boost, on a log scale, occurs approximately half way between the highest zero (FZ2) and the lowest pole (FP1). To be precise, it is Collect All Known Circuit Parameters L: Inductor value Output capacitor value COUT: ESR: Output capacitor ESR. Fco: Desired crossover frequency VRAMP: Internal ramp voltage = 1.5V Internal reference voltage = 0.7V VREF: Maximum input voltage of the converter VIN: at FZ2 × FP1 . The required compensation network for this is a double pole, double zero or type III network shown in Figure 12. Calculating Network Values Fo = 1 2 × π × L × COUT Choose RC1 value: This can be any reasonable value up to 10kΩ, but in order to keep the values of R1 and C2 within practical limits, this ‘factor’ can be useful. Rc1 = 25k/Fo Figure 12. Type III Compensation Network C1 = 1 2 × π × RC1× FZ1 Placement of the 2 Poles and 2 Zeros Choose a loop bandwidth/crossover frequency (Fco) at less than one fifth switching frequency and a phase C2 = 1 2 × π × RC1× FP2 August 2009 18 M9999-082809-A (408) 944-0800 Micrel, Inc. C3 = 2 × π × Fco × L × COUT VIN × RC1 VRAMP R3 = 1 2 × π × C3 × FP1 R2 = R1× VREF VOUT − VREF R1 = 1 − R3 2 × π × C3 × FZ2 MIC2150 Tantalum/Electrolytic Output Capacitor Designs The closed loop bode plot response of the higher ESR capacitor design looks something like the figure below. Figure 14. Type II Compensation Network Pole and Zero Positioning Fo = 1 2 × π × L × COUT To introduce a boost in phase at and beyond the resonance of the output LC filter (Fo), FZ can be placed at Fo. FZ = Fo Together with phase boost associated with the output capacitor ESR zero, this will achieve up to 45 degrees Phase margin. The noise suppression pole can be set to one half switching frequency. F FP = S 2 Calculating Network Values Choose R1 <10k to reduce susceptibility to noise and inaccuracies induced by the error amplifier bias current. Figure 13. Tantalum Output Capacitor Bode Plot Due to the output capacitor ESR creating a zero within the range of the desired crossover frequency (Fco), this design only requires that one adds one zero and one associated pole. The phase boost in this case occurs between the zero (FZ) and the pole (FP) of the compensator. Therefore, the zero gain crossover frequency (Fco) will be between these two points. The zero is created by RC1 and C1. The pole should be set at ≤one half switching frequency to reduce noise sensitivity. The plateau gain (gain between FZ and FP) is set by RC1 and R1, AvPLATEAU = RC1/R1, this should be set to a modest gain of five-to-ten to improve transient response. This compensation network is shown in Figure 14. August 2009 R1 = 1k To set output voltage, set R2: R1× VREF VOUT − VREF R2 = For a plateau gain of 5 RC1 = R1× 5 C1 = 1 2 × π × RC1× FZ Assuming FZ<<FP, C2 can be approximated to: C2 ≈ 19 1 2 × π × RC1× FP M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 bypass capacitor must be used to limit the overvoltage spike seen on the input supply with power is suddenly applied. Design and PCB Layout Guideline Warning!!! To minimize EMI and output noise, follow these layout recommendations. • PCB Layout is critical to achieve reliable, stable and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal and return paths. The following guidelines should be followed to insure proper operation of the MIC2150 and MIC2151 converters. Inductor IC (Integrated Circuit) • Place the IC and point-of-load (POL). • Use fat traces to route the input and output power lines. • Signal and power grounds should be kept separate and connected at only one location. • The exposed pad (EP) on the bottom of the IC must be connected to the PGND and AGND pins of the IC. MOSFETs close to the • Place the feedback network close to the IC and keep the high impedance feedback trace short. Then route the VOUT trace to the output. • The VDD capacitor must be placed close to the VDD pin and preferably connected directly to the pin and not through a via. The capacitor must be located right at the IC. The VDD terminal is very noise sensitive and placement of the capacitor is very critical. Connections must be made with wide trace. • Keep the inductor connection to the switch node (SW) short. • Do not route any digital lines underneath or close to the inductor. • Keep the switch node (SW) away from the feedback (FB) pin. • To minimize noise, place a ground plane underneath the inductor. Output Capacitor • Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. • Phase margin will change as the output capacitor value and ESR changes. Make sure stability calculations and done at the minimum and maximum tolerance values of ESR for the capacitor. • The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high current load trace can degrade the DC load regulation. MOSFETs • Input Capacitor • Place the VIN input capacitors on the same side of the board and as close to the MOSFETs as possible. • Keep both the VIN and power GND connections short. • Place several vias to the ground plane close to the VIN input capacitor ground terminal. An additional Tantalum or Electrolytic bypass input capacitor of 22µF or higher is required at the input power connection. Low gate charge MOSFETs should be used to maximize efficiency, especially at when operating at lower output current. RC Snubber • An RC snubber from each switch node-to-ground is recommended to reduce ringing and noise on the output and minimize component stress. Schottky Diode (Optional) • Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors. • Place the Schottky diode on the same side of the board as the MOSFETs and VIN input capacitor. • Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor. • The connection from the Schottky diode’s Anode to the input capacitors ground terminal must be as short as possible. • If a Tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%. • The diode’s Cathode connection to the switch node (SW) must be keep as short as possible. • Others • In “Hot-Plug” applications, a Tantalum or Electrolytic August 2009 20 Connect the current limiting resistor directly to the drain of low-side MOSFET. M9999-082809-A (408) 944-0800 Micrel, Inc. • The output voltage feedback resistors should be placed close to the FB pin. The top side of the upper resistor should connect directly to the output node. Run this trace away from the switch node traces and inductor. The bottom side of the lower voltage divider resistor should connect to the GND pin of the control IC. • The compensation resistor and capacitors should be placed right next to the COMP pin and the other side should connect directly to the GND pin on the control IC rather than going to the ground plane. • Add placeholders for gate resistors on the top-side MOSFET gate drives. If necessary, gate resistors of 10Ω or less should be used. August 2009 MIC2150 21 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 MIC2150 Evaluation Board Schematic August 2009 22 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Bill of Materials Item Part Number Manufacturer C1,C3 TR3D107K016C0100 Vishay C8,C10,C11, C12,C20 GRM21BR61C106KE15L Murata(2) or VJ0805Y106KXXAT Vishay(1) or 0805YD106K C13,C14 VJ0805Y104KXXAT VJ0603Y104KXXAT C7,C28,C29 C6,C9 VJ0603Y105KXXAT Description (1) Qty. 100µF/16V, D case 2 10µF/16V, 1210, X5R 5 Vishay(1) 100nF/16V, 0805 2 (1) 100nF/16V, 0603 3 (1) 1µF/16V, 0603 2 (1) 1µF/16V, 0805 2 100µF/6.3V, 1210 1 OPEN, NF 1 330µF/6.3V, D case 1 AVX(3) Vishay Vishay C4,C5 VJ0805Y105KXXAT C18 C3225X5R0J107M Vishay TDK(4) or 12106D107KAT2A AVX(3) C15 OPEN C19 TR3D337K6R3C0100 Vishay(1) or TPSD337K006R0045 AVX(3) C21,C22 VJ0805Y102KXXAT Vishay(1) 1nF/16V, 0805 2 C26 VJ0603A181KXXAT (1) Vishay 180pF/16V, 0603 1 C25 VJ0603A121KXXAT Vishay(1) 120pF/16V, 0603 1 VJ0603Y472KXXAT (1) 4.7nF/16V, 0603 2 (1) C23,C24 Vishay C16,C17 VJ0603A220KXXAT Vishay 22pF/16V, 0603 2 C27 VJ0603Y222KXXAT Vishay(1) 2.2nF/16V, 0603 1 C30 OPEN OPEN, NF 1 SD103BWS 2 DFLS220L-7 2 D1,D2 SD103BWS-V-GS08 (1) Vishay Diodes Inc. (5) D3,D4 DFLS220L-7(Not Fitted) L2 HC5-1R5 Cooper(6) 1.5µH,17A 1 L3 HC5-2R2 (6) Cooper 2.2µH,14A 1 Q1,Q4 FDMS8680 Fairchild(7) or SiR462DP Vishay(1) 20A HS FET 2 Q5,Q8 FDMS8660AS or Si7636DP 20A LS FET 2 Q3, Q2 Not Fitted 20A HS FET 0 Q7, Q6 Not Fitted 20A LS FET 0 Fairchild(7) Vishay(1) (1) R2,R3,R4 CRCW06031002FKEA Vishay 10K , 0603 3 R18 CRCW06034751FKEA Vishay(1) 4.75k, 0603 1 CRCW06031001FKEA (1) 1k, 0603 1 (1) 221 ohm, 0603 2 (1) R17 R10,R11 CRCW06032210FKEA Vishay Vishay R9,R12 CRCW12062R00FKEA Vishay 2 ohms, 1206 2 R20 CRCW06033011FKEA Vishay(1) 3.01k, 0603 1 CRCW06033920FKEA (1) 392 ohms, 0603 1 (1) 3.65k, 0603 1 R19 R15 August 2009 CRCW06033651FKEA Vishay Vishay 23 M9999-082809-A (408) 944-0800 Micrel, Inc. Item MIC2150 Part Number R16 R1 Manufacturer Description Qty. 4.99k, 0603 1 (1) 10 ohms, 0603 1 (1) 365 ohms , 0603 1 OPEN, NF 1 MIC2150 2-Phase Dual Output PWM Synchronous Buck Control IC 1 CRCW06034991FKEA Vishay(1) CRCW060310R0FKEA R21 CRCW06033650FKEA R22 OPEN U1 MIC2150YML Vishay Vishay Micrel Semiconductor (8) Notes: 1. Vishay.: www.vishay.com 2. Murata: www.murata.com 3. AVX: www.avx.com 4. TDK: www.tdk.com 5. Diodes Inc.: www.diodes.com 6. Cooper Electronics: www.cooperet.com 7. Fairchild Semiconductor: www.fairchildsemi.com 8. Micrel, Inc.: www.micrel.com August 2009 24 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Recommended Layout Top Copper Bottom Copper August 2009 25 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Mid Layer 1 Mid Layer 2 August 2009 26 M9999-082809-A (408) 944-0800 Micrel, Inc. MIC2150 Package Information 24-Lead MLF (ML) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2009 Micrel, Incorporated. August 2009 27 M9999-082809-A (408) 944-0800