MM54HCT109/MM74HCT109 Dual J-K Flip-Flops with Preset and Clear General Description These high speed J-K FLIP-FLOPS utilize advanced silicongate CMOS technology. They possess the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Each flip flop has independent J, K, PRESET, CLEAR, and CLOCK inputs and Q and Q outputs. These devices are edge sensitive to the clock input and change state on the positive going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input. MM54HCT/MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LSTTL devices and can be used to reduce power consumption in existing designs. Features Y Y Y Y Typical propagation delay: 20 ns Low input current: 1 mA maximum Low quiescent current: 40 mA maximum (74HCT Series) Output drive capability: 10 LS-TTL loads The 54HCT/74HCT logic family is functionally as well as pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Connection and Logic Diagrams Function Table Dual-In-Line Package Inputs Outputs PR CLR CLK J K Q L H L H H H H H H L L H H H H H X X X X X X L H L H X X X X L L H H X H L L H H* H* L H TOGGLE Q0 Q0 H L Q0 Q0 u u u u L Q Order Number MM54HCT109 or MM74HCT109 TL/F/5361 – 1 TL/F/5361 – 2 C1995 National Semiconductor Corporation TL/F/5361 RRD-B30M105/Printed in U. S. A. MM54HCT109/MM74HCT109 Dual J-K Flip-Flops with Preset and Clear January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HCT MM54HCT b 0.5 to VCC a 0.5V g 20 mA Min 4.5 Max 5.5 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 500 ns Input Rise or Fall Times (tr, tf) g 25 mA g 50 mA b 65§ C to a 150§ C 600 mW 500 mW 260§ C DC Electrical Characteristics VCC e 5V g 10% (unless otherwise specified) Symbol Parameter TA e 25§ C Conditions 74HCT TA eb40 to 85§ C Typ 54HCT TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0 2.0 2.0 V VIL Maximum Low Level Input Voltage 0.8 0.8 0.8 V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 4.0 mA, VCC e 4.5V lIOUTl e 4.8 mA, VCC e 5.5V VCC 4.2 5.2 VCCb0.1 3.98 4.98 VCCb0.1 3.84 4.84 VCCb0.1 3.7 4.7 V V V Maximum Low Level Voltage VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 4.0 mA, VCC e 4.5V lIOUTl e 4.8 mA, VCC e 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V V V IIN Maximum Input Current VIN e VCC or GND, VIH or VIL g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 4.0 40 80 mA VIN e 2.4V or 0.5V (Note 4) 0.3 0.4 0.5 mA VOL Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: Measured per pin, all other inputs held at VCC or GND. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol fMAX Parameter Conditions Typ Maximum Operating Frequency Guaranteed Units Limit 50 30 MHz tPHL, tPLH Maximum Propagation Delay from Clock to Q or Q 18 30 ns tPHL, tPLH Maximum Propagation Delay from Preset or Clear to Q or Q 18 30 ns 20 ns tREM Minimum Removal Time, Preset or Clear to Clock tS Minimum Setup Time J or K Clock 10 20 ns tH Minimum Hold Time Clock to J or K b3 0 ns tW Minimum Pulse Width Clock, Preset or Clear 8 16 ns AC Electrical Characteristics VCC e 5.0V g 10%, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C Typ fMAX Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay from Clock to Q or Q tPHL, tPLH Maximum Propagation Delay from Preset or Clear to Q or Q tREM Minimum Removal Time Preset or Clear to Clock tS Minimum Setup Time J or K to Clock tH Minimum Hold Time Clock to J or K tW 74HCT TA eb40§ to 85§ C 54HCT TA eb55§ to 125§ C Units Guaranteed Limits 27 22 18 MHz 22 35 44 52 ns 22 35 44 52 ns 20 25 30 ns 10 20 25 30 ns b3 0 0 0 ns Minimum Pulse Width Clock, Preset or Clear 16 20 24 ns tr, tf Maximum Input Rise and Fall Time 500 500 500 ns tTHL, tTLH Maximum Output Rise and Fall Time 15 19 22 ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per flip-flop) 35 pF 5 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 MM54HCT109/MM74HCT109 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions inches (millimeters) Order Number MM54HCT109J or MM74HCT109J NS Package J16A Order Number MM74HCT109N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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