For Information Equipment MN89302 SVGA Display Controller Overview The MN89302 is an LCD/CRT display controller with IBM™ VGA-compatible registers. It features all the necessary interfaces for a compact display system: ISA bus interface, local bus interface, DRAM interface, and LCD panel interface. The built-in graphics acceleration functions include support for bit-block transfers (BITBLT) and hardware cursor. Note: IBM™ and VGA are registered trademarks of International Business Machines Corporation. Features Monochrome STN LCD panel support Maximum display size: 800 × 600 Built-in graphics acceleration functions Support for single and dual panels • Bit-block transfers (BITBLT) to and from host video memory and within video memory 32-monochrome gradation • Hardware cursor (16 × 16 or 32 × 32) Color STN LCD panel support Maximum display size: 800 × 600 Support for single and dual panels 32-gradation for each color (RGB) Color TFT LCD panel support Maximum display size: 800 × 600 5-bit output for red and blue; 6-bit output for green Maximum number of colors in concurrent display 320 × 240: 64k (TFT, STN) 640 × 480: 256/260K palette (TFT, STN) 800 × 600: 256/260K palette (TFT, STN) Applications Point-of-sale terminals, Factory automation terminals, word processors, and other terminals Built-in automatic display centering Built-in gradation control table (rewritable) for optimizing gradation to match panel DRAM interface with 16-bit bus • Support for 2CAS/2WE mode • Refresh control Host interfaces • ISA bus (16-bit) • i386/i486 local bus (16-bit) Note: i386 and i486 are trademarks of Intel Corporation. MN89302 For Information Equipment Pin Assignment 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDD GND LCAS UCAS WE RAS GND MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 VDD GND UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 VDD GND LD7 LD6 LD5 ISA bus mode 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SA16 SA17 SA18 SA19 A20 A21 GND XIN XOUT GND SCANTEST TEST RESET MINTEST REFRESH MEMR GND IOCS16 MEMCS16 VDD SA1 MEMW IOCHRDY IOWR IORD BIOSEN AEN SBHE GND SD15 SD14 SD13 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 GND VDD SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 (TOP VIEW) QFP128-P-1818 LD4 LD3 LD2 LD1 LD0 VDD GND DCLK LP FP DISP VDD GND LOGICON LCDON BACKON SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 VDD SA0 GND SD8 SD9 SD10 SD11 SD12 For Information Equipment MN89302 Block Diagram Gray scale engine UD[7:0] LD[7:0] BACKON LCDON LOGICON LP FP DISP DCLK RAM table Hardware cursor 49 50 51 56 55 54 57 LCD panel controller Attribute control 8 XIN 13 RESET 12/14 TEST/MINTEST Address[21:0] SD[15:0] AEN SBHE IOWR IORD SMEMW SMEMR IOCHRDY REFRESH MEMCS 16 IOCS 16 LCD/CRT controller Memory interface 27 28 BITBLT 24 25 22 16 23 15 19 18 Video FIFO Host interface Memory write buffer 91 Access attributer 93 94 92 Graphics controller 26 MA[9:0] MD[15:0] RAS UCAS LCAS WE BIOSEN MN89302 For Information Equipment Pin Descriptions Pin No. Symbol I/O Level 27 AEN I TTL Function Description Address Enable "H" level input from this pin indicates that a DMA transfer is in progress, so the chip does not respond to I/O access. 28 SBHE I TTL Byte High Enable This input indicates the state of the 16-bit bus. 24 IOWR I TTL I/O Write This input indicates an I/O write request. 25 IORD I TTL I/O Read This input indicates an I/O read request. 22 SMEMW I TTL Memory Write This input indicates a memory write request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 16 SMEMR I TTL Memory Read This input indicates a memory read request dedicated for an address space in the first megabyte (000000 to 0FFFFFH). 6 to 5 A[21:20] I TTL Address[21:20] These inputs give the address 21:20. 4 to 1, SA[19:0] I TTL 128 to 115, Address[19:0] These inputs give the address 19:0. 21 ,39 30 to 48 SD[15:0] I/O TTL 23 IOCHRDY I/O TTL Data[15:0] These pins represent the host data bus. I/O Channel Ready This pin is "L" level when I/O or memory access is given wait states. 19 MEMCS16 O TTL Memory Chip Select 16 This output indicates to the system that 16-bit memory access is available. 18 IOCS16 O TTL I/O Chip Select 16 This output indicates to the system that 16-bit I/O access is available. 15 REFRESH I TTL Refresh "L" level input indicates that the system is refreshing its DRAM. 89 to 80 MA[9:0] I/O CMOS Memory Address These outputs give the address of the display memory . 91 RAS O CMOS Row Address Strobe (RAS). This output is the strobe signal for the row address latch. 93 UCAS O CMOS Upper Column Address Strobe (UCAS) This output is the strobe signal for the upper column address latch. In the 2WE mode, however, it functions as the CAS signal. For Information Equipment MN89302 Pin Descriptions (continued) Pin No. Symbol I/O Level 94 LCAS O CMOS Function Description Lower Column Address Strobe (LCAS) This output is the strobe signal for the lower column address latch. In the 2WE mode, however, it functions as the LWE signal. 92 WE O CMOS Write Enable This output is the data write signal. In the 2WE mode, however, it functions as the UWE signal. 112 to 97 MD[15:0] I/O TTL Memory Data These pins represent the data bus to the DRAM. 26 BIOSEN O CMOS BIOS Enable This output enables ROM BIOS output. 49 BACKON O CMOS Backlight ON This output requests backlighting. "L" level: OFF; "H" level: ON 50 LCDON O CMOS LCD Drive ON This output requests power-ON for the LCD panel. "L" level: OFF; "H" level: ON 51 LOGICON O CMOS LCD Logic ON This output requests power-ON for LCD panel logic circuits. "L" level: OFF; "H" level: ON 56 LP O CMOS Line Pulse This output provides pulses indicating the end of a line of the LCD panel. 55 FP O CMOS Frame Pulse This output provides pulses indicating the start of a frame of the LCD panel. 54 DISP O CMOS Display Enable This output enables the LCD display. An external RAMDAC uses this signal as a blanking signal. A TFT LCD uses it as an enable signal. 57 DCLK O CMOS Data Shift Clock This pin provides a data shift clock signal for an STN LCD panel or a dot clock signal for a TFT LCD panel or external RAMDAC. 77 to 70 UD[7:0] O CMOS Upper Data[7:0] 67 to 60 LD[7:0] O CMOS Lower Data[7:0] This pins provide display data. Usage varies with the LCD panel type. MN89302 For Information Equipment Pin Descriptions (continued) Pin No. Symbol I/O Level 13 RESET I CMOS Function Description Reset "H" level input from this pin reset and initializes the chip. If the host is in a i386 mode, the chip aligns the clock phase with this signal. 81 to 80 MA[1:0] I CMOS Host Type During a reset, these pins select the host type. MA[1:0] 12/14 TEST/ CMOS Host Type 0 0 ISA 0 1 i386SX 1 0 i386DX 1 1 i486 Chip Test Condition MINTEST 11 SCANTEST 8/9 XIN/XOUT This pin selects the chip test mode. I/O Clock IN/OUT These pins are the clock I/O pins. Connect them to a crystal oscillator. Absolute Maximum Ratings Parameter Symbol Power supply voltage Ratings Unit VDD – 0.3 to +7.0 V Input pin voltage VI – 0.3 to VDD +0.3 V Output pin voltage VO – 0.3 to VDD +0.3 V Power dissipation PD 1000 mW Operating ambient temperature Topr 0 to 70 ˚C Storage temperature Tstg –55 to +150 ˚C Recommended Operating Conditions Parameter Symbol Conditions min typ max Unit 4.75 5.00 5.25 V 0 70 ˚C 0 150 ns Power supply voltage VDD Ambient temperature Ta Rise time for input tr 0 Fall time for input 150 ns Operating frequency f opr1 tf At character clock of 8 XIN 30 MHz Operating frequency f opr2 At character clock less than 8 XIN 25 MHz For Information Equipment MN89302 Electrical Characteristics VDD=4.75 to 5.25V, V SS=0.00V, f=30MHz, Ta=0 to 70˚C Parameter Power supply current Symbol IDD0 Conditions VI =VDD or VSS ,V DD=5.0V IDD1 IDD2 min typ max 160 Unit mA VI =VDD or VSS ,V DD=5.0V 15 mA VI =VDD or VSS ,V DD=5.0V 75 mA during operation Power supply current in the SUSPEND mode Power supply current in the STANDBY mode "H" level input voltage 1 VIH1 2.0 VDD V VIH2 VDD × 0.7 VDD V V IL1 0 0.8 V V IL2 0 VDD × 0.3 V AEN ,SBHE ,IOWR ,IORD , SMEMW ,SMEMR , REFRESH ,A21 to 20 , SA19 to 0 ,SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "H" level input voltage 2 TEST ,MINTEST , SCANTEST ,RAS ,UCAS , LCAS ,BACKON ,LCDON , LOGICON ,MA9 to 0 , RESET "L" level input voltage 1 AEN ,SBHE ,IOWR ,IORD , SMEMW ,SMEMR , REFRESH ,A21 to 20 , SA19 to 0 ,SD15 to 0 , MD15 to 0 ,BIOSEN , IOCHRDY "L" level input voltage 2 TEST ,MINTEST , SCANTEST ,RAS ,UCAS , LCAS ,BACKON ,LCDON , LOGICON ,MA9 to 0 , RESET Input leakage current 1 ILI1 VI =VDD or VSS ±20 µA ILI2 VI =VDD or VSS ±10 µA TEST ,MINTEST , SCANTEST Input leakage current 2 AEN ,SBHE ,IOWR ,IORD , SMEMW ,SMEMR , REFRESH ,A21 to 20 , SA19 to 0 ,RESET MN89302 For Information Equipment Electrical Characteristics (continued) VDD=4.75 to 5.25V, V SS=0.00V, f=30MHz, Ta=0 to 70˚C Parameter Symbol Pull-down resistance RPD1 "H" level output voltage 1 V OH1 Conditions min VI =VDD ,VDD=5.0V IO =–2.0mA typ max 30 Unit kΩ VDD – 0.6 V VDD – 0.6 V VDD – 0.6 V VDD – 0.6 V V DD – 0.6 V VI =VDD or VSS BACKON ,LCDON , LOGICON ,SD15 to 0 , MD15 to 0 ,BIOSEN "H" level output voltage 2 V OH2 IO =–4.0mA VI =VDD or VSS WE ,MA9 to 0 ,RAS , UCAS ,LCAS "H" level output voltage 3 V OH3 IO =–8.0mA VI =VDD or VSS DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 "H" level output voltage 4 V OH4 IOCHRDY "H" level output voltage 5 VI =VDD or VSS V OH5 IOCS16 ,MEMCS16 "L" level output voltage 1 IO =–12.0mA IO =–16.0mA VI =VDD or VSS VOL1 IO =2.0mA 0.4 V 0.4 V 0.4 V 0.4 V 0.4 V ±10 µA VI =VDD or VSS BACKON ,LCDON , LOGICON ,MD15 to 0 "L" level output voltage 2 VOL2 IO =4.0mA VI =VDD or VSS SD15 to 0 ,MA9 to 0 ,RAS , UCAS ,LCAS ,WE ,BIOSEN "L" level output voltage 3 VOL3 IO =8.0mA VI =VDD or VSS DCLK ,DISP ,LP ,FP , UD7 to 0 ,LD7 to 0 "L" level output voltage 4 VOL4 IO =12.0mA VOL5 IO =16.0mA IOCHRDY "L" level output voltage 5 VI =VDD or VSS IOCS16 ,MEMCS16 Output leakage current VI =VDD or VSS ILO VO =High-impedance state IOCS16 ,BACKON , VI =VDD or VSS MA9 to 0 ,MEMCS16 , VO =VDD or VSS UCAS ,LCAS ,RAS , LOGICON ,LCDON , SD15 to 0 ,MD15 to 0 , BIOSEN ,IOCHRDY For Information Equipment MN89302 Timing Chart for LCD Panel Outputs FP LP DCLK LD7/UD7 R1 B3 G638 R1 B3 G6 LD6/UD6 G1 R4 B638 G1 R4 B6 LD5/UD5 B1 G4 R639 B1 G4 R7 LD4/UD4 R2 B4 G639 R2 B4 G7 LD3/UD3 G2 R5 B639 G2 R5 B7 LD2/UD2 B2 G5 R640 B2 G5 R8 LD1/UD1 R3 B5 G640 R3 B5 G8 LD0/UD0 G3 R6 B640 G3 R6 B8 FP LP UD 240 lines 1 line 2 lines 3 lines 4 lines 5 lines LD 480 lines 241 lines 242 lines 243 lines 244 lines 245 lines 1 1 line 2 lines · · · · · 2 3 R1 G1 B1 R2 G2 B2 R3 G3 B3 UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 UD7 640 R640 G640 B640 UD2 UD1 UD0 First byte of data Upper screen 240 lines 241 lines 242 lines · · · · · · · 480 lines R1 G1 B1 R2 G2 B2 R3 G3 B3 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LD7 First byte of data Lower screen R640 G640 B640 LD2 LD1 LD0 MN89302 For Information Equipment Application Circuit Example BIOS CE(20) SD[15:0] BIOSEN Address[21:0] XOUT XIN RESET UD[7:0] AEN LD[7:0] SBHE BACKON IOWR IORD LCDON MN89302 SMEMW LOGICON SMEMR LP REFRESH FP IOCHRDY DISP 4MDRAM ISA bus DCLK MA[9:0] RAS UCAS LCAS WE BIOSEN IOCS16 MD[15:0] MEMCS16 LCD panel For Information Equipment MN89302 Package Dimensions (Unit: mm) QFH128-P-1818 20.0±0.2 18.0±0.2 96 65 64 18.0±0.2 20.0±0.2 (1.25) 97 0.1 SEATING PLANE 0 to 10° 1.0±0.2 +0.10 32 0.2±0.1 0.15–0.05 0.5 3.4±0.3 1 3.3±0.2 (1.25) 33 0.1±0.1 128 0.5±0.2