® MPC800 High Speed CMOS ANALOG MULTIPLEXER FEATURES ● HIGH SPEED 100ns Access Time 800ns Settling to 0.01% 250ns Settling to 0.1% ● USER-PROGRAMMABLE 16-Channel Single-Ended or 8-Channel Differential ● SELECTABLE TTL OR CMOS COMPATIBILITY ● WILL NOT SHORT SIGNAL SOURCES — Break-Before-Make Switching ● SELF-CONTAINED WITH INTERNAL CHANNEL ADDRESS DECODER ● 28-PIN HERMETIC DUAL-IN-LINE PACKAGE DESCRIPTION The MPC800 is a high speed multiplexer that is userprogrammable for 16-channel single-ended operation or 8-channel differential operation and for TTL or CMOS compatibility. The MPC800 features a self-contained binary address decoder. It also has an enable line which allows the user to inhibit the entire multiplexer thereby facilitating channel expansion by adding additional multiplexers. High quality processing is employed to produce CMOS FET analog channel switches which have low leakage current, low ON resistance, high OFF resistance, low feedthrough capacitance, and fast settling time. Two models are available, the MPC800KG for operation from 0°C to +75°C. International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © PDS-463A 1985 Burr-Brown Corporation Printed in U.S.A. April, 1996 SPECIFICATIONS ELECTRICAL At TA = +25°C and ±VCC = 15V, unless otherwise noted. MPC800KG PARAMETER MIN ANALOG INPUTS Voltage Range Maximum Overvoltage Number of Input Channels Differential Single-Ended Reference Voltage Range(1) ON Characteristics(2) ON Resistance (RON) at +25°C Over Temperature Range R ON Drift vs Temperature R ON Mismatch ON Channel Leakage Over Temperature Range ON Channel Leakage Drift OFF Characteristics OFF Isolation OFF Channel Input Leakage Over Temperature Range OFF Channel Input Leakage Drift OFF Channel Output Leakage Over Temperature Range OFF Channel Output Leakage Drift Output Leakage (All channels disabled)(3) Output Leakage with Overvoltage +16V Input –16V Input DIGITAL INPUTS Over Temperature Range TTL (4) Logic “0” (VAL) Logic “1” (VAH) IAH IAL TTL Input Overvoltage CMOS Logic “0” (VAL) Logic “1” (VAH) CMOS Input Overvoltage Address A3 Overvoltage Digital Input Capacitance Channel Select (5) Single-Ended Differential Enable TYP MAX UNITS –15 –VCC –2 +15 +VCC +2 V V 8 16 6 10 V 750 1000 Ω Ω 100 Ω nA nA 50 dB nA nA 100 nA nA 620 700 See Typical Performance Curves < 10 0.04 0.6 See Typical Performance Curves 90 0.01 0.38 See Typical Performance Curves 0.035 0.48 See Typical Performance Curves 0.02 nA < 0.35 < 0.65 mA mA 0.8 2.4 0.05 4 –6 1 25 6 0.3VREF 0.7VREF –2 –VCC –2 +VCC +2 +VCC +2 5 V V µA µA V V V V V pF 4-bit Binary Code One of 16 3-bit Binary Code One of 8 Logic “0” Inhibits All Channels POWER REQUIREMENTS Over Temperature Range Rated Supply Voltage Maximum Voltage Between Supply Pins Total Power Dissipation Allowable Total Power Dissipation(6) Supply Drain (+25°C) At 1MHz Switching Speed At 100kHz Switching Speed ±15 V 33 525 1200 +35, –39 +25, –29 V mW mW mA mA The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® MPC800 2 SPECIFICATIONS (CONT) ELECTRICAL At TA = +25°C and ±VCC = 15V, unless otherwise noted. MPC800KG PARAMETER MIN DYNAMIC CHARACTERISTICS Gain Error Crosstalk(7) TOPEN (Break-before-make delay) Access Time at +25°C Over Temperature Range Settling Time(8) to 0.1% (20mV) to 0.01% (2mV) Common-Mode Rejection (Differential) DC 60Hz OFF Channel Input Capacitance, CS OFF Channel Output Capacitance, CO OFF Input to Output Capacitance, CDS TYP MAX UNITS < 0.0003 % See Typical Performance Curves 20 100 120 TEMPERATURE MPC800KG Specification Storage ns ns ns 150 200 250 800 ns ns > 125 > 75 2.5 18 0.02 dB dB pF pF pF 0 –65 °C °C +75 +150 NOTES: (1) Reference voltage controls noise immunity, normally left open for TTL compatibility and connected to VDD for CMOS compatibility. (2) VIN = ±10V, IOUT = 100µA. (3) Single-ended mode. (4) Logic levels specified for VREF (pin 13) open. (5) For single-ended operation, connect output A (pin 28) to output B (pin 2) and use A3 (pin 14) as an address line. For differential operation connect A3 to –VCC. (6) Derate 8mW/°C above T A = +75°C. (7) 10Vp-p sine wave on all unused channels. See Typical Performance Curves. (8) For 20V step input to ON channel, into 1kΩ load. PIN CONFIGURATION ORDERING INFORMATION MODEL Top View MPC800KG +VCC 1 28 Out A Out B 2 27 –VCC NC 3 26 IN8/8A IN16/8B 4 25 IN7/7A IN15/7B 5 24 IN6/6A IN14/6B 6 23 IN5/5A IN13/5B 7 22 IN4/4A IN12/4B 8 21 IN3/3A IN11/3B 9 20 IN2/2A IN10/2B 10 19 IN1/1A IN9/1B 11 PACKAGE TEMPERATURE RANGE Single-Wide Cerdip –0°C to +75°C PACKAGE INFORMATION MODEL MPC800KG PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Single-Wide Cerdip 228 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. 18 ENABLE GND 12 17 A0 VREF 13 16 A1 A3 14 15 A2 ® 3 MPC800 TYPICAL PERFORMANCE CURVES At TA = +25°C and ±VCC = 15V, unless otherwise noted. LEAKAGE CURRENTS vs TEMPERATURE 0.1 100 Leakage Current (nA) 1000 0.01 0.001 0.0001 “ON” Channel 10 “OFF” Output 1 “OFF” Input 0.1 0.00001 0.01 1k 100 10k 100k 1M 10M 25 35 Signal Frequency (Hz) 45 55 65 75 65 75 Temperature (°C) COMBINED CMR vs FREQUENCY FOR MODEL 3630 AND MPC800 RON DRIFT vs TEMPERATURE 500 140 G = 1000 400 100 RON (Ω) CMR (dB) 120 Balanced Source 80 300 200 Unbalanced = 1kΩ 100 60 Unbalanced = 10kΩ 0 40 100 10 1k 10k 100k 25 1M SETTLING TIME vs SOURCE RESISTANCE (10V Step Change, RL = 1kΩ) 1000 800 To 0.01% 600 400 To 0.1% 200 0 0.01 0 0.1 1 10 100 Source Resistance (kΩ) ® MPC800 35 45 55 Temperature (°C) Frequency (Hz) Settling Time (ns) Cross Talk (% of OFF Channel Signal) CROSS TALK vs SIGNAL FREQUENCY 1 4 DISCUSSION OF PERFORMANCE Input Offset Voltage Bias and leakage currents generate an input offset voltage as a result of the IR drop across the multiplexer ON resistance and source resistance. A load bias current of 10nA, a leakage current of 1nA, and an ON resistance of 700Ω will generate an offset voltage of 19µV if a 1000Ω source is used, and 118µV if a 10kΩ source is used. In general, for the MPC800 the offset voltage at the output is determined by: STATIC TRANSFER ACCURACY The static or DC transfer accuracy of transmitting the multiplexer input voltage to the output depends on the channel ON resistance (RON), the load impedance, the source impedance, the load bias current, and the multiplexer leakage current. VOFFSET = (IB + IL)(RON + RSOURCE) where: Single-Ended Multiplexer Static Accuracy The major contributors to static transfer accuracy for singleended multiplexers are: IB = Bias current of device multiplexer is driving IL = Multiplexer leakage current RON = Multiplexer ON resistance RSOURCE = Source resistance Source resistance loading error Multiplexer ON resistance error DC offset error caused by both load bias current and multiplexer leakage current. Differential Multiplexer Static Accuracy Static accuracy errors in a differential multiplexer are difficult to control, especially when it is used for multiplexing low level signals with full scale ranges of 10mV to 100mV. Resistive Loading Errors The source and load impedances will determine the ON resistance loading errors. To minimize these errors: The matching properties of the multiplexer, source and output load play a very important part in determining the transfer accuracy of the multiplexer. The source impedance unbalance, common-mode impedance, load bias current mismatch, load differential impedance mismatch, and common-mode impedance of the load all contribute errors to the multiplexer. The multiplexer ON resistance mismatch, leakage current mismatch and ON resistance also contribute to differential errors. • Keep loading impedance as high as possible. This minimizes the resistive loading effects of the source resistance and multiplexer ON resistance. As a guideline, load impedance of 108Ω or greater will keep resistive loading errors to 0.002% or less for 1000Ω source impedances. A 106Ω load impedance will increase source loading error to 0.2% or more. • Use sources with impedances as low as possible. A 1000Ω source resistance will present less than 0.002% loading error and 10kΩ source resistance will increase source loading error 0.02% with a 108Ω load impedance. Referring to Figure 2, the effects of these errors can be minimized by following the general guidelines described in this section, especially for low level multiplexing applications. Input resistive loading errors are determined by the following relationship (see Figure 1): RS1A Source and Multiplexer Resistive Loading Error RON1A I BiasA Z Load ∈(RS + RON) = RS + RON RS + RON + RL x 100% ILA VCC1 RCM where, RS = RSOURCE RL = Load resistance ROS = Multiplexer ON resistance 1 RS1B RON1B RD/2 CD/2 CCM I BiasB CD/2 RCM RD/2 RS8A ROFF8A ILB VCC8 VCC16 RS1 RON RCM8 I Bias RS8B ROFF8B Vm IL VCC1 RS16 FIGURE 2. MPC800 Static Accuracy Equivalent Circuit (Differential Operation). Measured Voltage ROFF Z Load Load (Output Device) Characteristics • Use devices with very low bias current. Generally FET input amplifiers should be used for low level signals less than 50mV FSR. Low bias current bipolar input amplifiers are acceptable for signal ranges higher than 50mV FSR. Bias current matching will determine input offset. VCC16 FIGURE 1. MPC800 Static Accuracy Equivalent Circuit (Single-ended Operation). ® 5 MPC800 SETTLING TIME Settling time is the time required for the multiplexer to reach and maintain an output within a specified error band of its final value in response to a step input. The settling time of the MPC800 is primarily due to the channel capacitance and a combination of resistances which include the source and load resistances. • The system DC common-mode rejection (CMR) can never be better than the combined CMR of the multiplexer and driven load. System CMR will be less than the device which has the lower CMR figure. • Load impedances, differential and common-mode should be 1010Ω or higher. If the parallel combination of the source and load resistance times the total channel capacitance is kept small, then the settling time is primarily affected by internal RCs. For the MPC800, the internal capacitance is approximately 20pF differential or 40pF single-ended. With external capacitance neglected, the time constant of source resistance in parallel with load resistance and the internal capacitance should be kept less than 40ns. This means the source resistance should be kept to less than 2kΩ (assume high load resistance) to maintain fast settling times. Source Characteristics • The source impedance unbalance will produce offset, common-mode, and channel-to-channel gain scatter errors. Use sources which do not have large impedance unbalances if at all possible. • Keep source impedances as low as possible to minimize resistive loading errors. • Minimize ground loops. If signal lines are shielded, ground all shields to a common point at the system analog common. If the MPC800 is used for multiplexing high level signals of 1V to 10V full scale ranges, the foregoing precautions should be taken, but the parameters are not as critical as for low level signal applications. ACCESS TIME This is the time required for the CMOS FET to turn ON after a new digital code has been applied to the Channel Address inputs. It is measured from the 50 percent point of the address input signal to the 90 percent point of the analog signal seen at the output for a 10V signal change between channels. Load Source Node A RLOAD CLOAD CS CROSSTALK Crosstalk is the amount of signal feedthrough from the 7 differential or 15 signal-ended OFF channels appearing at the multiplexer output. Crosstalk is caused by the voltage divider effect of the OFF channel, OFF resistance, and junction capacitances in series with the RON and RSOURCE impedance of the ON channel. Crosstalk is measured with a RSOURCE FIGURE 3. Settling Time Effect (Single-ended). RSA Node A RDA CSA CDA RCMS Source CCMS Load CSB Node B RSB FIGURE 4. Settling and Common-Mode Effects (Differential). ® MPC800 6 RDB CDB 20Vp-p, 1000Hz sine wave applied to all OFF channels. The crosstalk for these multiplexers is shown in the Typical Performance Curves. connections and/or multiplexer output lines. This will help common-mode capacitance balance and reduce stray signal pickup. If shields are used, all shields should be connected as close as possible to system analog common or to the common-mode guard driver. COMMON-MODE REJECTION (Differential Mode Only) The matching properties of the load, multiplexer and source affect the common-mode rejection (CMR) capability of a differentially multiplexed system. CMR is the ability of the multiplexer and input amplifier to reject signals that are common to both inputs, and to pass on only the signal difference to the output. Protection is provided for commonmode signals of ±2V above the power supply voltages with no damage to the analog switches. LOGIC LEVELS The logic level is user-programmable as either TTL-compatible by leaving the VREF (pin 13) open or CMOS-compatible by connecting the VREF to VDD (CMOS supply voltage). 16-CHANNEL SINGLE-ENDED OPERATION To use the MPC800 as a 16-channel single-ended multiplexer, output A (pin 28) is connected to output B (pin 2) to form a single output, then all four address lines (A0, A1, A2 and A3) are used to address the correct channel. The CMR of the MPC800 and Burr-Brown’s model 3630 instrumentation amplifier is 120dB at DC to 10Hz with a 6dB/octave rolloff to 80dB at 1000Hz. This measurement of CMR is shown in the Typical Performance Curves and is made with a Burr-Brown model 3630 instrumentation amplifier connected for a signal of 1000 and with source unbalance of 10kΩ. 1kΩ and no unbalance. The MPC800 can also be used as a dual 8-channel singleended multiplexer by not connecting output A and B, but then only one channel in one of the multiplexers can be addressed at a time. Factors which will degrade multiplexer and system DC CMR are: 8-CHANNEL DIFFERENTIAL OPERATION To use the MPC800 as an 8-channel differential multiplexer, connect address line A3 to –VCC, then use the remaining three address lines (A0, A1 and A2) to address the correct channel. The differential inputs are the pairs of A1 and B1, A2 and B2, etc. • Amplifier bias current and differential impedance mismatch. • Load impedance mismatch. • Multiplexer impedance and leakage current mismatch. • Load and source common-mode impedance. AC CMR rolloff is determined by the amount of commonmode capacitances (absolute and mismatch) from each signal line to ground. Larger capacitances will limit CMR at higher frequencies; thus, if good CMR is desired at higher frequencies, the common-mode capacitances and unbalance of signal lines and multiplexer to amplifier wiring must be minimized. Use twisted-shielded pair signal lines wherever possible. TRUTH TABLES MPC800 used as 16-channel single-ended multiplexer or 8channel dual multiplexer. USE A3 AS DIGITAL ADDRESS INPUT INSTALLATION AND OPERATING INSTRUCTIONS The ENABLE input, pin 18, is included for expansion of the number of channels on a single-node as illustrated in Figure 5. With the ENABLE line at a logic 1, the channel is selected by the Channel Select Address (shown in the Truth Tables). If ENABLE is at logic 0, all channels are turned OFF, even if the Channel Address Lines are active. If the ENABLE line is not to be used, simply tie it to logic 1. For the best settling time, the input wiring and interconnections between multiplexer output and driven devices should be kept as short as possible. When driving the digital inputs from TTL, open collector output with pullup resistors are recommended. “ON” CHANNEL TO ENABLE A3 A2 A1 A0 OUT A OUT B L X X X X None None H L L L L 1A None H L L L H 2A None H L L H L 3A None H L L H H 4A None H L H L L 5A None H L H L H 6A None H L H H L 7A None H L H H H 8A None H H L L L None 1B H H L L H None 2B H H L H L None 3B H H L H H None 4B H H H L L None 5B H H H L H None 6B H H H H L None 7B H H H H H None 8B For 16-channel single-ended function, tie “out A” to “out B”, for dual 8-channel function use the A3 address pin to select between MUX A and MUX B, where MUX A is selected with A3 low. To preserve common-mode rejection of the MPC800 use twisted-shielded pair wire for signal lines and inter-tier ® 7 MPC800 Two-Tier Expansion Up to seventeen MPC800s can be connected in a two-tier structure to form a 256-channel single-ended multiplexer (see Figure 6) or up to nine MPC800s can be connected in a two-tier structure to form a 64-channel differential multiplexer. Programming is accomplished with an 8-bit address. MPC800 used as 8-channel differential multiplexer. A3 CONNECT TO –VCC “ON” CHANNEL TO ENABLE A2 A1 A0 OUT A OUT B L X X X None None H L L L 1A 1B H L L H 2A 2B H L H L 3A 3B H L H H 4A 4B H H L L 5A 5B H H L H 6A 6B H H H L 7A 7B H H H H 8A 8B Single vs Multitiered Channel Expansion In addition to reducing programming complexity, two-tier configuration offers the added advantages over single-node expansion of reduced OFF channel current leakage (reduced offset), better CMR, and a more reliable configuration if a channel should fail in the ON condition (short). Should a channel fail ON in the single-node configuration, data cannot be taken from any channel, whereas only one-channel group is failed (8 or 16) in the multitiered configuration. CHANNEL EXPANSION Single-Tier Expansion Up to four MPC800s can be connected to a single node to form a 64-channel single-ended multiplexer or up to eight MPC800s can be connected to two nodes to form a 64-channel differential multiplexer. Programming is accomplished with a 6-bit address and a 1-of-4 decoder for 64-channel single-ended expansion (see Figure 5), and an 8-bit address and a 1-of-8 decoder for 64-channel differential expansion. The decoder drives the enable inputs of the MPC800, turning on only one multiplexer at a time. 16 Analog Inputs In16 Enable Out A Out B 1 of 4 Decoder 16 Analog Inputs A0 A1 A2 A3 In1 In2 In3 MPC800 8-Bit Channel Address Generator Multiplexer Output A0 A1 A2 A3 In1 In2 In3 MPC800 In16 Enable Out A Out B Enable Out A Out B A0 A1 A2 A3 In1 In2 In3 MPC800 In16 To multiplexers 3 and 4 64-channel single-tier expansion (single-ended) A0 A1 A2 A3 In1 In2 In3 MPC800 In16 Enable Out A Out B Multiplexer Output Enable Out A Out B To multiplexers 3 through 16 256-channel two-tier expansion (single-ended) FIGURE 5. 32- to 64-Channel, Single-tier Expansion. FIGURE 6. Channel Expansion up to 256 Channels Using 16 X 16 Two-tiered Expansion. ® MPC800 A0 A1 A2 A3 In1 In2 In3 MPC800 In16 16 Analog Inputs 16 Analog Inputs 6-Bit Channel Address Generator 8