FREESCALE MRF1550N

Freescale Semiconductor
Technical Data
Document Number: MRF1550N
Rev. 13, 6/2008
RF Power Field Effect Transistors
MRF1550NT1
MRF1550FNT1
N - Channel Enhancement - Mode Lateral MOSFETs
Designed for broadband commercial and industrial applications with frequencies to 175 MHz. The high gain and broadband performance of these devices
make them ideal for large - signal, common source amplifier applications in
12.5 volt mobile FM equipment.
• Specified Performance @ 175 MHz, 12.5 Volts
Output Power — 50 Watts
Power Gain — 14.5 dB
Efficiency — 55%
• Capable of Handling 20:1 VSWR, @ 15.6 Vdc, 175 MHz, 2 dB Overdrive
Features
• Excellent Thermal Stability
• Characterized with Series Equivalent Large - Signal Impedance Parameters
• Broadband- Full Power Across the Band: 135 - 175 MHz
• 200_C Capable Plastic Package
• N Suffix Indicates Lead - Free Terminations. RoHS Compliant.
• In Tape and Reel. T1 Suffix = 500 Units per 44 mm, 13 inch Reel.
175 MHz, 50 W, 12.5 V
LATERAL N - CHANNEL
BROADBAND
RF POWER MOSFETs
CASE 1264 - 10, STYLE 1
TO - 272- 6 WRAP
PLASTIC
MRF1550NT1
CASE 1264A - 03, STYLE 1
TO - 272- 6
PLASTIC
MRF1550FNT1
Table 1. Maximum Ratings
Rating
Symbol
Value
Unit
Drain- Source Voltage
VDSS
- 0.5, +40
Vdc
Gate- Source Voltage
VGS
± 20
Vdc
ID
12
Adc
PD
165
0.50
W
W/°C
Storage Temperature Range
Tstg
- 65 to +150
°C
Operating Junction Temperature
TJ
200
°C
Symbol
Value(2)
Unit
RθJC
0.75
°C/W
Drain Current — Continuous
Total Device Dissipation @ TC = 25°C
Derate above 25°C
(1)
Table 2. Thermal Characteristics
Characteristic
Thermal Resistance, Junction to Case
Table 3. Moisture Sensitivity Level
Test Methodology
Per JESD 22 - A113, IPC/JEDEC J - STD - 020
Rating
Package Peak Temperature
Unit
1
260
°C
TJ – TC
1. Calculated based on the formula PD =
RθJC
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
RF Device Data
Freescale Semiconductor
MRF1550NT1 MRF1550FNT1
1
Table 4. Electrical Characteristics (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
IDSS
—
—
1
μAdc
Gate- Source Leakage Current
(VGS = 10 Vdc, VDS = 0 Vdc)
IGSS
—
—
0.5
μAdc
Gate Threshold Voltage
(VDS = 12.5 Vdc, ID = 800 μA)
VGS(th)
1
—
3
Vdc
Drain- Source On - Voltage
(VGS = 5 Vdc, ID = 1.2 A)
RDS(on)
—
—
0.5
Ω
Drain- Source On - Voltage
(VGS = 10 Vdc, ID = 4.0 Adc)
VDS(on)
—
—
1
Vdc
Input Capacitance (Includes Input Matching Capacitance)
(VDS = 12.5 Vdc, VGS = 0 V, f = 1 MHz)
Ciss
—
—
500
pF
Output Capacitance
(VDS = 12.5 Vdc, VGS = 0 V, f = 1 MHz)
Coss
—
—
250
pF
Reverse Transfer Capacitance
(VDS = 12.5 Vdc, VGS = 0 V, f = 1 MHz)
Crss
—
—
35
pF
Gps
—
14.5
—
dB
η
—
55
—
%
Off Characteristics
On Characteristics
Dynamic Characteristics
RF Characteristics (In Freescale Test Fixture)
Common- Source Amplifier Power Gain
(VDD = 12.5 Vdc, Pout = 50 Watts, IDQ = 500 mA)
f = 175 MHz
Drain Efficiency
(VDD = 12.5 Vdc, Pout = 50 Watts, IDQ = 500 mA)
f = 175 MHz
MRF1550NT1 MRF1550FNT1
2
RF Device Data
Freescale Semiconductor
VGG
C10
C9
C8
+
R4
C20
C21
R3
C19
C18
Z9
L4
C13
C14
VDD
+
L5
C7
R2
Z6
R1
N1
RF
INPUT
Z1
L1
Z2
Z3
L2
Z4
Z5
C2
C4
C3
B1
C1
C2
C3
C4, C16
C5
C6
C7, C17
C8, C18
C9, C19
C10
C11, C12
C13
C14
C15
C20
L1
L2
L3
Z8
C11
C12
L3
Z10
Z11 C17
N2
RF
OUTPUT
DUT
C6
C1
Z7
C15
C16
C5
L4
L5
N1, N2
R1
R2
R3
R4
Z1
Z2
Z3
Z4
Z5, Z6
Z7
Z8
Z9
Z10
Z11
Board
Ferroxcube #VK200
180 pF, 100 mil Chip Capacitor
10 pF, 100 mil Chip Capacitor
33 pF, 100 mil Chip Capacitor
24 pF, 100 mil Chip Capacitors
160 pF, 100 mil Chip Capacitor
240 pF, 100 mil Chip Capacitor
300 pF, 100 mil Chip Capacitors
10 μF, 50 V Electrolytic Capacitors
0.1 μF, 100 mil Chip Capacitors
470 pF, 100 mil Chip Capacitor
200 pF, 100 mil Chip Capacitors
22 pF, 100 mil Chip Capacitor
30 pF, 100 mil Chip Capacitor
6.8 pF, 100 mil Chip Capacitor
1,000 pF, 100 mil Chip Capacitor
18.5 nH, Coilcraft #A05T
5 nH, Coilcraft #A02T
1 Turn, #24 AWG, 0.250″ ID
1 Turn, #26 AWG, 0.240″ ID
3 Turn, #24 AWG, 0.180″ ID
Type N Flange Mounts
5.1 Ω, 1/4 W Chip Resistor
39 Ω Chip Resistor (0805)
1 kΩ, 1/8 W Chip Resistor
33 kΩ, 1/4 W Chip Resistor
1.000″ x 0.080″ Microstrip
0.400″ x 0.080″ Microstrip
0.200″ x 0.080″ Microstrip
0.200″ x 0.080″ Microstrip
0.100″ x 0.223″ Microstrip
0.160″ x 0.080″ Microstrip
0.260″ x 0.080″ Microstrip
0.280″ x 0.080″ Microstrip
0.270″ x 0.080″ Microstrip
0.730″ x 0.080″ Microstrip
Glass Teflon®, 31 mils
Figure 1. 135 - 175 MHz Broadband Test Circuit
TYPICAL CHARACTERISTICS
0
80
135 MHz
VDD = 12.5 Vdc
IRL, INPUT RETURN LOSS (dB)
Pout , OUTPUT POWER (WATTS)
70
60
175 MHz
50
155 MHz
40
30
20
10
0
−5
175 MHz
−10
135 MHz
−15
155 MHz
VDD = 12.5 Vdc
0
1.0
2.0
4.0
3.0
Pin, INPUT POWER (WATTS)
5.0
Figure 2. Output Power versus Input Power
6.0
−20
10
20
30
40
50
60
Pout, OUTPUT POWER (WATTS)
70
80
Figure 3. Input Return Loss
versus Output Power
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
3
TYPICAL CHARACTERISTICS
16
80
175 MHz
GAIN (dB)
14
h, DRAIN EFFICIENCY (%)
15
135 MHz
155 MHz
13
12
11
70
155 MHz
60
175 MHz
135 MHz
50
40
VDD = 12.5 Vdc
10
10
20
30
40
50
60
Pout, OUTPUT POWER (WATTS)
70
VDD = 12.5 Vdc
30
10
80
Figure 4. Gain versus Output Power
70
80
80
155 MHz
135 MHz
h, DRAIN EFFICIENCY (%)
Pout , OUTPUT POWER (WATTS)
40
50
60
30
Pout, OUTPUT POWER (WATTS)
Figure 5. Drain Efficiency versus Output Power
70
65
175 MHz
60
155 MHz
55
175 MHz
70
135 MHz
60
50
VDD = 12.5 Vdc
Pin = 35 dBm
VDD = 12.5 Vdc
Pin = 35 dBm
50
200
400
800
600
IDQ, BIASING CURRENT (mA)
1000
40
200
1200
Figure 6. Output Power versus Biasing Current
400
600
800
IDQ, BIASING CURRENT (mA)
1000
1200
Figure 7. Drain Efficiency versus
Biasing Current
90
80
155 MHz
80
h, DRAIN EFFICIENCY (%)
Pout , OUTPUT POWER (WATTS)
20
70
155 MHz
135 MHz
60
175 MHz
50
70
175 MHz
135 MHz
60
50
IDQ = 500 mA
Pin = 35 dBm
40
30
10
11
12
13
14
VDD, SUPPLY VOLTAGE (VOLTS)
Figure 8. Output Power versus Supply Voltage
IDQ = 500 mA
Pin = 35 dBm
15
40
10
11
12
13
14
15
VDD, SUPPLY VOLTAGE (VOLTS)
Figure 9. Drain Efficiency versus Supply Voltage
MRF1550NT1 MRF1550FNT1
4
RF Device Data
Freescale Semiconductor
TYPICAL CHARACTERISTICS
MTTF FACTOR (HOURS X AMPS2)
1011
1010
109
108
90 100 110 120 130 140 150 160 170 180 190 200 210
TJ, JUNCTION TEMPERATURE (°C)
This above graph displays calculated MTTF in hours x ampere2
drain current. Life tests at elevated temperatures have correlated to
better than ±10% of the theoretical prediction for metal failure. Divide
MTTF factor by ID2 for MTTF in a particular application.
Figure 10. MTTF Factor versus Junction Temperature
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
5
Zo = 10 Ω
f = 175 MHz
f = 175 MHz
Zin
ZOL*
f = 135 MHz
f = 135 MHz
VDD = 12.5 V, IDQ = 500 mA, Pout = 50 W
Zin
f
MHz
Zin
Ω
ZOL*
Ω
135
4.1 + j0.5
1.0 + j0.6
155
4.2 + j1.7
1.2 + j.09
175
3.7 + j2.3
0.7 + j1.1
= Complex conjugate of source
impedance.
ZOL* = Complex conjugate of the load
impedance at given output power,
voltage, frequency, and ηD > 50 %.
Input
Matching
Network
Output
Matching
Network
Device
Under Test
Z
in
Z
*
OL
Figure 11. Series Equivalent Input and Output Impedance
MRF1550NT1 MRF1550FNT1
6
RF Device Data
Freescale Semiconductor
Table 5. Common Source Scattering Parameters (VDD = 12.5 Vdc)
IDQ = 500 mA
S11
S21
S12
S22
f
MHz
|S11|
∠φ
|S21|
∠φ
|S12|
∠φ
|S22|
∠φ
50
0.93
- 178
4.817
80
0.009
- 39
0.86
- 176
100
0.94
- 178
2.212
69
0.009
-3
0.88
- 175
150
0.95
- 178
1.349
61
0.008
-8
0.90
- 174
200
0.95
- 178
0.892
54
0.006
- 13
0.92
- 174
250
0.96
- 178
0.648
51
0.005
-7
0.93
- 174
300
0.97
- 178
0.481
47
0.004
-8
0.95
- 174
350
0.97
- 178
0.370
46
0.005
4
0.95
- 174
400
0.98
- 178
0.304
43
0.001
15
0.97
- 174
450
0.98
- 178
0.245
43
0.005
81
0.97
- 174
500
0.98
- 178
0.209
43
0.003
84
0.97
- 174
550
0.99
- 177
0.178
41
0.007
70
0.98
- 175
600
0.98
- 178
0.149
41
0.010
106
0.96
- 175
IDQ = 2.0 mA
S11
S21
S12
S22
f
MHz
|S11|
∠φ
|S21|
∠φ
|S12|
∠φ
|S22|
∠φ
50
0.93
- 177
4.81
80
0.003
- 119
0.93
- 178
100
0.94
- 178
2.20
69
0.006
4
0.93
- 178
150
0.95
- 178
1.35
61
0.003
-1
0.93
- 177
200
0.95
- 178
0.89
54
0.004
18
0.93
- 176
250
0.96
- 178
0.65
51
0.001
28
0.94
- 176
300
0.97
- 178
0.48
47
0.004
77
0.94
- 175
350
0.97
- 178
0.37
46
0.006
85
0.95
- 175
400
0.98
- 178
0.30
43
0.007
53
0.96
- 174
450
0.98
- 178
0.25
43
0.006
74
0.97
- 174
500
0.98
- 177
0.21
44
0.006
84
0.97
- 174
550
0.99
- 177
0.18
41
0.002
106
0.97
- 175
600
0.98
- 178
0.15
41
0.004
116
0.96
- 174
IDQ = 4.0 mA
S11
S21
S12
S22
f
MHz
|S11|
∠φ
|S21|
∠φ
|S12|
∠φ
|S22|
∠φ
50
0.97
- 179
5.04
87
0.002
- 116
0.94
- 179
100
0.96
- 179
2.43
82
0.006
42
0.94
- 178
150
0.96
- 179
1.60
77
0.004
13
0.94
- 177
200
0.96
- 179
1.14
74
0.003
43
0.95
- 176
250
0.97
- 179
0.89
71
0.004
65
0.95
- 175
300
0.97
- 179
0.71
68
0.006
68
0.95
- 175
350
0.97
- 179
0.57
67
0.006
74
0.97
- 174
(continued)
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
7
Table 5. Common Source Scattering Parameters (VDD = 12.5 Vdc) (continued)
IDQ = 4.0 mA (continued)
S11
S21
S12
S22
f
MHz
|S11|
∠φ
|S21|
∠φ
|S12|
∠φ
|S22|
∠φ
400
0.97
- 179
0.49
63
0.005
58
0.97
- 173
450
0.98
- 178
0.41
63
0.005
73
0.98
- 173
500
0.98
- 178
0.36
62
0.003
128
0.98
- 173
550
0.98
- 178
0.32
58
0.004
57
0.99
- 174
600
0.98
- 178
0.27
58
0.009
83
0.98
- 174
MRF1550NT1 MRF1550FNT1
8
RF Device Data
Freescale Semiconductor
APPLICATIONS INFORMATION
DESIGN CONSIDERATIONS
This device is a common - source, RF power, N - Channel
enhancement mode, Lateral Metal - Oxide Semiconductor
Field - Effect Transistor (MOSFET). Freescale Application
Note AN211A, “FETs in Theory and Practice”, is suggested
reading for those not familiar with the construction and characteristics of FETs.
This surface mount packaged device was designed primarily for VHF and UHF mobile power amplifier applications.
Manufacturability is improved by utilizing the tape and reel
capability for fully automated pick and placement of parts.
However, care should be taken in the design process to insure proper heat sinking of the device.
The major advantages of Lateral RF power MOSFETs include high gain, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mismatched loads without suffering damage.
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between all three terminals. The metal oxide gate structure
determines the capacitors from gate - to - drain (Cgd), and
gate - to - source (Cgs). The PN junction formed during fabrication of the RF MOSFET results in a junction capacitance
from drain - to - source (Cds). These capacitances are characterized as input (Ciss), output (Coss) and reverse transfer
(Crss) capacitances on data sheets. The relationships between the inter - terminal capacitances and those given on
data sheets are shown below. The Ciss can be specified in
two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate.
In the latter case, the numbers are lower. However, neither
method represents the actual operating conditions in RF applications.
Drain
Cgd
Gate
Cds
Ciss = Cgd + Cgs
Coss = Cgd + Cds
Crss = Cgd
Cgs
Source
DRAIN CHARACTERISTICS
One critical figure of merit for a FET is its static resistance
in the full - on condition. This on - resistance, RDS(on), occurs
in the linear region of the output characteristic and is specified at a specific gate - source voltage and drain current. The
drain - source voltage under these conditions is termed
VDS(on). For MOSFETs, VDS(on) has a positive temperature
coefficient at high temperatures because it contributes to the
power dissipation within the device.
BVDSS values for this device are higher than normally required for typical applications. Measurement of BVDSS is not
recommended and may result in possible damage to the device.
GATE CHARACTERISTICS
The gate of the RF MOSFET is a polysilicon material, and
is electrically isolated from the source by a layer of oxide.
The DC input resistance is very high - on the order of 109 Ω
— resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage to
the gate greater than the gate - to - source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gates of these devices are essentially capacitors. Circuits that leave the gate open - circuited or floating should be avoided. These conditions can
result in turn - on of the devices due to voltage build - up on
the input capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate - to - source. If gate protection is required, an external zener diode is recommended.
Using a resistor to keep the gate - to - source impedance low
also helps dampen transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate - drain capacitance. If the
gate - to - source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate - threshold voltage
and turn the device on.
DC BIAS
Since this device is an enhancement mode FET, drain current flows only when the gate is at a higher potential than the
source. RF power FETs operate optimally with a quiescent
drain current (IDQ), whose value is application dependent.
This device was characterized at IDQ = 500 mA, which is the
suggested value of bias current for typical applications. For
special applications such as linear amplification, IDQ may
have to be selected to optimize the critical parameters.
The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may
require a more elaborate bias system.
GAIN CONTROL
Power output of this device may be controlled to some degree with a low power dc control signal applied to the gate,
thus facilitating applications such as manual gain control,
ALC/AGC and modulation systems. This characteristic is
very dependent on frequency and load line.
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
9
AMPLIFIER DESIGN
Impedance matching networks similar to those used with
bipolar transistors are suitable for this device. For examples
see Freescale Application Note AN721, “Impedance
Matching Networks Applied to RF Power Transistors.”
Large - signal impedances are provided, and will yield a good
first pass approximation.
Since RF power MOSFETs are triode devices, they are not
unilateral. This coupled with the very high gain of this device
yields a device capable of self oscillation. Stability may be
achieved by techniques such as drain loading, input shunt
resistive loading, or output to input feedback. The RF test fixture implements a parallel resistor and capacitor in series
with the gate, and has a load line selected for a higher efficiency, lower gain, and more stable operating region.
Two - port stability analysis with this device’s
S - parameters provides a useful tool for selection of loading
or feedback circuitry to assure stable operation. See Freescale Application Note AN215A, “RF Small - Signal Design
Using Two - Port Parameters” for a discussion of two port
network theory and stability.
MRF1550NT1 MRF1550FNT1
10
RF Device Data
Freescale Semiconductor
PACKAGE DIMENSIONS
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
11
MRF1550NT1 MRF1550FNT1
12
RF Device Data
Freescale Semiconductor
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
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MRF1550NT1 MRF1550FNT1
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RF Device Data
Freescale Semiconductor
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
15
MRF1550NT1 MRF1550FNT1
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RF Device Data
Freescale Semiconductor
PRODUCT DOCUMENTATION
Refer to the following documents to aid your design process.
Application Notes
• AN211A: Field Effect Transistors in Theory and Practice
• AN215A: RF Small - Signal Design Using Two - Port Parameters
• AN721: Impedance Matching Networks Applied to RF Power Transistors
• AN1907: Solder Reflow Attach Method for High Power RF Devices in Plastic Packages
• AN3263: Bolt Down Mounting Method for High Power RF Transistors and RFICs in Over - Molded Plastic Packages
Engineering Bulletins
• EB212: Using Data Sheet Impedances for RF LDMOS Devices
REVISION HISTORY
The following table summarizes revisions to this document.
Revision
Date
12
Feb. 2008
Description
• Changed DC Bias IDQ value from 150 to 500 to match Functional Test IDQ specification, p. 9
• Replaced Case Outline 1264 - 09 with 1264 - 10, Issue L, p. 1, 11 - 13. Removed Drain - ID label from top
view and View Y - Y. Corrected cross hatch pattern and its dimensions (D2 and E2) on source contact.
Renamed E2 with E3. Added Pin 7 designation. Corrected positional tolerance for bolt hole radius. Added
JEDEC Standard Package Number.
• Replaced Case Outline 1264A - 02 with 1264A - 03, Issue D, p. 1, 14 - 16. Removed Drain - ID label from
View Y - Y. Corrected cross hatch pattern and its dimensions (D2 and E2) on source contact (Changed D2
and E2 dimensions from basic to .604 Min and .162 Min, respectively). Added dimension E3. Added Pin 7
designation. Corrected positional tolerance for bolt hole radius. Added JEDEC Standard Package Number.
• Added Product Documentation and Revision History, p. 17
13
June 2008
• Corrected specified performance values for power gain and efficiency on p. 1 to match typical
performance values in the functional test table on p. 2
MRF1550NT1 MRF1550FNT1
RF Device Data
Freescale Semiconductor
17
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MRF1550NT1 MRF1550FNT1
Document Number: MRF1550N
Rev. 13, 6/2008
18
RF Device Data
Freescale Semiconductor