E2E1013-27-Y4 ¡ Semiconductor MSM65514/65P514 ¡ Semiconductor ThisMSM65514/65P514 version: Jan. 1998 Previous version: Nov. 1996 High Performance 8-Bit Microcontroller GENERAL DESCRIPTION The MSM65514 is a high-performance 8-bit microcontroller that employs OKI original nX-8/50 CPU core. With a minimum instruction execution time of 400 ns (10MHz clock), the MSM65514 is capable of high-speed processing, and includes 16K bytes of program memory, 384 bytes of data memory, timers and serial ports on chip. Also available are the MSM65P514, which replaces the on-chip program memory with one-time PROM, and the MSM65X514, which uses external program memory. FEATURES • Operating range Operating frequency : Operating voltage Operating temperature • Memory space Internal program memory Internal data memory • Minimum instruction execution time • Powerful instruction set : : : : : : : • Abundant addressing modes • Multiplication/division operation functions : 8 ¥ 8 Æ 16 16 ÷ 8 Æ 16 ... 8 • I/O port Input-output port Input port • Timers : : : • Counters : • Capture input • Compare output • Serial ports : : : 6 ports ¥ 8 bits 1 port ¥ 8 bits 8-bit auto-reload timer ¥ 2 16-bit auto-reload timer ¥ 1 Watchdog timer ¥ 1 Time base counter ¥ 1 16-bit free-running counter ¥ 1 1 channel 2 channels Shift register ¥ 1 Serial port with baud rate generator (UART/synchronous) ¥ 1 3 15 • External interrupts : • Interrupt sources : • Package 64-pin plastic shrink DIP (SDIP64-P-750-1.78) : 64-pin plastic QFP (QFP64-P-1414-0.80-BK) : 68-pin plastic QFJ (PLCC) (QFJ68-P-S950-1.27): 0 to 10MHz (VDD=4.5 to 5.5V) 0 to 5MHz (VDD=2.7 to 5.5V) 2.7 to 5.5V –40 to +85°C 64K bytes 16K bytes 384 bytes 400ns @ 10MHz 83 basic instructions 8/16-bit operation instructions Bit manipulation instructions Compound function instructions (MSM65514-¥¥¥SS, MSM65P514¥¥¥SS) (MSM65514-¥¥¥GS-BK, MSM65P514-¥¥¥GS-BK) (MSM65514-¥¥¥JS, MSM65P514¥¥¥JS) ¥¥¥ indicates the code number. 1/23 OSC CONT. 8 BUS CONT. IR 8 AR BR PSW SP LMAR TBC 8 A8-15* WDT 16-bit TIMER T2CK* 16-bit FRC CAP¥1, CMP¥2 CAP* CMP0* CMP1* SIO 8-bit TIMER¥3** MUL/DIV AD0-7* RAM (384 bytes) GMAR PC ALU T/C 8 RD WR* ALE EA CPU CORE INST. DEC. VDD GND EXT.MEM. CONT. 8 I/O PORT 8-bit SHIFT-REG. TXD* RXD* T1OUT* T0CK* GATE* SFTO* SFTI* SFTCK* INT0* INT1* INT2* 2/23 * Secondary functions of ports ** One timer is used for the SIO baud rate generator. MSM65514/65P514 INTERRUPT CONT. P0 P1 P2 P3 P4 P5 P6 ¡ Semiconductor ROM (16K bytes) BLOCK DIAGRAM OSC0 OSC1 RESET HSTOP* ¡ Semiconductor MSM65514/65P514 PIN CONFIGURATION (TOP VIEW) P5.0 1 64 VDD P5.1 2 63 P6.7 P5.2 3 62 P6.6 P5.3 4 61 P6.5 P4.0 5 60 P6.4 P4.1 6 59 P6.3 P4.2 7 58 P6.2 P4.3 8 57 P6.1 P4.4 9 56 P6.0 P4.5 P4.6 10 11 55 54 P5.7 P5.6 P4.7 12 53 P5.5 P3.0/T2CK 13 52 P5.4 P3.1/CAP 14 51 P0.0/AD0 P3.2/CMP0 15 50 P0.1/AD1 P3.3/CMP1 16 49 P0.2/AD2 P3.4/INT2 P3.5/SFTO 17 18 48 47 P0.3/AD3 P0.4/AD4 P3.6/SFTI 19 46 P0.5/AD5 P3.7/SFTCK 20 45 P0.6/AD6 RESET 21 44 P0.7/AD7 P2.0/RXD 22 43 EA P2.1/TXD 23 42 ALE P2.2/INT0 24 41 RD P2.3/INT1/GATE P2.4/T0CK 25 26 40 39 P1.7/A15 P1.6/A14 P2.5/HSTOP 27 38 P1.5/A13 P2.6/WR 28 37 P1.4/A12 P2.7/T1OUT 29 36 P1.3/A11 OSC1 30 35 P1.2/A10 OSC0 GND 31 34 32 33 P1.1/A9 P1.0/A8 64-Pin Plastic Shrink DIP 3/23 ¡ Semiconductor MSM65514/65P514 P2.1/TXD 15 P2.2/INT0 16 49 P6.1 50 P6.2 54 P6.3 52 P6.4 53 P6.5 54 P6.6 55 P6.7 56 VDD 57 P5.0 58 P5.1 59 P5.2 60 P5.3 61 P4.0 62 P4.1 42 P0.1/AD1 41 P0.2/AD2 40 P0.3/AD3 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 35 EA 34 ALE 33 RD P1.7/A15 32 RESET 13 P2.0/RXD 14 43 P0.0/AD0 P1.6/A14 31 P3.6/SFTI 11 P3.7/SFTCK 12 44 P5.4 P1.5/A13 30 9 45 P5.5 P1.4/A12 29 P3.4/INT2 P3.5/SFTO 10 46 P5.6 P1.3/A11 28 8 47 P5.7 P1.2/A10 27 7 P3.3/CMP1 48 P6.0 P1.1/A9 26 P3.2/CMP0 P1.0/A8 25 6 GND 24 5 P3.1/CAP OSC0 23 P3.0/T2CK OSC1 22 4 P2.7/T1OUT 21 3 P4.7 P2.6/WR 20 P4.6 P2.5/HSTOP 19 2 P2.4/T0CK 18 1 P4.5 P2.3/INT1/GATE 17 P4.4 63 P4.2 64 P4.3 PIN CONFIGURATION (TOP VIEW) (Continued) 64-Pin Plastic QFP 4/23 ¡ Semiconductor MSM65514/65P514 44 RD 46 EA 45 ALE 48 P0.6/AD6 47 P0.7/AD7 50 P0.4/AD4 49 P0.5/AD5 52 NC 51 P0.3/AD3 54 P0.1/AD1 53 P0.2/AD2 56 P5.4 55 P0.0/AD0 58 P5.6 57 P5.5 60 P6.0 59 P5.7 PIN CONFIGURATION (TOP VIEW) (Continued) 35 NC 34 GND P5.1 3 P5.2 4 33 OSC0 32 OSC1 P5.3 5 P4.0 6 31 P2.7/T1OUT 30 P2.6/WR P4.1 7 P4.2 8 29 P2.5/HSTOP 28 P2.4/T0CK P4.3 9 27 P2.3/INT1/GATE P2.2/INT0 26 VDD 1 P5.0 2 P2.0/RXD 24 P2.1/TXD 25 37 P1.1/A9 36 P1.0/A8 P3.7/SFTCK 22 RESET 23 P6.7 67 NC 68 P3.5/SFTO 20 P3.6/SFTI 21 39 P1.3/A11 38 P1.2/A10 NC 18 P3.4/INT2 19 P6.5 65 P6.6 66 P3.2/CMP0 16 P3.3/CMP1 17 41 P1.5/A13 40 P1.4/A12 P3.0/T2CK 14 P3.1/CAP 15 P6.3 63 P6.4 64 P4.6 12 P4.7 13 43 P1.7/A15 42 P1.6/A14 P4.4 10 P4.5 11 P6.1 61 P6.2 62 NC: No-connection pin 68-Pin Plastic QFJ (PLCC) 5/23 ¡ Semiconductor MSM65514/65P514 PIN DESCRIPTION Basic Functions Function Symbol Type Power Supply VDD — +5V power supply GND — 0V ground OSC0 I System clock input pin. Quartz oscillator or ceramic oscillator is connected between OSC0 and OSC1. For external clock, input at OSC0, leaving OSC1 open. OSC1 O System clock output pin RESET I System reset input (program starts from address 0040H); internal pull-up resistance EA I Program memory select input pin. "L" level input for external program memory; "H" level input for internal program memory. RD O Read strobe signal during external memory access ALE O Address latch signal during external memory access PORT 0 I/O 8-bit Input-output port During external memory access, becomes address/data bus for address output, instruction fetch or data read/write along with ALE, RD and WR pins. PORT 1 I/O 8-bit Input-output port Address bus during external memory access PORT 2 PORT 3 PORT 4 PORT 5 I/O 8-bit Input-output port ¥ 4. Secondary functions shown in following table are added for ports 2 and 3. PORT 6 I Oscillation Control Port Description 8-bit Input port 6/23 ¡ Semiconductor MSM65514/65P514 Secondary Functions Symbol Type Description RXD I/O P2.0 secondary function UART: Input pin for serial port receive data. Synchronous: Input/output pin for serial port transmit/receive data. TXD O P2.1 secondary function UART: Output pin for serial port transmit data. Synchronous: Output pin for serial port synchronizing clock. INT0 I P2.2 secondary function External interrupt 0 input pin. INT1/GATE I P2.3 secondary functions External interrupt 1 input pin. Also used as input pin for gate signal for timer 0 count enable/disable. T0CK I P2.4 secondary function Timer 0 external clock input pin. HSTOP I P2.5 secondary function Hard stop mode input pin; stops system clock oscillation with "L" level input. WR O P2.6 secondary function Write strobe signal output pin during external data memory access. T1OUT O P2.7 secondary function Output pin for signal that 2-divided timer 1 overflow. T2CK I P3.0 secondary function Timer 2 external clock input pin. CAP I P3.1 secondary function Capture trigger input pin. CMP0 O P3.2 secondary function Compare output channel 0 output pin. CMP1 O P3.3 secondary function Compare output channel 1 output pin. INT2 I P3.4 secondary function External interrupt 2 input pin. SFTO O P3.5 secondary function Shift register data output pin. SFTI I P3.6 secondary function Shift register data input pin. SFTCK I/O P3.7 secondary function Shift register synchronizing clock input/output pin. 7/23 ¡ Semiconductor MSM65514/65P514 Port Circuit Configuration Type Port Data Bus PORT0 P0D 1 Electrical Characteristics (VDD=5V) Circuit Configuration P0.0/AD0 to P0.7/AD7 P0 DIR "H" Output Voltage: • VOH=3.75V • IOH=–400mA "L" Output Voltage: • VOL=0.4V • IOL=3.2mA External Memory Control Data Bus PORT1 P1D 2 P1.0/A8 to P1.7/A15 "H" Input Voltage: • VIH=2.4V "L" Input Voltage: • VIL=0.8V "H" Input Voltage: • VIH=2.4V "L" Input Voltage: • VIL=0.8V "H" Output Voltage: • VOH=3.75V • IOH=–200mA P1 DIR "L" Output Voltage: • VOL=0.4V • IOL=1.6mA External Memory Control "H" Input Voltage: • VIH=2.4V "L" Input Voltage: • VIL=0.8V Data Bus 3 P2.0/RXD, P2.1/TXD, P2.6/WR, P2.7/T1OUT, P3.2/CMP0, P3.3/CMP1, P3.5/SFTO, P3.7/SFTCK Px MOD Secondary Output Function PORTx PxD Px DIR Secondary Input Function (x=2 to 5) P2.6/WR "H" Output Voltage: • VOH=3.75V • IOH=–400mA "L" Output Voltage: • VOL=0.4V • IOL=3.2mA Excluding P2.6/WR "H" Output Voltage: • VOH=3.75V • IOH=–200mA "L" Output Voltage: • VOL=0.4V • IOL=1.6mA 8/23 ¡ Semiconductor MSM65514/65P514 Port Circuit Configuration (Continued) Type 4 Port P2.2/INT0, P2.3/INT1/GATE, P2.4/T0CK, P2.5/HSTOP, P3.0/T2CK, P3.1/CAP, P3.4/INT2, P3.6/SFTI, P4.0 to P4.7, P5.0 to P5.7 Electrical Characteristics (VDD=5V) Circuit Configuration Data Bus PORTx PxD Px DIR Secondary Input Function (x=2 to 5) 5 Data Bus P6.0 to P6.7 PORT6 "H" Input Voltage: • VIH=2.4V "L" Input Voltage: • VIL=0.8V "H" Output Voltage: • VOH=3.75V • IOH=–200mA "L" Output Voltage: • VOL=0.4V • IOL=1.6mA "H" Input Voltage: • VIH=2.4V "L" Input Voltage: • VIL=0.8V 9/23 ¡ Semiconductor MSM65514/65P514 MEMORY MAPS General Memory Space 0FFFFH External Memory Local Memory Space 1FFH Page 1 Data Memory 4000H 100H Program Memory 100H SFR Internal Memory 80H Vector Call Table Area Data Memory 40H 30H 20H 10H 0 Local Register Set 3 Local Register Set 2 Local Register Set 1 Local Register Set 0 Page 0 80H 40H 20H 0 Program Memory Interrupt Vector Table Area Vector Call Table Area ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Symbol Condition Rating Ta=25°C VDD –0.3 to 7.0 Input Voltage VI –0.3 to VDD+0.3 Output Voltage VO Power Dissipation PD Storage Temperature TSTG Unit V –0.3 to VDD+0.3 Ta=25°C per package 400 Ta=25°C per output 50 — –55 to +150 mW °C RECOMMENDED OPERATING CONDITIONS Symbol Condition Range VDD Refer to Figure 1 2.7 to 5.5 Memory Hold Voltage VDDMH fOSC=0 Hz 2.0 to 5.5 Oscillation Operating Frequency *1 fOSC Refer to Figure 1 1 to 10 MHz External Clock Operating Frequency fEXTCLK Refer to Figure 1 0 to 10 MHz Operating Temperature Top — –40 to +85 °C Parameter Supply Voltage Unit V *1 This is due to the standard of a crystal oscillator or resonator. 10/23 ¡ Semiconductor MSM65514/65P514 Ta=–40 to +85°C fOSC, fEXTCLK (MHz) 10 8 6 5 4 2 1 * Oscillates at 1MHz or more. 2 3 2.7 4 5 5.5 6 VDD (V) Figure 1. Operating Frequency vs. Power Supply Voltage 11/23 ¡ Semiconductor MSM65514/65P514 ELECTRICAL CHARACTERISTICS DC Characteristics 1 (VDD=4.5 to 5.5V) Parameter "H" Input Voltage 1 *1 (GND=0V, Ta=–40 to +85°C) Symbol Condition Min. Typ. Max. VIH1 — 2.4 — VDD+0.3 "H" Input Voltage 2 *2 VIH2 — 0.7VDD — VDD+0.3 "L" Input Voltage Unit VIL — –0.3 — 0.8 "H" Output Voltage 1 *3 VOH1 IOH=–200mA 0.75VDD — — "H" Output Voltage 2 *4 "L" Output Voltage 1 *3 VOH2 IOH=–400mA 0.75VDD — — VOL1 IOL=1.6mA — — 0.4 "L" Output Voltage 2 *4 VOL2 IOL=3.2mA — — 0.4 Input Lack Current 1 *5 ILI1 VI=VDD/0V — — ±1 Input Lack Current 2 *6 ILI2 VI=VDD/0V — — ±10 "L" Input Current *7 IIL VI=0V –40 –200 –400 Input Capacity CI f=1MHz, Ta=25°C 5V, Stop mode *8 — 5 — pF — — 50 mA — 20 40 mA Still Current Consumption IDDS Operating Current Consumption IDD *1 *2 *3 *4 *5 *6 *7 *8 10MHz, 5V, no load Refer to Fig.2 V mA Excluding OSC0 and RESET OSC0 and RESET Excluding P0, ALE, RD, P2.6/WR P0, ALE, RD, P2.6/WR EA, P6 Excluding RESET, EA, P6 RESET The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be loaded. 12/23 ¡ Semiconductor MSM65514/65P514 DC Characteristics 2 (2.7 £ VDD < 4.5V) (GND=0V, Ta=–40 to +85°C) Parameter "H" Input Voltage 1 *1 Symbol Condition Min. Typ. Max. VIH1 — 0.5VDD+0.2 — VDD+0.3 "H" Input Voltage 2 *2 VIH2 — 0.6VDD+0.4 — VDD+0.3 "L" Input Voltage Unit VIL — –0.3 — 0.15VDD+0.1 "H" Output Voltage 1 *3 VOH1 IOH=–10mA 0.75VDD — — "H" Output Voltage 2 *4 VOH2 IOH=–20mA 0.75VDD — — "L" Output Voltage 1 *3 VOL1 IOL=10mA — — 0.1 "L" Output Voltage 2 *4 VOL2 IOL=20mA — — 0.1 Input Lack Current 1 *5 ILI1 VI=VDD/0V — — ±1 Input Lack Current 2 *6 "L" Input Current *7 ILI2 VI=VDD/0V — — ±10 IIL VDD=2.7 to 3.3V, VI=0V –40 –120 –240 Input Capacity CI f=1MHz, Ta=25°C 3V, Stop mode *8 — 5 — pF — — 25 mA — 6 15 mA Still Current Consumption IDDS Operating Current Consumption IDD *1 *2 *3 *4 *5 *6 *7 *8 5MHz, 3V, no load Refer to Fig.2 V mA Excluding OSC0 and RESET OSC0 and RESET Excluding P0, ALE, RD, P2.6/WR P0, ALE, RD, P2.6/WR EA, P6 Excluding RESET, EA, P6 RESET The ports configured as inputs should be coupled to VDD or 0V. Other ports should not be loaded. 13/23 ¡ Semiconductor MSM65514/65P514 10MHz 50 Max. IDD (mA) 40 30 Typ. 20 10 2 3 4 5 VDD (V) 6 6MHz 50 IDD (mA) 40 Max. 30 20 Typ. 10 2 3 4 5 VDD (V) 6 2MHz 50 IDD (mA) 40 30 20 Max. 10 Typ. 2 3 4 5 VDD (V) 6 Ta=–40 to +85°C, no load Figure 2. Operating Current Consumption vs. Power Supply Voltage 14/23 ¡ Semiconductor MSM65514/65P514 AC Characteristics • External memory control (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter Clock Period Symbol Condition tC Max. 100 — 45 — "L" Clock Pulse Width tCLW "H" Clock Pulse Width tCHW 45 — tC 200 — 90 — Clock Period VDD=4.5 to 5.5V Min. "L" Clock Pulse Width tCLW "H" Clock Pulse Width tCHW 90 — ALE Pulse Width tAW tC+tCHW–20 — ALE Pulse Delay Time 1 tALD1 tCLW–20 — ALE Pulse Delay Time 2 tALD2 tCLW–20 — RD Pulse Width tRW tC+tCHW–20 — RD Pulse Delay Time tRD tCLW–40 tCLW+20 WR Pulse Width tWW tC+tCHW–40 — WR Pulse Delay Time tWD tCLW–20 tCLW+40 "L" Address Setup Time tLAS tC–40 — "H" Address Setup Time tHAS tC–40 — "L" Address Hold Time tLAH tCLW–20 — Bus Float Time tLAZ — 20 "H" Address Hold Time tHAHR tC–20 — "H" Address Hold Time tHAHW tC–20 — Read Data Access Time tRDAA — tC+tCLW–15 Read Data Access Time tRDAR — tCHW+10 Read Data Hold Time tRDH 0 — Write Data Setup Time tWDS tC+tCLH–40 — Write Data Hold Time tWDH tCLW–20 — VDD=2.7 to 5.5V CL=100pF Unit ns 15/23 ¡ Semiconductor MSM65514/65P514 tCHW tC OSC0 tCLW tAW ALE tRD tRW tALD1 RD tRDAR tLAS P0 tLAH tRDH tLAZ INST or DATA IN ADDRESS L tRDAA tHAS tHAHR P1 ADDRESS H tWD tWW tALD2 tWDS tWDH WR P0 ADDRESS L DATA OUT tHAHW P1 ADDRESS H 16/23 ¡ Semiconductor MSM65514/65P514 • CPU control (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter RESET Pulse Width *1 RESET Pulse Width *2 Symbol Condition tRESW1 tRESW2 Min. Max. Unit — 20 — ns — *3 — — *1 Excluding power ON, stop mode and hard stop mode. *2 In power ON, stop mode and hard stop mode. *3 Oscillation stabilization time depends on resonator. RESET pulse width tRESW1, 2 RESET • Peripheral control 1 (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter tC Condition Min. Max. V DD=4.5 to 5.5V 100 — V DD=2.7 to 5.5V 200 — OSC Clock Period EXI External Interrupt Pulse Width tEXIW 4 tC — External Clock Pulse Width tT0CW 4 tC — GATE Pulse Width tT0GW 1 tTOCLK * — External Clock Pulse Width tT2CW 4 tC — CAP Pulse Width tCAPW 12 tC — T0 T2 CAP * Symbol — Unit ns tT0CLK : Timer 0 count clock period selected by T0CON. 17/23 ¡ Semiconductor MSM65514/65P514 tC OSC0 tCLW 1) EXI pulse width tEXIW INT0-2 2) T0 tT0CW T0CK tT0GW GATE 3) T2 tT2CW T2CK 4) CAP tCAPW CAP 18/23 ¡ Semiconductor MSM65514/65P514 • Peripheral control 2 (VDD=2.7 to 5.5V, GND=0V, Ta=–40 to +85°C) Parameter OSC Min. Max. VDD=4.5 to 5.5V 100 — VDD=2.7 to 5.5V 200 — tSFC 8 tC — SFTCK "L" Pulse Width tSFCLW 4 tC–20 — SFTCK "H" Pulse Width tSFCHW 4 tC–20 — SFTCK Setup Time tSFOS tSFCLW–100 — SFTO Hold Time tSFOH tSFCHW–100 — SFTI Setup Time tSFIS 100 — SFTI Hold Time tSFIH 100 — Clock Period SFTCK Period SFT Synchronous Clock Period Symbol tC Condition CL=100pF tSIC 8 tC — tSICLW 4 tC–20 — tSICHW 4 tC–20 — tSIOS 6 tC–100 — tSIOH 2 tC–100 — Input Data Setup Time tSIIS tC+tCLW+100 — Input Data Hold Time tSIIH 0 — Synchronous Clock "L" Pulse Width SIO (Clock Synchronous Clock "H" Synchro- Pulse Width nous Output Data Setup Time Mode) Output Data Hold Time Unit ns See TIMING DIAGRAM. 19/23 ¡ Semiconductor MSM65514/65P514 1) SFT tSFC tSFCLW tSFCHW tSFOS tSFOH tSFIS tSFIH SFTCK SFTO SFTI 2) SIO (Clock synchronous mode) tSIC tSICLW tSICHW tSIOS tSIOH tSIIS tSIIH TXD RXD (transmission) RXD (reception) 20/23 ¡ Semiconductor MSM65514/65P514 PACKAGE DIMENSIONS (Unit : mm) SDIP64-P-750-1.78 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 8.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 21/23 ¡ Semiconductor MSM65514/65P514 (Unit : mm) QFP64-P-1414-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 22/23 ¡ Semiconductor MSM65514/65P514 (Unit : mm) QFJ68-P-S950-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 4.50 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 23/23