MSTM-S3-T2F1 Stratum 3 Timing Module 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Bulletin Page Revision Date Issued By Application Features The Connor-Winfield MSTM-S3-T2F1 Simplified Control Timing Module acts as a complete system clock module for Stratum 3 timing applications in accordance with GR1244, Issue 2 and GR-253, Issue 3. Connor Winfield’s Stratum 3 timing modules helps reduce the cost of your design by minimizing your development time and maximizing your control of the system clock with our simplified design. • 5V Miniature Timing Module • Redundant 19.44 MHz References • 40 sec., Filtered, Hold Over History • Operational Status Flags TM030 1 of 16 Advance A00 03 October 01 MBatts © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice General Description The Connor-Winfield Stratum 3 Miniature Simplified Control Timing Module acts as a complete system clock module for general Stratum 3 timing applications. The MSTM is designed for external control functions. Full external control input allows for selections and monitoring of any of four possible operating states: 1) Holdover, 2) External Reference #1, 3) External Reference #2, and 4) Free Run. The Table 5 (pg. 4) illustrates the control signal inputs and corresponding operational states: In the absence of External Control Inputs (A,B), the MSTM enters the Free Run mode and signals an External Alarm. The MSTM will enter other operating modes upon application of a proper control signal. Mode 1 operation (A=1, B=0) results in an output signal that is phase locked to the External Reference Input #1. Mode 2 operation (A=0, B=1) results in an output signal that is phase locked to External Reference Input #2. Holdover mode operation (A=1, B=1) results in an output signal at or near the frequency as determined by the latest (last) locked-signal input values and the holdover performance of the MSTM. The primary feature of this model is the Reference Frequency Detector (RFD). This is an independent circuit that monitors both reference inputs simultaneously to determine that a signal is present and its frequency is within a valid range. A logical one on the outputs VALID_R1 and VALID_R2 indicates that the signals applied to EX_REF1 and EX_REF2 respectively have been detected and have a frequency that is within at least +/- 4.6 ppm of nominal. A range of +/-4.6 ppm is guaranteed for the life of the module. The actual range is somewhat more than twice that to account for normal drift and aging that will occur. When, for example, the reference applied to EX_REF1 disappears, VALID_R1 will go to a logical zero within 500 microseconds. When the signal returns at a frequency within +/ - 4.6 ppm of nominal the VALID_R1 output will return to a logical one after a 4-second delay. The delay is a validation period that requires the output of the frequency detector to remain stable for 4 seconds before confirming the status of the reference applied. This eliminates the incessant toggling of the frequency detector that occurs when the reference frequency is at the threshold frequency of the detector The function of the RFD is not related to the operational alarms, LOL and TVL, which monitor the operation of the PLL relative to the selected active reference. In fact the operational alarms function only at the extreme edge of the PLL operating range. This means that it is quite possible for the active reference to drift out of range of the Reference Frequency Detector and still remain well within the capture range of the PLL and not activate the operational alarms. If the other reference was still marked valid by the RFD it might make sense to switch to the better reference before the selected reference drifts completely out of range. Alarm signals are generated at the Alarm Output during Holdover and Free Run operation. Alarm Signals are also generated by loss-of-lock, loss of Reference, and by a Tune-Limit indication from the PLL. A Tune-Limit alarm signal indicates that the OCXO tuning voltage is approaching within 10% the limits of its lock capability and that the External Reference Input may be erroneous. A high level indicates an alarm condition. Real-time indication of the operational mode is available from outputs S0 and S1, which are determined from internal mode registers. Control loop filters effectively attenuate any reference jitter and smooth out phase transients. Functional Block Diagram Figure 1 Control Select Alarm Select CNTL A 0 S0 CNTL B 1 S1 Lock and Detection A0 PLL TVL A1 EX REF 1 EX REF 2 3:1 MUX Phase Comparator ÷N Internal Free Run DAC Filter Source Selector Tuning Voltage Monitor DAC Stratum 3 OCXO SYNC_OUT Filter/ FIFO TCXO CLK_OUT Holdover Circuit ÷N R2-CHK EX REF 2 EX REF 1 R1-CHK Advance Data Sheet #: TM030 VALID_R2 VALID_R1 Page 2 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Absolute Maximum Rating Table 1 Symbol Parameter Minimum Maximum Units Notes VCC Power Supply Voltage -0.5 Nominal 7.0 Volts 1.0 VI Input Voltage -0.5 VCC + 0.5 Volts 1.0 Ts Storage Temperature -55 100 deg. C 1.0 Notes Recommended Operating Conditions Table 2 Symbol Parameter Minimum Nominal Maximum Units Vcc Power supply voltage 4.75 5.00 5.25 Volts VIH High level input voltage - TTL 2.0 VCC Volts VIL Low level input voltage - TTL 0 0.8 Volts tIN Input signal transition - TTL 250 ns CIN Input capacitance 15 pF VOH High level output voltage, IOH = -4.0mA, VCC = min. 5.25 Volts VOL Low level output voltage, IOL = 12.0 mA, VCC = min. 0.4 Volts tTRANS Clock out transition time tPULSE 8kHz input reference pulse width( positive or negative) 30 TOP Operating temperature 0 2.4 4.0 2.0 ns ns 70 °C Specifications Table 3 Parameter Specifications Synchronized Output Frequency (SYNC_OUT) 19.44 MHz Notes Non-synchronized Output Frequency (CLK_OUT) 19.44 MHz Input Reference Frequency Dual 19.44 MHz references Supply Current 250 mA typical, 400 mA during warm-up (Maximum) Jitter, Wander and Phase Transient Tolerances GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 Wander Generation GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 Wander Transfer GR-1244-CORE 5.4 Jitter Generation GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 Jitter Transfer GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 Phase Transients GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 Free Run Accuracy 4.6 ppm over TOP Hold Over Stability ±0.37 ppm for initial 24 hrs Inital Offset 3.0 4.0 ±0.05 ppm Temperature ±0.28 ppm Drift ±0.04 ppm Maximum Hold Over History 40 seconds Pull-in/ Hold-in Range ±4.6 ppm minimum Lock Time <100 sec. PLL_TVL Alarm Limit Extreme 10% ranges of Pull-in/Hold-in Range Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. 5.0 Page 3 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Pin Description Table 4 Pin # Connection Description 1 S0 Condition state output bit 0 2 S1 Condition state output bit 1 3 VALID_R1 Reference #1 validation 4 VALID_R2 Reference #2 validation 5 GND Ground 6 A0 Alarm bit 0 7 CNTL A Mode control input 8 CNTL B Mode control input 9 A1 Alarm bit 1 10 GND Ground 11 SYNC_OUT Primary timing output signal. Signal is sychronized to reference. 12 GND Ground 13 CLK_OUT Stratum 3 TCXO output (non-sychronized 19.44 MHz, ±4.6 output) 14 GND Ground 15 EX_REF_2 External 19.44 MHz Input Reference #2 16 GND Ground 17 EX_REF_1 External 19.44 MHz Input Reference #1 18 VCC +5V DC supply Function Control Table Table 5 Control Inputs A B 0 0 Operational Mode Free Run (Default Mode) Alarm Outputs Condition State Output A0 A1 S0 0 0 0 S1 0 1 0 External Reference #1 Normal Tune Limit LOR LOL (>17 ppm) 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 1 External Reference #2 Normal Tune Limit LOR LOL (>17 ppm) 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 Hold Over NOTES: 1.0: Stresses beyond those listed under Absolute Maximum Rating may cause damage to the device. Operation beyond Recommended Conditions is not implied. 2.0: Logic is 3.3V CMOS 3.0: GR-1244-CORE 3.2.1 4.0: 5.0: Hold Over stability is the cumulative fractional frequency offset as described by GR-1244-CORE, 5.2 Pull-in Range is the maximum frequency deviation from nominal clock rate on the reference inputs to the timing module that can be overcome to pull into synchronization with the reference Advance Data Sheet #: TM030 Page 4 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Qualification Outputs Table 6 Condition Valid_R1 Valid_R2 Ref 1 is within ±4.6 ppm 1 X Ref 1 > ±4.6 ppm 0 X Ref 1 (No Signal) 0 X Ref 2 is within ±4.6 ppm X 1 Ref 2 > ±4.6 ppm X 0 Ref 2 (No Signal) X 0 Valid Reference Thresholds Table 7 Minimum Nominal Maximum VALID_R1 ±4.6 ppm ±9.2 ppm ±13.8 ppm VALID_R2 ±4.6 ppm ±9.2 ppm ±13.8 ppm Frequency Detector Range Over Lifetime Table 8 Detector Frequency Offset VALID_R1/R2 Range 0 ppm ±9.2 ppm +4.6 ppm +13.8 ppm -4.6 ppm -4.6 ppm +4.6 ppm -13.8 ppm Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 5 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Typical Application Figure 2 BITS System Signal Input Select Line Card #1 Timing Card #1 A B MUX C CW’s SCG 2500/4500 Y Clock out CW’s STM/MSTM module S RCV Line Card #N Timing Card #2 A B C CW’s SCG 2500/4500 Y MUX Clock out CW’s STM/MSTM module RCV S System Select Typical System Test Set-up Figure 3 G P S or LO R AN T i m in g S o u r c e T h is d e v ic e s u p p lie s s y s t e m t im e in fo rm a tio n . I t c a n b e t h o u g h t o f a s s u p p ly in g " a b s o lu t e tim e " r e f e r e n c e in fo rm a tio n S a m p l e M T IE D a t a f o r S T M - S 3 / M S T M - S 3 1 .0 E - 6 P o s s i b le C h o ic e s I n c lu d e S ta n fo rd R e s e a r c h M o d e l: F S 7 0 0 T r u e tim e M o d e l X X X T yp i c al r e s p o n s e - 3 0 0 0 s e c o n d te s t - J it t e r a p p lie d ( 2 U I @ re f d a t e A P R 1 0 H z) 2 2 1 9 9 8 k dh M T IE (s 1 0 0 .0 E - 9 10 MHz M T IE 1 0 .0 E - 9 1 2 4 4 - 5 .2 M a s k ( A ) 1 2 4 4 - 5 .2 M a s k ( B ) 1 2 4 4 - 5 .6 M a s k G R 2 5 3 - 5 .4 . 4 .3 . 2 1 .0 E - 9 1 0 0 .0 E - 3 1 .0 E +0 1 0.0E +0 1 0 0 .0 E + 0 O b s e r v a t i o n T im e ( s ) 1.0 E +3 C o p y ri g ht 1 0 .0 E + 3 1 9 9 8 C o n n o r - W in f ie ld a l l r ig h ts r e s e r v e d T a r g e t S y s te m U n d e r T e s t C l o c k o r B IT S l o g i c l e v e l c lo c k in p u t (T T L , C M O S , e tc .) A r b i tr a r y W a v e fo rm G e n e ra to r [N o i s e S o u rc e ] S a m p le W a n d e r G e n e r a tio n (T D E V ) f o r S T M / M S T M - S 3 1 .0 E - 6 T yp i c a l r e s p o n s e - 3 0 0 0 s e c o n d te s t - J it t e r a p pl ie d ( 2 U I @ r e f da t e A P R 2 2 1 9 9 8 10 H z ) k dh 1 0 0 .0 E - 9 1 0 .0 E - 9 T D E V ( se c DS-1 Line Card OC-48 Line Card OC-3 Line Card . . . . . .. OC-12 Line Card M T IE , T D E V , W a n d e r T r a n s fe r , a n d W a n d e r G e n e r a t io n P l o t s Line Card Noise Modulation Input 10 MHz E x te r n a l R e fe re n ce In p u t S ta n d a r d s C o m p lia n c e D o c u m e n ts D S 1 ra te R Z ( 1 . 5 4 4 M H z ) , E 1 ra te R Z o r 8 k H z c lo c k R Z w it h n o is e m o d u la t io n Timing Card A r b i tr a r y W a v e fo rm G e n e ra to r Timing Card E x te r n a l R e fe re n ce In p u t TDEV G R 1 2 4 4 - F ig 5 . 1 1 .0 E - 9 G R 1 2 4 4 - F ig 5 - 3 1 0 0 .0 E - 1 2 1 0 .0 E - 3 1 0 0 .0 E - 3 1 .0 E + 0 In te g r a t io n 1 0 .0 E +0 T im e (s e c ) 1 0 0 .0 E + 0 1 .0 E + 3 C o p y r i gh t 1 9 9 8 C o n n o r -W in f ie ld a ll l r ig h ts r e s e r v e d T im e - s t a m p e d e n s e m b le b a s e d o n a b s o lu t e tim e re fe re n c e ( 1 0 M H z in p u t ) 10 MHz D S 1 r a t e [ 1 . 5 4 4 M H z ] B IT S B ip o la r P h a s e E r ro r d a t a o u tp u t D S - 1 , O C - 3 , O C - 1 2 e le c tr ic a l o r o p t ic a l s ig n a ls 10 MHz T e k t ro n ix S J300E E x te r n a l R e fe re n c e In p u t HP 53310A M o d u la t io n A n a ly z e r / T im e I n t e r v a l A n a ly z e r W a n d e r A n a ly z e r d a ta ( I E E E - 4 8 8 ) E x te r n a l R e fe re n ce In p u t I E E E - 4 8 8 C o n tr o lle r P la t fo r m f o r s o f tw a r e H P 5 3 3 0 5 A P h a s e A n a ly z e r H P E 1748A Sync M e a s u re m e n t T e k t ro n ix W a n d e r A n a ly z e r T E K T R O N IX S J 3 0 0 E Advance Data Sheet #: TM030 Page 6 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice MSTM-S3-T2F1 Typical Current Draw Figure 4 0.45 0.4 CURRENT (A) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 10 20 30 40 50 60 TIME (Sec) Typical Calibrated Wander Transfer TDEV Figure 5 10000 100 TDEV (ns) 10 GR1244, Fig 5.3 10000 1000 100 10 1 0.1 1 0.01 TDEV (ns) 1000 Integration Time (Sec.) Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 7 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Typical Wander Generation MTIE Figure 6 1000 G R 1 2 4 4 , F ig 5 .2 (A ) G R 1 2 4 4 , F ig 5 .2 (B ) G R 2 5 3 -5 .4 .4 .3 .2 , F ig 5 .1 7 MTIE (ns) M T IE (n s ) 100 1000000 100000 10000 1000 100 10 1 0.1 10 O b s e r v a tio n T im e (s e c .) Typical Wander Generation TDEV Figure 7 100 T D E V (n s) G R 1 24 4, F ig 5 .1 TDEV (ns) 10 1 10000 1000 100 10 1 0.1 0 .1 In te g ra tio n T im e (s e c .) Advance Data Sheet #: TM030 Page 8 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice 1µ µ s Phase Transient TIE Figure 8 1200 1000 TIE (ns) 800 600 400 200 0 -200 0 1 2 3 4 5 6 7 8 9 10 Time (sec) 1µ µ s Phase Transient MTIE Figure 9 10000 MTIE (ns) 1000 G R -2 5 3 , F i g . 5 -1 9 M T I E (n s) 100 10 1 0 .0 1 0 .1 1 10 100 1000 O b s e rv a tio n T im e (s e c ) Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 9 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Entry Into Hold Over Figure 10 10000 MTIE (ns) 1000 100 10 G R -1 2 4 4 O b je c t ive , F ig . 5 -8 G R -1 2 4 4 R e q u ire m e n t , F ig . 5 -8 Ty p ic a l M TIE 1 0.001 0.01 0.1 1 10 100 O b se r v a ti o n T i m e (se c o n d s) Return from Hold Over Figure 11 10000 MTIE (ns) 1000 100 10 G R -1 2 4 4 R e q u ire m e n t , F ig . 5 -7 M TIE (n s ) Ty p ic a l M TIE 1 0.001 0.01 0 .1 1 10 100 O b se rv a ti o n T i m e (se c . ) Advance Data Sheet #: TM030 Page 10 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice MSTM-S3-T2F1 Mode Indicator Delay Figure 12 Change in Operational Mode Operational Mode Indicator ∆tm 2 msec <∆tm < 4.125 msec Loss of Reference Timing Diagram Figure 13 External Reference Input Alarm tAon tAoff 2 msec < tAon < 6.125 msec 0 msec < tAoff < 2.125 msec Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 11 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice Tuning Voltage Limit Alarm Timing Diagram Figure 14 TVL LimitHigh Frequency Sync_Out (NominalFrequency) TVL LimitLow Frequency TVL Alarm & AlarmOut ∆t 0< ∆t<2.125msec *The DAC is updated only when the output changes level. The maximum update rate is 8kHz Valid Reference Qualification Timing Diagram Figure 15 Reference Frequency Valid Upper Limit EX_REF 1 or EX_REF 2 No Reference Available (Nominal Frequency) Reference Frequency Valid Lower Limit Valid_R1 or Valid_R2 4 sec Delay Advance Data Sheet #: TM030 Page 12 of 16 375 usec - 500 usec Delay on LOR Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Clearance Figure 16 .020" MAX. .020" .030" PIN LAND ALL SOLDER AND/OR WIRE TAGS SHALL NOT EXTEND MORE THAN .020" BELOW PC BOARD BOTTOM SURFACE Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 13 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice MECHANICAL OUTLINE: GROUND AND POWER SUPPLY LINES: The mechanical outline of the MSTM-S3-T2F1 is shown in Figure 17. The board space required is 2” x 2”. The pins are .040” in diameter and are .150” in length. The unit is spaced off the PCB by .030” shoulders on the pins. Due to the height of the device it is recommended to have heat sensitive devices away where the air flow might not be blocked. Power specifications will vary depending primarily on the temperature range. At wider temperature ranges starting at 0 to 70 deg. C., an ovenized oscillator, OCXO, will be incorporated. The turn-on current for an OCXO requires a peak current of about .4A for about a minute. The steady state current will the vary from 50-150 mA depending on the temperature. It is suggested to plan for the peak current in the power and ground traces pin 18 and pin 5. The other four ground pins 10, 12, 14, and 16 are intended for signal grounds. PAD ARRAY AND PAD SPACING: The pins are arranged in a dual-in-line configuration as shown in Figure 16. There is .2” space between the pins in-line and each line is separated by 1.6”. See Figures 17 & 18 and Table 6. PAD CONSTRUCTION: The recommended pad construction is shown in Figure 18. For the pin diameter of .040” a hole diameter of .055” is suggested for ease of insertion and rework. A pad diameter of .150” is also suggested for support. This leaves a spacing of .050” between the pads which is sufficient for most signal lines to pass through. SOLDER MASK: A solder mask is recommended to cover most the top pad to avoid excessive solder underneath the shoulder of the pin to avoid rework damage. See Table 6 and Figure 19. VIA KEEP OUT AREA: It is recommended that there be no vias or feed throughs underneath the main body of the module between the pins. It is suggested that the traces in this area be kept to a minimum and protected by a layer of solder mask. See Figure 18. POWER SUPPLY REGULATION: Good power supply regulation is recommended for the MSTM-S3-T2F1 The internal oscillators are regulated to operate from 4.75 - 5.25 volts. Large jumps within this range may still produce varying degrees of wander. If the host system is subject to large voltage jumps due to hot-swapping and the like, it is suggested that there be some form of external regulation such as a DC/DC converter. SOLDERING RECOMMENDATIONS: Due to the sensitive nature of this part, hand soldering or wave soldering of the pins is recommended after reflow processes. WASHING RECOMMENDATIONS: The MSTM-S3-T2F1 is not in a hermetic enclosure. It is recommended that the leads be hand cleaned after soldering. Do not completely immerse the module. MODULE BAKEOUT: Do not bakeout the MSTM-S3-T2F1 Advance Data Sheet #: TM030 Page 14 of 16 Rev: A00 Date: 10 / 03 / 01 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Package Dimensions Characteristic Measurements Figure 17 Table 9 Characteristic Item Measurement (inches) Pad to Pad Spacing 0.200 Solder pad top O.D. 0.150 Solder pad top I.D. 0.055 Solder pad bottom O.D. 0.150 Solder pad bottom I.D. 0.055 Solder mask top dia. 0.070 Solder mask bottom dia. 0.155 Pin row to row spacing 1.600 Recommended Footprint Dimensions Side Assembly View Figure 18 Figure 19 TOP SIDE SOLDER RESIST (OVER PAD) PCB SIDE VIEW BOTTOM SIDE SOLDER RESIST (UP TO PAD) Advance Data Sheet #: TM030 © Copyright 2001 The Connor-Winfield Corp. Page 15 of 16 Rev: A00 Date: 10 / 03 / 01 All Rights Reserved Specifications subject to change without notice 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Revision Revision Date Note A00 10/03/01 Advance Info Data Sheet