MAXIM MX7824KN

19-0255; Rev 2; 4/94
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
High-Speed Servo Control
Audio Instrumentation
____________________________Features
♦ One-Chip Data Acquisition System
♦ Four or Eight Analog Input Channels
♦ 2.5µs per Channel Conversion Time
♦ Internal 2.5V Reference (MAX154/MAX158 only)
♦ Built-In Track/Hold Function
♦ 1/2LSB Error Specification
♦ Single +5V Supply Operation
♦ No External Clock
♦ New Space-Saving SSOP Package
______________Ordering Information
TEMP. RANGE
PART
PIN-PACKAGE
ERROR
(LSB)
MX7824LN
0°C to +70°C
24 Narrow
Plastic DIP
±1/2
MX7824KN
0°C to +70°C
24 Narrow
Plastic DIP
±1
MX7824LCWG
0°C to +70°C
24 Wide SO
±1/2
MX7824KCWG
0°C to +70°C
24 Wide SO
MX7824LCAG
0°C to +70°C
24 SSOP
MX7824KCAG
0°C to +70°C
24 SSOP
Ordering Information continued on last page.
±1
±1/2
±1
__________________________________________________________Pin Configurations
TOP VIEW
AIN4 1
24 VDD
AIN3 2
23 NC
AIN2 3
22 A0
AIN1 4
TP (REF OUT) 5
21 A1
MAX154
MX7824
20 DB7
AIN6 1
28 AIN7
AIN5 2
27 AIN8
AIN4 3
26 VDD
AIN3 4
25 A0
AIN2 5
AIN1 6
MAX158
MX7828
24 A1
23 A2
19 DB6
TP (REF OUT) 7
22 DB7
18 DB5
DB0 8
21 DB6
DB2 8
17 DB4
DB1 9
20 DB5
DB3 9
16 CS
DB2 10
19 DB4
RD 10
15 RDY
DB3 11
18 CS
INT 11
14 VREF+
RD 12
17 RDY
13 VREF-
INT 13
16 VREF+
GND 14
15 VREF-
DB0 6
DB1 7
GND 12
DIP/SO/SSOP
DIP/SO/SSOP
( ) ARE FOR MAX154/MAX158 ONLY.
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
1
MX7824/MX7828
_______________General Description
The MAX154/MAX158 and MX7824/MX7828 are highspeed, multi-channel analog-to-digital converters
(ADCs). The MAX154 and MX7824 have four analog
input channels, while the MAX158 and MX7828 have
eight channels. Conversion time for all devices is 2.5µs.
The MAX154/MAX158 also feature a 2.5V on-chip reference, forming a complete high-speed data acquisition
system.
All four converters include a built-in track/hold, eliminating the need for an external track/hold with many input
signals. The analog input range is 0V to +5V, although
the ADC operates from a single +5V supply.
Microprocessor interfaces are simplified by the ADC’s
ability to appear as a memory location or I/O port without
the need for external logic. The data outputs use latched,
three-state buffer circuitry to allow direct connection to a
microprocessor data bus or system input port.
The MX7824 and MX7828 are pin compatible with
Analog Devices’ AD7824 and AD7828. The MAX154
and MAX158, which feature internal references, are also
compatible with these products.
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to GND ........................................0V, +10V
Voltage at Any Other Pins......................GND - 0.3V, VDD + 0.3V
Output Current (REF OUT)..................................................30mA
Power Dissipation (any package) to +75°C ....................450mW
Derate above +25°C by ..............................................6mW/°C
Operating Temperature Ranges
MX7824, MX7828
KN/LN/KCW_/LCW_ ............................................0°C to +70°C
BQ/CQ .............................................................-40°C to +85°C
TQ/UQ............................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
8
Bits
MAX15_A, MX782_L/C/U
MAX15_B, MX782_K/B/T
Total Unadjusted Error (Note 1)
No Missing Codes Resolution
±1/2
±1
LSB
±1/4
LSB
8
Bits
Channel to Channel Mismatch
REFERENCE INPUT
Reference Resistance
1
4
kΩ
VREF+ Input Voltage Range
VREF-
VDD
V
VREF- Input Voltage Range
GND
VREF+
V
REFERENCE OUTPUT—MAX154/MAX158 Only (Note 2)
Output Voltage
2.50
2.53
V
Load Regulation
REF OUT
IL = 0mA to 10mA, TA = +25°C
-6
-10
mV
Power-Supply Sensitivity
VDD ±5%, TA = +25°C
±1
±3
mV
MAX15_C
40
70
MAX15_E
40
70
MAX15_M
60
100
Temperature Drift (Note 3)
Output Noise
TA = +25°C
2.47
eN
200
Capacitive Load
ppm/°C
µV/rms
0.01
µF
ANALOG INPUT
Analog Input Voltage Range
AINR
Analog Input Capacitance
CAIN
Analog Input Current
IAIN
VREF-
VREF+
45
Any channel, AIN = 0V to 5V
Slew Rate, Tracking
SR
–—– –—–
LOGIC INPUTS ( RD , CS , A0, A1, A2)
0.7
V
pF
±3
µA
0.157
V/µs
Input High Voltage
VINH
Input Low Voltage
VINL
0.8
V
Input High Current
IINH
1
µA
Input Low Current
IINL
-1
µA
Input Capacitance (Note 4)
CIN
8
pF
2
2.4
V
5
_______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
MX7824/MX7828
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
VOH
—
–—–
DB0–DB7, INT; IOUT = -360µA
4.0
VOL
—
–—–
DB0–DB7, INT; RDY
TYP
MAX
UNITS
LOGIC OUTPUTS
Output High Voltage
Output Low Voltage
Three-State Output Current
Output Capacitance (Note 4)
V
IOUT = 1.6mA
0.4
IOUT = 2.6mA
0.4
DB0–DB7, RDY; VOUT = 0V to VDD
COUT
5
V
±3
µA
8
pF
POWER SUPPLY
Supply Voltage
VDD
Supply Current
IDD
5V ±5% for specified performance
–—– –—–
CS = RD = 2.4V
PSS
VDD = ±5%
4.75
Power Dissipation
Power-Supply Sensitivity
Note 1:
Note 2:
Note 3:
Note 4:
5.25
V
15
mA
25
75
mW
±1/16
±1/4
LSB
Total unadjusted error includes offset, full-scale, and linearity errors.
Specified with no external load unless otherwise noted.
Temperature drift is defined as change in output voltage from +25°C to TMIN or TMAX divided by (25 - TMIN) or (TMAX - 25).
Guaranteed by design.
TIMING CHARACTERISTICS (Note 5)
(VDD = +5V, VREF+ = +5V, VREF- = GND, Mode 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
TA = +25°C
CONDITIONS
MIN
–—– –—–
CS to RD Setup Time
–—– –—–
CS to RD Hold Time
Multiplexer Address
Setup Time
Multiplexer Address
Hold Time
–—–
CS to RDY Delay
Conversion Time (Mode 0)
–—–
Data Access Time After RD
Data Access Time
—
–—–
After INT, Mode 0
–—– —
–—–
RD to INT Delay (Mode 1)
Data Hold Time
Delay Time
Between Conversions
–—–
RD Pulse Width (Mode 1)
TYP
MAX
MAX15_ _C/E
MX782_K/L/B/C
MIN
MAX
MAX15_ _M
MX782_T/U
MIN
UNITS
MAX
tCSS
0
0
0
ns
tCSH
0
0
0
ns
tAS
0
0
0
ns
30
tAH
40
ns
40
2.0
85
60
2.4
110
60
2.8
120
ns
µs
ns
(Note 6)
20
50
60
70
ns
CL = 50pF
40
75
100
100
ns
60
70
70
ns
CL = 50pF, RL = 5kΩ
tACC2
tINTH
tDH
35
30
1.6
tRDY
tCRD
tACC1
(Note 6)
(Note 7)
tP
500
tRD
60
500
600
80
600
500
80
ns
400
ns
Note 5: All input control signals are specified with tR = tF = 20ns (10% to 90% of +5V) and timed from a 1.6V voltage level.
Note 6: Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
_______________________________________________________________________________________
3
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
OUTPUT CURRENT
vs. TEMPERATURE
VDD = 5V
2.500
2.490
LINEARITY ERROR (LSB)
16
OUTPUT CURRENT (mA)
2.510
2.0
MX7824/28-2
20
MX7824/28-1
2.520
ACCURACY vs. DELAY BETWEEN
CONVERSIONS (tp)
ISOURCE VOUT = 2.4V
12
8
ISINK VOUT = 0.4V
4
0
50
-100
150
100
0.5
-50
0
50
300
150
100
400
500
ACCURACY vs. VREF
(VREF = VREF+ - VREF-)
600
700
8
IDD – SUPPLY CURRENT (mA)
MX7824/28-4
VDD = 5V
1.5
1.0
0.5
0
7
VDD = 5.25V
6
5
VDD = 5V
4
VDD = 4.75V
3
2
0
1
2
3
4
5
-100
VREF (V)
-50
0
50
100
150
AMBIENT TEMPERATURE (°C)
+5V
+5V
3k
DBN
DBN
100pF
100pF
DGND
DGND
b. High-Z to VOL
Figure 1. Load Circuits for Data-Access Time Test
4
3k
DBN
DBN
a. High-Z to VOH
900
POWER-SUPPLY CURRENT vs. TEMPERATURE
(NOT INCLUDING REFERENCE LADDER)
2.0
3k
800
tp (ns)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
LINEARITY ERROR (LSB)
1.0
MX7824/28-5
-50
VDD = 5V
VREF = 5V
1.5
0
0
2.480
MX7824/28-3
REFERENCE TEMPERATURE
DRIFT (MAX154/MAX158 ONLY)
REF OUT VOLTAGE (V)
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
3k
10pF
10pF
DGND
a. VOH to High-Z
DGND
b. VOL to High-Z
Figure 2. Load Circuits for Data-Hold Time Test
_______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
PIN
PIN
NAME
FUNCTION
MAX154
MX7824
NAME
FUNCTION
MAX158
MX7828
1
AIN4
Analog Input Channel 4
1
AIN6
Analog Input Channel 6
2
AIN3
Analog Input Channel 3
2
AIN5
Analog Input Channel 5
3
AIN2
Analog Input Channel 2
3
AIN4
Analog Input Channel 4
4
AIN1
Analog Input Channel 1
4
AIN3
Analog Input Channel 3
5
REF OUT
TP
Reference Output (2.5V) for MAX154.
Test point for MX7824. Do not connect.
5
AIN2
Analog Input Channel 2
6
AIN1
Analog Input Channel 1
6
DBO
Three-State Data Output, bit 0 (LSB)
7
DB1
Three-State Data Output, bit 1
7
REF OUT
TP
8
DB2
Three-State Data Output, bit 2
8
DB0
Three-State Data Output, bit 0 (LSB)
9
DB3
Three-State Data Output, bit 3
–—–
Read Input. RD controls conversions
and data access. See Digital Interface
section.
Interrupt Output. INT going low indicates the completion of a conversion.
See Digital Interface section.
9
DB1
Three-State Data Output, bit 1
10
DB2
Three-State Data Output, bit 2
11
DB3
12
–—–
RD
Three-State Data Output, bit 3
–—–
Read Input. RD controls conversions
and data access. See Digital Interface
section.
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
13
INT
Interrupt Output. INT going low indicates the completion of a conversion.
See Digital Interface section.
14
GND
15
VREF-
Ready Output. Open-drain output with
no active pull-up device. Goes low
–—–
when CS goes low and high impedance at the end of a conversion.
–—–
Chip-Select Input. CS must be low for
the device to be selected.
16
VREF+
17
RDY
18
–—–
CS
10
–—–
RD
11
INT
12
GND
13
VREF-
14
VREF+
15
RDY
Reference Output (2.5V) for MAX158.
Test point for MX7828. Do not connect.
Ground
Lower Limit of Reference Span. Sets
the zero-code voltage.
Range: GND to VREF+.
Upper Limit of Reference Span. Sets
the full-scale input voltage.
Range: VREF- to VDD.
Ready Output. Open-drain output with
no active pull-up device. Goes low
–—–
when CS goes low and high impedance at the end of a conversion.
–—–
Chip-Select Input. CS must be low for
the device to be selected.
16
–—–
CS
17
DB4
Three-State Data Output, bit 4
18
DB5
Three-State Data Output, bit 5
19
DB6
Three-State Data Output, bit 6
19
DB4
Three-State Data Output, bit 4
20
DB7
Three-State Data Output, bit 7 (MSB)
20
DB5
Three-State Data Output, bit 5
21
A1
Channel Address 1 Input
21
DB6
Three-State Data Output, bit 6
22
A0
Channel Address 0 Input
22
DB7
Three-State Data Output, bit 7 (MSB)
23
NC
No Connect
23
A2
Channel Address 2 Input
24
VDD
Power-Supply Voltage, +5V
24
A1
Channel Address 1 Input
25
A0
Channel Address 0 Input
26
VDD
Power-Supply Voltage, +5V
27
AIN8
Analog Input Channel 8
28
AIN7
Analog Input Channel 7
_______________________________________________________________________________________
5
MX7824/MX7828
_____________________________________________________________Pin Descriptions
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_______________Detailed Description
___________________Digital Interface
Converter Operation
The MAX154/MAX158 and MX7824/MX7828 use only
Chip Select (CS) and Read (RD) as control inputs. A
READ operation, taking CS and RD low, latches the multiplexer address inputs and starts a conversion (Table 1).
The MAX154/MAX158 and MX7824/MX7828 use what is
commonly called a “half-flash” conversion technique
(Figure 3). Two 4-bit flash ADC sections are used to
achieve an 8-bit result. Using 15 comparators, the
upper 4-bit MS (most significant) flash ADC compares
the unknown input voltage to the reference ladder and
provides the upper four data bits.
An internal DAC uses the MS bits to generate an analog
signal from the first flash conversion. A residue voltage
representing the difference between the unknown input
and the DAC voltage is then compared to the reference
ladder by 15 LS (least significant) flash comparators to
obtain the lower four output bits.
Table 1. Truth Table for Input Channel
Selection
MAX154/MX7824
A1
A0
0
0
1
1
0
1
0
1
Operating Sequence
The operating sequence is shown in Figure 4. A conversion is initiated by a falling edge of RD and CS. The
comparator inputs track the analog input voltage for
approximately 1µs. After this first cycle, the MS flash
result is latched into the output buffers and the LS conversion begins. INT goes low approximately 600ns
later, indicating the end of the conversion, and that the
lower four bits are latched into the output buffers. The
data can then be accessed using the CS and RD
inputs.
AIN1
REF OUT**
0
0
0
0
0
0
1
1
0
1
0
1
AIN1
AIN2
AIN3
AIN4
1
1
1
1
0
0
1
1
0
1
0
1
AIN5
AIN6
AIN7
AIN8
DB7
DB6
4-BIT
FLASH
ADC
(4MSB)
VREF-
VREF+
16
2.5V
REF
*MAX154/MX7824 – 4-Channel Mux
MAX158/MX7828 – 8-Channel Mux
** REF OUT on MAX154/MAX158 only
DB5
DB4
THREESTATE
DRIVERS
4-BIT
DAC
MUX*
AIN8
A1
A2
DB3
DB2
DB1
4-BIT
FLASH
ADC
(4LSB)
ADDRESS
LATCH
DECODE
A0
DB0
TIMING AND CONTROL
CIRCUITRY
RDY
CS
INT
RD
Figure 3. Functional Diagram
6
SELECTED
CHANNEL
There are two interface modes, which are determined
by the length of the RD input. Mode 0, implemented by
keeping RD low until the conversion ends, is designed
for microprocessors that can be forced into a WAIT
state. In this mode, a conversion is started with a READ
operation (taking CS and RD low), and data is read
when the conversion ends. Mode 1, on the other hand,
VREF+
AIN4
MAX158/MX7828
A2
A1
A0
_______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
500ns
1000ns
SETUP TIME REQUIRED
BY THE INTERNAL
COMPARATORS PRIOR TO
STARTING CONVERSION
600ns
VIN IS SAMPLED
AND THE FOUR MSBs
ARE LATCHED
VIN IS TRACKED
BY INTERNAL
COMPARATORS
There are two status outputs: Interrupt (INT) and Ready
(RDY). RDY, an open-drain output (no internal pull-up
device), is connected to the processor’s READY/WAIT
input. RDY goes low on the falling edge of CS and goes
high impedance at the end of the conversion, when the
conversion result appears on the data outputs. If the RDY
output is not required, its external pull-up resistor can be
omitted. INT goes low when the conversion is complete
and returns high on the rising edge of CS or RD.
Interface Mode 1
Figure 4. Operating Sequence
does not require microprocessor WAIT states. A READ
operation simultaneously initiates a conversion and
reads the previous conversion result.
Interface Mode 0
Figure 5 shows the timing diagram for Mode 0 operation. This is used with microprocessors that have WAIT
state capability, whereby a READ instruction is extended to accommodate slow-memory devices. Taking CS
and RD low latches the analog multiplexer address and
starts a conversion. Data outputs DB0–DB7 remain in
the high-impedance condition until the conversion is
complete.
Mode 1 is designed for applications where the microprocessor is not forced into a WAIT state. Taking CS
and RD low latches the multiplexer address and starts
a conversion (Figure 6). Data from the previous conversion is immediately read from the outputs (DB0–DB7).
INT goes high at the rising edge of CS or RD and goes
low at the end of the conversion. A second READ operation is required to read the result of this conversion.
The second READ latches a new multiplexer address
and starts another conversion. A delay of 2.5µs must
be allowed between READ operations. RDY goes low
on the falling edge of CS and goes high impedance at
the rising edge of CS. If RDY is not needed, its external
pull-up resistor can be omitted.
CS
tCSH
tCSS
tCSS
RD
tP
tAS
tAS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
tAH
RDY
tRDY
INT
tINTH
tCRD
tACC2
HIGH IMPEDANCE
DATA
tDH
DATA
VALID
Figure 5. Mode 0 Timing Diagram
_______________________________________________________________________________________
7
MX7824/MX7828
RD
INT GOING LOW
INDICATES THAT
CONVERSION IS
COMPLETE AND
THAT DATA CAN
BE READ
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
CS
tRD
tCSS
tCSH
tCSS
tCSH
tRD
RD
tP
tAS
tAS
ANALOG
CHANNEL
ADDRESS
ADDR
VALID
ADDR
VALID
tAH
tAH
RDY
tRDY
tRDY
tCRD
tINTH
INT
tACCI
tINTH
tDH
tDH
tACCI
OLD
DATA
DATA
NEW
DATA
Figure 6. Mode 1 Timing Diagram
_____________Analog Considerations
OUTPUT
CODE
Reference and Input
The VREF+ and VREF- inputs of the converter define the
zero and the full-scale of the ADC. In other words, the
voltage at VREF- is equal to the input voltage that produces an output code of all zeros, and the voltage at
VREF+ is equal to input voltage that produces an output
code of all ones (Figure 7).
Figure 8 shows some possible reference configurations. For the MAX154/MAX158, a 0.01µF bypass
capacitor to GND should be used to reduce the highfrequency output impedance of the internal reference.
Larger capacitors should not be used, as this degrades
the stability of the reference buffer. The 2.5V reference
output is with respect to the GND pin.
FULL-SCALE
TRANSITION
11111111
11111110
11111101
1LSB = F8 = VREF+ - VREF256
256
00000011
00000010
VREF+
00000001
Bypassing
A 47µF electrolytic and 0.1µF ceramic capacitor should
be used to bypass the VDD pin to GND. These capacitors must have minimum lead length, since excess lead
length may contribute to conversion errors and instability.
If the reference inputs are driven by long lines, they
should be bypassed to GND with 0.1µF capacitors at
the reference input pins.
8
00000000
VREF-
1
2
3
FS
AIN INPUT VOLTAGE
(IN TERMS OF LSBs)
Figure 7. Transfer Function
_______________________________________________________________________________________
FS–1LSB
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
VIN
AINx(-)
GND
VDD
+5V
REF OUT
0.1µF
47µF
Input Current
MAX154
MAX158
VREF+
0.01µF
VREF-
Figure 8a. Internal Reference (MAX154/MAX158 only)
AINx(+)
VIN
AINx(-)
GND
VDD
+5V
0.1µF
2.5V
47µF
MX584
MX7824
MX7828
VREF+
VREF-
Figure 8b. External Reference +2.5V Full-Scale
AINx(+)
VIN
AINx(-)
GND
Input Filtering
MAX154
MAX158
VREF+ MX7824
MX7828
VDD
+5V
0.1µF
47µF
The converters’ analog inputs behave somewhat differently from conventional ADCs. The sampled data comparators take varying amounts of current from the input,
depending on the cycle they are in. The equivalent circuit of the converter is shown in Figure 9a. When the
conversion starts, AIN(n) is connected to the MS and
LS comparators. Thus, AIN(n) is connected to thirty-one
1pF capacitors.
To acquire the input signal in approximately 1µs, the
input capacitors must charge to the input voltage
through the on-resistance of the multiplexer (about
600Ω) and the comparator’s analog switches (2kΩ to
5kΩ per comparator). In addition, about 12pF of stray
capacitance must be charged. The input can be modeled as an equivalent RC network shown in Figure 9b.
As RS (source impedance) increases, the capacitors
take longer to charge.
Since the length of the input acquisition time is internally set, large source resistances (greater than 100Ω) will
cause settling errors. The output impedance of an opamp is its open-loop output impedance divided by the
loop gain at the frequency of interest. It is important
that the amplifier driving the converter input have sufficient loop gain at approximately 1MHz to maintain low
output impedance.
VREF-
Figure 8c. Power Supply as Reference
The transients in the analog input caused by the sampled data comparators do not degrade the converter’s
performance, since the ADC does not “look” at the
input when these transients occur. The comparator’s
outputs track the input during the first 1µs of the conversion, and are then latched. Therefore, at least 1µs
will be provided to charge the ADC’s input capacitance. It is not necessary to filter these transients with
an external capacitor on the AIN terminals.
Sinusoidal Inputs
* Current path must
still exist from
VIN(-) to Ground
AINx(+)
VIN
GND
VDD
+5V
0.1µF
VREF+
47µF
2.5V
VREF-
AINx(-)
*
MAX154
MAX158
MX7824
MX7828
The MAX154/MAX158 and MX7824/MX7828 can measure input signals with slew rates as high as 157mV/µs
to the rated specifications. This means that the analog
input frequency can be as high as 10kHz without the
aid of an external track/hold. The maximum sampling
rate is limited by the conversion time (typical tCRD =
2µs) plus the time required between conversions (tp =
500ns). It is calculated as:
fMAX =
1
1
=
= 400kHz
tCRD + tp
(2.0 + 0.5) µs
Figure 8d. Inputs Not Referenced to GND
_______________________________________________________________________________________
9
MX7824/MX7828
AINx(+)
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
fMAX permits a maximum sampling rate of 50kHz per
channel when using the MAX158/MX7828 and 100kHz
per channel when using the MAX154/MX7824. These
rates are well above the Nyquist requirement of 20kHz
sampling rate for a 10kHz input bandwidth.
Bipolar Input Operation
The circuit in Figure 10a can be used for bipolar input
operation. The input voltage is scaled by an amplifier so
that only positive voltages appear at the ADC’s inputs.
An external reference should be used for the MX7824/
MX7828, but is not needed with the MAX154/MAX158.
The analog input range is ±4V and the output code is
complementary offset binary. The ideal input/output
characteristic is shown in Figure 10b.
3.57k
11.5Ω
VIN
0.01µF
CS
AIN1
10.0k
MAX154
MAX158
16.2k
RDY
RD
0.01µF
VREF+
INT
REF OUT
+5V
VDD
DB0–DB7
VREF47µF
0.1µF
RS
AIN1
VIN
CS
2pF
RON
RMUX
CS
12pF
GND
ONLY CHANNEL 1 SHOWN
1pF
1pF
•
•
•
15 LSB COMPARATORS
TO LS
LADDER
Figure 10a. Bipolar ±4V Input Operation
RON
1pF
1pF
•
•
•
16 MSB COMPARATORS
TO MS
LADDER
FS = 8V
1LSB = FS / 256
11111111
11111110
11111101
Figure 9a. Equivalent Input Circuit
10000010
10000001
+FS
2
10000000
01111111
RS
VIN
AIN1
B MUX
600Ω
CS1
2pF
01111110
RON
350Ω
CS2
2pF
-FS + 1LSB
2
00000010
00000001
32pF
00000000
0V
AIN INPUT VOLTAGE (LSBs)
Figure 9b. RC Network Model
10
Figure 10b. Transfer Function for ±4V Input Operation
______________________________________________________________________________________
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
ADDRESS BUS
VDD
A0
EN
MREQ
ADDRESS
DECODE
A0
A1
A2*
BANDPASS
FILTER 1
6
BANDPASS
FILTER 2
5 AIN2
AIN1
5V
ZBO
MX7824/MX7828
+5V
26
A15
MAX154
MAX158
RDY MX7824
MX7828
RD
CS
5k
WAIT
RD
18
RD
12
MAX158
MX7828
AMP
DB0–DB7
BANDPASS
FILTER 7
28
A2
BANDPASS
FILTER 8
+5V
DATA
AIN7
DB0–DB7
DATA BUS
D0–D7
SPEECH
INPUT
CS
27 AIN8
16
VREF+
VREF15
A1
A0
23
24
25
GND
14
*A2 ON MAX158/MX7828 ONLY.
Figure 12. Speech Analysis Using Real-Time Filtering
Figure 11. Simple Mode 0 Interface
SAMPLE
PULSE
+5V
24
VDD
16
CS
4 AIN1
3 AIN2
2
1
14
13
12
AIN3
AIN4
+15V
18
VDD
10
RD
INT
11
15
VREF 4
WR
MAX154
MX7824
VOUT A 2
MX7226
DB0–DB7
VOUT B 1
VOUT C
DB0–DB7
VREF+
VOUT D
VREF-
A1
A0
GND
21
16
A1
22
17
A0
DGND
AGND
20
19
6
5
VSS
3
A0
A1
Figure 13. 4-Channel Fast Sample and Infinite Hold
______________________________________________________________________________________
11
MX7824/MX7828
CMOS, High-Speed, 8-Bit ADCs
with Multiplexer
_Ordering Information (continued)
PART
TEMP. RANGE
PIN-PACKAGE
MX7824LEAG
-40°C to +85°C
24 SSOP
ERROR
(LSB)
MX7824KEAG
-40°C to +85°C
24 SSOP
-40°C to +85°C
24 CERDIP
±1/2
MX7824BQ
MX7824UQ
MX7824TQ
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
24 CERDIP
24 CERDIP
24 CERDIP
±1
±1/2
±1
MX7828LN
MX7828KN
MX7828LCWI
0°C to +70°C
0°C to +70°C
0°C to +70°C
28 Plastic DIP
28 Plastic DIP
28 Wide SO
±1/2
±1
±1/2
MX7828KCWI
0°C to +70°C
28 Wide SO
MX7828LCAI
0°C to +70°C
28 SSOP
±1/2
MX7828KCAI
0°C to +70°C
28 SSOP
±1
MX7828LP
0°C to +70°C
28 PLCC
±1/2
0°C to +70°C
28 PLCC
±1
-40°C to +85°C
28 SSOP
±1/2
MX7828KP
AIN4 AIN6 AIN8
(N.C.) (AIN2) (AIN4)
AIN3 AIN5 AIN7
(N.C.) (AIN1) (AIN3)
±1/2
MX7824CQ
MX7828LEAI
___________________Chip Topography
VDD A0
±1
±1
MX7828KEAI
-40°C to +85°C
28 SSOP
MX7828CQ
-40°C to +85°C
28 CERDIP
±1/2
±1
MX7828BQ
-40°C to +85°C
28 CERDIP
±1
MX7828UQ
-55°C to +125°C
28 CERDIP
±1/2
MX7828TQ
-55°C to +125°C
28 CERDIP
±1
A1
A2 (N.C.)
AIN2 (N.C.)
AIN1 (N.C.)
TP (REF OUT)
0.127"
(3.228mm)
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
CS
A0
GND VREF+
INT VREF-
ADY
0.124"
(3.150mm)
( ) ARE FOR MAX154/MX7824
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.