NCV898031 2 MHz Non-Synchronous SEPIC/Boost Controller The NCV898031 is an adjustable output non−synchronous 2 MHz SEPIC/boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting and thermal shutdown. Additional features include low quiescent current sleep mode and microprocessor compatible enable pin. MARKING DIAGRAM 8 SOIC−8 D SUFFIX CASE 751 8 1 Features • • • • • • • • • • • • http://onsemi.com Peak Current Mode Control with Internal Slope Compensation 1.2 V $2% Reference Voltage 2 MHz Fixed Frequency Operation Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump Input Undervoltage Lockout (UVLO) Internal Soft−Start Low Quiescent Current in Sleep Mode (< 10 mA Typical) Cycle−by−Cycle Current Limit Protection Hiccup−Mode Overcurrent Protection (OCP) Hiccup−Mode Short−Circuit Protection (SCP) Thermal Shutdown (TSD) This is a Pb−Free Device Typical Applications • Small Form Factor Point−of−Load Power Regulation • Headlamps • Backlighting 898031 ALYW G 1 898031 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS EN 1 8 VFB ISNS 2 7 VC GND 3 6 VIN GDRV 4 5 VDRV (Top View) ORDERING INFORMATION Device Package Shipping† NCV898031D1R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2012 June, 2012 − Rev. 1 1 Publication Order Number: NCV898031/D NCV898031 6 TEMP ENABLE EN FAULT LOGIC 1 5 CLK SC PWN OSC VC VDRV 7 DRIVE LOGIC 4 2 CL + RC CSA 3 CDRV VDRV Cg L1 Q ● SS CCPL D GDRV L2 ISNS GND Vo ● Co RSNS RF1 SCP 8 Gm CC Vg VIN VFB RF2 Vref Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS Pin No. Pin Symbol 1 EN Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable time−out period. 2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass with a 1.0 mF ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. Function http://onsemi.com 2 NCV898031 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) Rating Value Unit −0.3 to 40 V Peak Transient Voltage (Load Dump on VIN) 45 V Dc Supply Voltage (VDRV, GDRV) 12 V −0.3 to 6 V −0.3 to 3.6 V Dc Voltage (EN) −0.3 to 6 V Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V Operating Junction Temperature −40 to 150 °C Storage Temperature Range −65 to 150 °C 265 peak °C Dc Supply Voltage (VIN) Peak Transient Voltage (VFB) Dc Voltage (VC, VFB, ISNS) Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage. PACKAGE CAPABILITIES Characteristic ESD Capability (All Pins) Human Body Model Machine Model Moisture Sensitivity Level Unit w2.0 w200 KV V 1 Package Thermal Resistance 1. Value based on copper are of 650 Value Junction−to−Ambient, RqJA (Note 1) mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate. http://onsemi.com 3 100 °C/W NCV898031 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit GENERAL Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C − 2.0 − mA Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C − 2.0 6.0 mA Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching − 1.5 2.5 mA Quiescent Current, Switching, normal operation Iq,on Into VIN pin, EN = 1, Switching − 4.0 6.0 mA OSCILLATOR Minimum pulse width ton,min 30 65 90 ns Maximum duty cycle Dmax 85 88 90 % Switching frequency fs 1.8 2.0 2.2 MHz Soft−start time tss From start of switching with VFB = 0 until reference voltage = VREF 520 650 780 ms Soft−start delay tss,dly From EN → 1 until start of switching with VFB = 0 80 100 280 ms 28 34 40 mV/ms − 5.0 10 mA Slope compensating ramp Sa ENABLE EN pull−down current IEN VEN = 5 V EN input high voltage Vs,ih 2.0 − 5.0 V EN input low voltage Vs,il 0 − 800 mV EN time−out ratio %ten From EN falling edge, to oscillator control (EN high) or shutdown (EN low), Percent of typical switching frequency − 250 350 % Acsa Input−to−output gain at dc, ISNS v 1 V 0.9 1.0 1.1 V/V 2.5 − − MHz CURRENT SENSE AMPLIFIER Low−frequency gain Bandwidth BWcsa Gain of Acsa − 3 dB ISNS input bias current Isns,bias Out of ISNS pin Current limit threshold voltage Vcl Voltage on ISNS pin Current limit, Response time tcl CL tripped until GDRV falling edge, VISNS = Vcl + 40 mV Overcurrent protection, Threshold voltage %Vocp Overcurrent protection, Response Time tocp Percent of Vcl From overcurrent event, Until switching stops, VISNS = VOCP + 40 mV − 30 50 mA 360 400 440 mV − 80 125 ns 125 150 175 % − 80 125 ns 0.92 1.28 1.63 mS VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER Transconductance gm,vea VEA output resistance Ro,vea VFB input bias current Ivfb,bias VFB – Vref = ± 20 mV 2.0 − − MW − 0.5 2.0 mA Vref 1.176 1.200 1.224 V VEA maximum output voltage Vc,max 2.5 − − V VEA minimum output voltage Vc,min − − 0.3 V VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − mA VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 − mA Reference voltage Current out of VFB pin http://onsemi.com 4 NCV898031 ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. Characteristic Symbol Conditions Min Typ Max Unit GATE DRIVER Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V 600 800 − mA Sinking current Isink VGDRV ≥ 2 V 500 600 − mA VIN − VDRV, IvDRV = 25 mA − 0.3 0.6 V VIN − VDRV = 1 V 35 45 − mA − − 0.7 V Driving voltage dropout Vdrv,do Driving voltage source current Idrv Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA Driving voltage VDRV IVDRV = 0.1 − 25 mA 6.0 6.3 6.6 V Undervoltage lock−out, Threshold voltage Vuvlo VIN falling 2.95 3.05 3.15 V Undervoltage lock−out, Hysteresis Vuvlo,hys VIN rising 50 150 250 mV Thermal shutdown threshold Tsd TJ rising 160 170 180 °C Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns UVLO THERMAL SHUTDOWN http://onsemi.com 5 NCV898031 TYPICAL PERFORMANCE CHARACTERISTICS 6 TJ = 25°C 6 Iq,sleep, SLEEP CURRENT (mA) Iq,sleep, SLEEP CURRENT (mA) 7 5 4 3 2 1 0 0 10 20 30 VIN, INPUT VOLTAGE (V) VIN = 13.2 V 5 4 3 2 1 0 −50 40 150 0 50 100 TJ, JUNCTION TEMPERATURE (°C) Figure 2. Sleep Current vs. Input Voltage Figure 3. Sleep Current vs. Temperature 64.5 4.90 ton,min MINIMUM ON TIME (ns) Iq,on, QUIESCENTCURRENT (mA) 4.92 4.88 4.86 4.84 4.82 4.80 4.78 4.76 −50 VIN = 13.2 V 50 100 150 0 TJ, JUNCTION TEMPERATURE (°C) 64.0 63.5 63.0 62.5 62.0 61.5 −50 200 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (°C) Figure 4. Quiescent Current vs. Temperature Figure 5. Minimum On Time vs. Temperature 1.205 1.010 Vref, REFERENCE VOLTAGE (V) NORMALIZED CURRENT LIMIT (25°C) 200 1.203 1.005 1.201 1.000 1.199 0.995 0.990 −40 1.197 10 60 110 TJ, JUNCTION TEMPERATURE (°C) 160 1.195 −40 10 60 110 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Normalized Current Limit vs. Temperature Figure 7. Reference Voltage vs. Temperature http://onsemi.com 6 160 NCV898031 TYPICAL PERFORMANCE CHARACTERISTICS 8.0 TJ = 25°C 6 Ienable, PULLDOWN CURRENT (mA) Ienable, PULLDOWN CURRENT (mA) 7 5 4 3 2 1 0 0 1 2 3 4 Venable, VOLTAGE (V) 5 6 7.5 7.0 6.5 6.0 5.5 5.0 −40 10 60 110 160 TJ, JUNCTION TEMPERATURE (°C) Figure 8. Enable Pulldown Current vs. Voltage Figure 9. Enable Pulldown Current vs. Temperature the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. If the voltage across the current sense resistor exceeds the over current threshold voltage, the device enters over current hiccup mode. The device will remain off for the hiccup time and then go through the soft−start procedure. Current Mode Control The NCV898031 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV898031 also includes a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. Short Circuit Protection If the short circuit enable bit is set (SCE = Y), the device will attempt to protect the power MOSFET from damage. When the output voltage falls below the short circuit trip voltage, after the initial short circuit blanking time, the device enters short circuit latch−off. The device will remain off for the hiccup time and then go through the soft−start. Enable The Enable pin has two modes. When a DC logic high (CMOS/TTL compatible) voltage is applied to this pin, the NCV898031 operates at the programmed frequency. When a DC logic low voltage is applied, the NCV898031 enters a low quiescent current sleep mode. The NCV898031 requires 2 clock cycles after the falling edge of the Enable signal to stop switching. UVLO Current Limit Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. The NCV898031 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set http://onsemi.com 7 NCV898031 Internal Soft-Start VDRV To insure moderate inrush current and reduce output overshoot, the NCV898031 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to ensure fast turn on times. The capacitor should be between 0.1 mF and 1 mF, depending on switching speed and charge requirements of the external MOSFET. Oscillator S Q PWM Comparator Gate Drive R ISNS + VIN L1 GDRV CCPL L2 CSA Slope Compensation Co RL VFB Voltage Error VEA NCV898031 Compensation Figure 10. SEPIC Current Mode Schematic SEPIC Design Methodology From this the ideal minimum and maximum duty cycles can be calculated as follows: This section details an overview of the component selection process for the NCV898031 in continuous conduction mode SEPIC. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Current Sense Resistor 3. Select SEPIC Inductors 4. Select Coupling Capacitor 5. Select Output Capacitors 6. Select Input Capacitors 7. Select Feedback Resistors 8. Select Compensator Components 9. Select MOSFET(s) 10. Select Diode D min + V OUT V IN(max) ) V OUT D max + V OUT V IN(min) ) V OUT Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the calculated DWC (worst case) is higher than the Dmax limit of the NCV898031, the conversion will not be possible. It is important for a SEPIC converter to have a restricted Dmax, because while the ideal conversion ratio of a SEPIC converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will skip pulses at high VIN: Define Operational Parameters Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] IOUT(max): maximum output current [A] ICL: desired typical cycle−by−cycle current limit [A] D min w t on(min) fs Where: fs: switching frequency [Hz] ton(min): minimum on time [s] http://onsemi.com 8 NCV898031 Select Current Sense Resistor Current mode control helps resolve some of the resonant frequencies that create issues in voltage mode SEPIC converter designs, but some resonance issues may occur. A resonant frequency exists at Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. Note that the ICL equals the sum of the currents from both inductors. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + f resonance + It may become necessary to place an RC damping network in parallel with the coupling capacitor if the resonance is within ~1 decade of the closed−loop crossover frequency. The capacitance of the damping capacitor should be ~5 times that of the coupling capacitor. The optimal damping resistance (including the ESR of the damping capacitor) is calculated as V CL I CL Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] Select Coupling Inductors R damping + The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VIN. After choosing a peak current ripple value, calculate the inductor value as follows: L+ L1 ) L2 C coupling The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: V OUT(ripple) + I OUT(max)D WC C OUT f s ) ǒ I OUT(max) 1 * D WC ) Ǔ D WCV IN(min) 2 f sL 2 R esr The capacitors need to survive an RMS ripple current as follows: DI L,max f sV OUT Ǹ Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] The maximum average inductor current can be calculated as follows: I Cout(RMS) + ǒ I OUT(max) 2 D WC ) I 2a ) Ǔ I 2r * I aI r DȀ WC 3 where I a + I L1_peak ) I L2_peak * I L1_peak I r + DI L1 ) DI L2 V OUT I OUT(max) The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. V IN(WC) The Peak Inductor current can be calculated as follows: Select Input Capacitors DI I L1,peak + I L1,avg ) L1 2 I L2,peak + I OUT(max) ) Ǹ Select Output Capacitors V IN(WC) 2 D WC I L1,avg + 1 2p Ǹ(L1 ) L2)C coupling The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. DI L2 2 I Cin(RMS) + Where (if L1 = L2): DIL1 = DIL2 Select Coupling Capacitor DI L1 Ǹ12 Select Feedback Resistors Coupling capacitor RMS current is significant. A low ESR ceramic capacitor is required as a coupling capacitor. Selecting a capacitor value too low will result in high capacitor ripple voltage which will distort ripple current and diminish input line regulation capability. Budgeting 2−5% coupling capacitor ripple voltage is a reasonable guideline. The feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. During regulation, the divided voltage will equal Vref. The lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: R upper + R lower I out D WC DV coupling + C coupling f s http://onsemi.com 9 ǒV out * V refǓ V ref NCV898031 Select MOSFET(s) The total feedback resistance (Rupper + Rlower) should be in the range of 1 kW – 100 kW. In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: Select Compensator Components Current Mode control method employed by the NCV898031 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. Q g(total) v Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: I D(max) + Ǹ ǒ D WC I Q(peak) 2 ) ǒDI L1 ) DI L2Ǔ 2 3 I drv fs * I Q(peak)ǒDI L1 ) DI L2Ǔ Ǔ Select Diode where The output diode rectifies the output current. The average current through diode will be equal to the output current: I Q(peak) + I L1_peak ) I L2_peak The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: I D(avg) + I OUT(max) Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: V Q(max) + V OUT(max) V D(max) + V OUT(max) The maximum power dissipation in the diode can be calculated as follows: P D + V f (max) I OUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] Oscillator PWM Comparator GDRV S Q L VOUT Gate Drive R ISNS + VIN CSA Slope Compensation VFB Voltage Error VEA NCV898031 Compensation Figure 11. Boost Current Mode Schematic http://onsemi.com 10 CO RL NCV898031 BOOST TOPOLOGY APPLICATION INFORMATION Design Methodology If the following equation is not satisfied, the device will skip pulses at high VIN: This section details an overview of the component selection process for the NCV898031 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 2. Select Current Sense Resistor 3. Select Output Inductor 4. Select Output Capacitors 5. Select Input Capacitors 6. Select Feedback Resistors 7. Select Compensator Components 8. Select MOSFET(s) 9. Select Diode D min w t on(min) fs Where: fs: switching frequency [Hz] ton(min): minimum on time [s] Select Current Sense Resistor Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: RS + Where: RS: sense resistor [W] VCL: current limit threshold voltage [V] ICL: desire current limit [A] Define Operational Parameters Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage [V] VIN(max): maximum input voltage [V] VOUT: output voltage [V] IOUT(max): maximum output current [A] ICL: desired typical cycle−by−cycle current limit [A] From this the ideal minimum and maximum duty cycles can be calculated as follows: D min + 1 * D WC + 1 * V CL I CL Select Output Inductor The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VIN. After choosing a peak current ripple value, calculate the inductor value as follows: V IN(max) V OUT V IN(WC) V OUT Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated DWC is higher than the Dmax limit of the NCV898031, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ratio of a boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. L+ V IN(WC) 2 D WC DI L,max f sV OUT Where: VIN(WC): VIN value as close as possible to half of VOUT [V] DWC: duty cycle at VIN(WC) DIL,max: maximum peak to peak ripple [A] The maximum average inductor current can be calculated as follows: I L,avg + V OUTI OUT(max) V IN(min) The Peak Inductor current can be calculated as follows: I L,peak + I L,avg ) V IN(min) 2 D WC Lf sV OUT Where: IL,peak: Peak inductor current value [A] http://onsemi.com 11 NCV898031 Select Output Capacitors Select MOSFET(s) The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: Q g(total) v V OUT(ripple) + I OUT(max)(V OUT * V IN(WC)) ǒC OUTfǓ 2 ) Where: Qg(total): Total Gate Charge of MOSFET(s) [C] Idrv: Drive voltage current [A] fs: Switching Frequency [Hz] The maximum RMS Current can be calculated as follows: I OUT(max)V OUTR ESR V IN(WC) The capacitors need to survive an RMS ripple current as follows: I Cout(RMS) + I OUT Ǹ I D(max) + I out V OUT * V IN(WC) V IN(WC) ǸD WC DȀ WC The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: The use of parallel ceramic bypass capacitors is strongly encouraged to help with the transient response. V Q(max) + V OUT(WC) Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. I Cin(RMS) + I drv fs Select Diode The output diode rectifies the output current. The average current through diode will be equal to the output current: V IN(WC) 2 D WC I D(avg) + I OUT(max) Lf sV OUT2 Ǹ3 Additionally, the diode must block voltage equal to the higher of the output voltage and the maximum input voltage: Select Feedback Resistors V D(max) + V OUT(max) The feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. During regulation, the divided voltage will equal Vref. The lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: R upper + R lower The maximum power dissipation in the diode can be calculated as follows: P D + V f (max) I OUT(max) Where: Pd: Power dissipation in the diode [W] Vf(max): Maximum forward voltage of the diode [V] ǒV out * V refǓ V ref The total feedback resistance (Rupper + Rlower) should be in the range of 1 kW – 100 kW. Low Voltage Operation If the input voltage drops below the UVLO or MOSFET threshold voltage, another voltage may be used to power the device. Simply connect the voltage you would like to boost to the inductor and connect the stable voltage to the VIN pin of the device. In boost configuration, the output of the converter can be used to power the device. In some cases it may be desirable to connect 2 sources to VIN pin, which can be accomplished simply by connecting each of the sources through a diode to the VIN pin. Select Compensator Components Current Mode control method employed by the NCV898031 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. http://onsemi.com 12 NCV898031 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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