Preliminary Data Sheet NP40N10YDF, NP40N10VDF, NP40N10PDF R07DS0361EJ0201 Rev.2.01 May 13, 2013 100 V – 40 A – N-channel Power MOS FET Application: Automotive Description These products are N-channel MOS Field Effect Transistors designed for high current switching applications. Features • Low on-state resistance ⎯ RDS(on) = 25 mΩ MAX. (VGS = 10 V, ID = 20 A) (NP40N10YDF) ⎯ RDS(on) = 26 mΩ MAX. (VGS = 10 V, ID = 20 A) (NP40N10VDF) ⎯ RDS(on) = 27 mΩ MAX. (VGS = 10 V, ID = 20 A) (NP40N10PDF) • Low Ciss: Ciss = 2100 pF TYP. (VDS = 25 V, VGS = 0 V) • Logic level drive type • Designed for automotive application and AEC-Q101 qualified Outline Drain Body Diode Gate Source 8-pin HSON 8 7 6 5 TO-252 TO-263 4 4 1 2 3 4 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain 2 2 3 3 1 1. Gate 2. Drain 3. Source 4. Fin (Drain) 1 1. Gate 2. Drain 3. Source 4. Fin (Drain) Remark: Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Ordering Information Part No. NP40N10YDF-E1-AY *1 NP40N10YDF-E2-AY *1 NP40N10VDF-E1-AY *1 NP40N10VDF-E2-AY *1 NP40N10PDF-E1-AY *1 NP40N10PDF-E2-AY *1 Note: Lead Plating Pure Sn (Tin) Pure Sn (Tin) Pure Sn (Tin) Packing Taping (E1 type) Taping (E2 type) Tape 2500 p/reel Taping (E1 type) Taping (E2 type) Tape 800 p/reel Taping (E1 type) Taping (E2 type) Tape 2500 p/reel Package 8-pin HSON TO-252 (MP-3ZP) TO-263 (MP-25ZP) *1. Pb-free (This product does not contain Pb in the external electrode) R07DS0361EJ0201 Rev.2.01 May 13, 2013 Page 1 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary Absolute Maximum Ratings (TA = 25°C) Item Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse) ∗1 Total Power Dissipation (TC = 25°C) Symbol VDSS VGSS ID(DC) ID(pulse) PT1 NP40N10YDF Total Power Dissipation (TA = 25°C) ∗2 PT2 Ratings 100 ±20 ±40 ±80 120 1.0 NP40N10VDF Total Power Dissipation (TA = 25°C) ∗2 1.2 NP40N10PDF Total Power Dissipation (TA = 25°C) Channel Temperature Storage Temperature Single Avalanche Current ∗3 Single Avalanche Energy ∗3 1.8 Tch Tstg IAS EAS Unit V V A A W W 175 −55 to +175 25 61 °C °C A mJ Thermal Resistance Channel to Case Thermal Resistance Channel to Ambient Thermal Resistance ∗2 Rth(ch-C) Rth(ch-A) NP40N10YDF NP40N10VDF NP40N10PDF 1.25 150 125 83.3 °C/W °C/W °C/W °C/W Notes: *1. TC = 25°C, PW ≤ 10 μs, Duty Cycle ≤ 1% *2. Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% copper area (35 μm) *3. Tch(start) = 25°C, VDD = 50 V, RG = 25 Ω, L = 100 μH, VGS = 20 V → 0 V R07DS0361EJ0201 Rev.2.01 May 13, 2013 Page 2 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary Electrical Characteristics (TA = 25°C) Item Zero Gate Voltage Drain Current Gate Leakage Current Gate to Source Threshold Voltage Forward Transfer Admittance ∗1 Drain to Source NP40N10YDF On-state Resistance ∗1 Symbol IDSS IGSS VGS(th) | yfs | RDS(on)1 Min Typ 1.5 20 Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time RDS(on)2 RDS(on)3 RDS(on)1 RDS(on)2 RDS(on)3 RDS(on)1 RDS(on)2 RDS(on)3 Ciss Coss Crss td(on) tr 2.0 40 21 23 24 21 23 24 21 23 24 2100 200 80 15 16 Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage ∗1 Reverse Recovery Time Reverse Recovery Charge td(off) tf QG QGS QGD VF(S-D) trr Qrr 60 5 47 8 12 0.9 67 162 NP40N10VDF NP40N10PDF Note: Max 1 ±100 2.5 Unit μA nA V S mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ mΩ pF pF pF ns ns 25 30 36 26 31 37 27 32 38 3150 300 144 33 40 120 13 71 ns ns nC nC nC V ns nC 1.5 Test Conditions VDS = 100 V, VGS = 0 V VGS = ±20 V, VDS = 0 V VDS = VGS, ID = 250 μA VDS = 5.0 V, ID = 20 A VGS = 10 V, ID = 20 A VGS = 5.0 V, ID = 20 A VGS = 4.5 V, ID = 20 A VGS = 10 V, ID = 20 A VGS = 5.0 V, ID = 20 A VGS = 4.5 V, ID = 20 A VGS = 10 V, ID = 20 A VGS = 5.0 V, ID = 20 A VGS = 4.5 V, ID = 20 A VDS = 25 V, VGS = 0 V, f = 1 MHz VDD = 50 V, ID = 20 A, VGS = 10 V, RG = 0 Ω VDD = 80 V, VGS = 10 V, ID = 40 A IF = 40 A, VGS = 0 V IF = 40 A, VGS = 0 V, di/dt = 100 A/μs *1. Pulsed test TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω PG. VGS = 20 → 0 V TEST CIRCUIT 2 SWITCHING TIME D.U.T. L 50 Ω RL Wave Form RG PG. VDD VGS VGS VDD 0 VGS 10% 90% VDS 90% ID IAS 90% VDS VGS 0 BVDSS VDS 10% 0 10% Wave Form VDS VDD Starting Tch τ τ = 1 μs Duty Cycle ≤ 1% td(on) tr ton td(off) tf toff TEST CIRCUIT 3 GATE CHARGE PG. D.U.T. IG = 2 mA RL 50 Ω VDD R07DS0361EJ0201 Rev.2.01 May 13, 2013 Page 3 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary Typical Characteristics (TA = 25°C) TOTAL POWER DISSIPATION vs. CASE TEMPERATURE 140 120 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 0 0 25 50 75 100 125 150 175 120 100 80 60 40 20 0 0 25 50 75 100 125 150 175 TC - Case Temperature - °C TC - Case Temperature - °C FORWARD BIAS SAFE OPERATING AREA ID - Drain Current - A 1000 RDS(ON) Limited 100 (VGS = 10V) PW = 100 μs ID(Pulse) 10 Power Dissipation Limited 1 ms 1 Secondary Breakdown Limited TC = 25°C Single Pulse 0.1 0.1 10 ms 1 10 100 VDS - Drain to Source Voltage - V R07DS0361EJ0201 Rev.2.01 May 13, 2013 Page 4 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (NP40N10YDF) rth(t) - Transient Thermal Resistance - °C/W 1000 Rth(ch-A) = 150°C/W 100 10 Rth(ch-C) = 1.25°C/W 1 0.1 Single pulse Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% copper area (35 μm) 0.01 100 μ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (NP40N10VDF) rth(t) - Transient Thermal Resistance - °C/W 1000 Rth(ch-A) = 125°C/W 100 10 Rth(ch-C) = 1.25°C/W 1 0.1 Single pulse Mounted on glass epoxy substrate of 40 mm × 40 mm × 1.6 mmt with 4% copper area (35 μm) 0.01 100 μ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH (NP40N10PDF) rth(t) - Transient Thermal Resistance - °C/W 1000 Rth(ch-A) = 83.3°C/W 100 10 Rth(ch-C) = 1.25°C/W 1 0.1 Single Pulse 0.01 100 μ 1m 10 m 100 m 1 10 100 1000 PW - Pulse Width - s R07DS0361EJ0201 Rev.2.01 May 13, 2013 Page 5 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE FORWARD TRANSFER CHARACTERISTICS 100 100 90 VGS = 10 V 80 ID - Drain Current - A ID - Drain Current - A VDS = 10 V Pulsed 5.0 V 4.5 V 70 60 50 40 30 20 1 0.1 Pulsed 0 1 2 3 4 5 0.001 6 0 1 2 3 4 5 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT |yfs| - Forward Transfer Admittance - S 2.5 VDS = VGS ID = 250 μA 2 1.5 1 0.5 0 –100 –50 0 50 100 150 200 100 TA = –55°C –25°C 25°C 75°C 100°C 125°C 10 150°C 175°C VDS = 5 V Pulsed 1 0.01 0.1 1 10 100 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 60 VGS = 4.5 V 50 5.0 V 40 10 V 30 20 10 Pulsed 0 0.1 1 10 ID - Drain Current - A R07DS0361EJ0201 Rev.2.01 May 13, 2013 100 RDS(on) - Drain to Source On-State Resistance - mΩ VGS(th) - Gate to Source Threshold Voltage - V RDS(on) - Drain to Source On-State Resistance - mΩ TA = –55°C –25°C 25°C 75°C 100°C 125°C 150°C 175°C 0.01 10 0 10 45 40 ID = 40 A 35 20 A 30 8A 25 20 15 10 5 0 Pulsed 0 5 10 15 20 VGS - Gate to Source Voltage - V Page 6 of 9 Preliminary DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 70 10000 50 40 30 20 ID = 20 A Pulsed 10 0 –100 –50 0 50 100 150 1000 Coss 100 Crss VGS = 0 V f = 1 MHz 10 0.01 200 0.1 1 10 100 Tch - Channel Temperature - °C VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS DYNAMIC INPUT/OUTPUT CHARACTERISTICS 1000 12 90 VDD = 50 V VGS = 10 V RG = 0 Ω 100 td(off) td(on) tr 10 tf 1 0.1 1 10 VDD = 80 V 50 V 20 V 80 70 10 8 60 VGS 50 6 40 4 30 20 2 10 0 100 ID = 40 A VDS 0 10 20 30 40 ID - Drain Current - A QG- Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DRAIN CURRENT trr - Reverse Recovery Time - ns VGS = 10 V 0V 10 1 Pulsed 0.1 0 50 100 100 IF - Diode Forward Current - A Ciss VGS - Gate to Source Voltage - V 60 Ciss, Coss, Crss - Capacitance -pF VGS = 4.5 V 5.0 V 10 V VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns RDS(on) - Drain to Source On-State Resistance - mΩ NP40N10YDF, NP40N10VDF, NP40N10PDF 0 0.2 0.4 0.6 0.8 VF(S-D) - Source to Drain Voltage - V R07DS0361EJ0201 Rev.2.01 May 13, 2013 1 10 di/dt = 100 A/μs VGS = 0 V 1 0.1 1 10 100 IF - Drain Current - A Page 7 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary Package Drawings (Unit: mm) 8-pin HSON (Mass: 0.13 g TYP.) 1.27 Renesas package code: PLSN0008KA-A 1 5 +0.1 5.0 ±0.2 6 4 0.42 –0.05 7 3 5.15 ±0.2 8 2 6.0 ±0.2 0.10 S 3.8 ±0.2 1.45 MAX. 0.73 0.4 0.42 ±0.05 0 +0.05 –0 0.10 M 5.4 ±0.2 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain 3.18 ±0.2 0.8 ±0.15 0.6 ±0.15 TO-252 (MP-3ZP) (Mass: 0.27 g TYP.) Renesas package code: PRSS0004ZP-A 2.3±0.1 1.0 TYP. 6.5±0.2 5.1 TYP. 4.3 MIN. 0.5±0.1 No Plating 2 3 0.8 1 1.14 MAX. 0.51 MIN. 1.13 6.1±0.2 10.4 MAX. (9.8 TYP.) 4.0 MIN. 4 No Plating 2.3 1. Gate 2. Drain 3. Source 4. Fin (Drain) R07DS0361EJ0201 Rev.2.01 May 13, 2013 0 to 0.25 0.5±0.1 0.76±0.12 2.3 1.0 Page 8 of 9 NP40N10YDF, NP40N10VDF, NP40N10PDF Preliminary TO-263 (MP-25ZP) (Mass: 1.48 g TYP.) No plating 10.0 ±0.3 7.88 MIN. 1.35 ±0.3 Renesas package code: PRSS0004AL-A 4.45 ±0.2 1.3 ±0.2 9.15 ±0.3 0.5 0.025 to 0.25 15.25 ±0.5 8.0 TYP. 4 3 2.5 1 2 R07DS0361EJ0201 Rev.2.01 May 13, 2013 .2 0 to 8 ° 0.25 2.54 1. Gate 2. Drain 3. Source 4. Fin (Drain) 2.54 ±0.25 0.6 ±0 0.75 ±0.2 Page 9 of 9 Revision History NP40N10YDF, NP40N10VDF, NP40N10PDF Data Sheet Description Rev. Date 1.00 2.00 Feb 21, 2013 Mar 11, 2013 2.01 May 13, 2013 Page — Summary First Edition Issued 1 7 "Outline" added Modification of "CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE" 1 8 Modification of "Outline" Modification of "Package Drawings 8-pinHSON" All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. 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