NT68P81
USB Keyboard Micro-Controller
Features
n Built-in 6502C 8 -bit CPU
n 3 MHz CPU operation frequency when oscillator is
running at 6 MHz
n 6K bytes of OTP (one time programming) ROM
n 256 bytes of SRAM
n One 8-bit programmable base timer with pre-divider
circuit
n 29 programmable bi-directional I/O pins including two
external interrupts
n
n
n
n
n
n
n
n
n
3 LED direct sink pins with internal serial resistors
On-chip oscillator (Crystal or Ceramic Resonator)
Watch-dog timer reset
Built-in power-on reset
USB interface
3 supported endpoints
Remote wakeup provided
CMOS technology for low power consumption
40-pin DIP package, 42-pad Dice form and COB
General Description
The NT68P81 is a single chip micro-controller for USB
keyboard applications. It incorporates a 6502C 8-bit
CPU core, 6K bytes of OTP ROM, and 256 bytes of RAM
used as working RAM and stack area. It also includes 29
programmable bi-directional I/O pins with built-in
resistors, and one 8-bit pre-loadable base timer.
Pin Configuration
Additionally, it includes a built-in power-on reset, a builtin low voltage reset, an oscillator that requires crystal or
ceramic resonator applied, and a watch-dog timer that
prevents system standstill.
Pad Configuration
GND
1
40
OSCI
VCP
2
39
OSCO
VDP
3
38
VD D
VDM
4
37
LED2 [MODE2]
P16
28
26
LED1 [MODE1]
P17
27
LED0 [MODE0]
P20
28
P21
29
P22
30
P23
31
5
[PGM] P31
6
36
35
INT0/P32
7
34
INT1/P33
8
33
P27 [DB7]
P26 [DB6]
P34
9
32
P25 [DB5]
31
P24 [DB4]
P24
32
30
P23 [DB3]
P25
33
29
P22 [DB2]
P26
34
28
P21 [DB1]
P27
35
P20 [DB0]
P17
LED0
36
LED1
37
[VPP] RESET
10
NT68P81
[OE] P30
[A0] P00
11
[A1] P01
12
[A2] P02
[A3] P03
13
14
27
[A4] P04
15
[A5] P05
16
26
25
[A6] P06
17
[A7] P07
[A8] P10
[A9] P11
P16
P15 [CE]
18
24
23
19
22
P13 [A11]
20
21
P12 [A10]
P
1
5
P
1
4
P
1
3
25
24
23
22
21
P
1
0
20
P
0
7
19
P
0
6
18
P
0
5
17
16
P04
15
P03
14
P02
13
P01
12
P00
11
RESET
10
P34
9
P33
8
P32
7
P31
6
P30
1
L
E
D
2
1
P
1
1
NT68P81
38
P14 [A12]
P
1
2
39
40
V
C
C
V
C
C
41
O
S
C
O
42
O
S
C
I
2
G
N
D
G
N
D
3
V
C
P
4
5
V
D
P
V
D
M
V2.0
NT68P81
Block Diagram
OSCI
Timing Generator
Power Down/Up
Transceiver
VCP
VDP
VDM
OSCO
SIE
6502
CPU
Interrupt
Controller
6K Bytes
OTP ROM
Serial Bus
Manager
256 Bytes
SRAM
FIFOs
Watch Dog
Timer
V DD
GND
RESET
Power-On
Reset
I/O PORTs
Base Timer
2
LED0
LED1
LED2
P00~P07
P10~P17
P20~P27
P30~P34
NT68P81
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
I/O
Shared with OTP[I/O]
Description
1
1,2
GND
P
Ground
2
3
VCP
O
USB 3.3V driver
3
4
VDP
I/O
USB data plus
4
5
VDM
I/O
USB data minus
5
6
P30
I/O
Bi-directional I/O pin
OE [I]
I/O
6
7
Program output enable
Bi-directional I/O pin
P31
PGM [I]
Program control
7
8
P32/INT0
I/O
Bi-directional I/O shared with INT0
8
9
P33/INT1
I/O
Bi-directional I/O shared with INT1
9
10
P34
I/O
Bi-directional I/O pin
10
11
RESET
I
Internally pulled down resistor
VPP [P]
11 ~ 18
12 ~ 19
P00 ~ P07
I/O
Bi-directional I/O pin
A0 ~ A7 [I]
19 ~ 23
20 ~ 24
P10 ~ P14
I/O
25
P15
I/O
26
P16
I/O
27
27 ~ 34
28 ~ 35
36
I/O
Bi-directional I/O pin
P20 ~ P27
I/O
Bi-directional I/O pin
LED0
O
37
LED1
O
38
LED2
O
39,40
39
41
Mode selection
LED direct sink
MODE2 [I]
38
Mode selection
LED direct sink
MODE1 [I]
37
Program data buffer
LED direct sink
MODE0 [I]
36
OTP Program Input Voltage High
P17
DB0 ~ DB7 [I/O]
35
Program chip enable
Bi-directional I/O pin
VPIH[I]
26
Program address buffer
Bi-directional I/O pin
CE [I]
25
Program address buffer
Bi-directional I/O pin
A8 ~ A12
24
Program supply voltage
Mode selection
VDD
P
Power supply (+5V)
OSCO
O
Crystal oscillator output
CLK[I]
3
Program Clock
NT68P81
40
42
OSCI
I
Crystal oscillator input
VPIL[I]
* [ ]: OTP Mode
4
OTP Program Input Voltage Low
NT68P81
Functional Description
1. 6502C CPU
The 6502C is an 8 -bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory
range, and an interrupt input. Other features are also included.
The CPU clock cycle is 3MHz (6MHz system clock divided by 2). Please refer to 6502 data sheet for more detailed
information.
7
0
Accumulator A
7
0
Index Register Y
7
0
Index Register X
15
8
Program Counter PCH
PCL
7
0
7
0
Stack Pointer SP
7
N
0
V
B
D
I
Z
C
Status Register P
Carry
1 = TRUE
Zero
1 = Result ZERO
1 = DISABLE
IRQ Disable
Decimal Mode
BRK Command
1 = TRUE
1 = BRK
Overflow
1 = TRUE
Negative
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
NT68P81
2.Instruction Set List
Instruction Code
Meaning
Operation
ADC
Add with carry
A + M + C → A，C
AND
Logical AND
A•M → A
ASL
Shift left one bit
C ← M7•••M0 ← 0
BCC
Branch if carry clear
Branch on C＝0
BCS
Branch if carry set
Branch on C＝1
BEQ
Branch if equal to zero
Branch on Z＝1
BIT
Bit test
A•M，M7 → N，M6 → V
BMI
Branch if minus
Branch on N＝1
BNE
Branch if not equal to zero
Branch on Z＝0
BPL
Branch if plus
Branch on N＝0
BRK
Break
Forced interrupt PC + 2↓ PC↓
BVC
Branch if overflow clear
Branch on V＝0
BVS
Branch if overflow set
Branch on V＝1
CLC
Clear carry
0→ C
CLD
Clear decimal mode
0→ D
CLI
Clear interrupt disable bit
0→ I
CLV
Clear overflow
0→ V
CMP
Compare accumulator to memory
A－M
CPX
Compare with index register X
X－ M
CPY
Compare with index register Y
Y－M
DEC
Decrement memory by one
M－1→M
DEX
Decrement index X by one
X－ 1 → X
DEY
Decrement index Y by one
Y－1→Y
EOR
Logical exclusive-OR
A ♁ M→A
INC
Increment memory by one
M+1→ M
INX
Increment index X by one
X+1 → X
INY
Increment index Y by one
Y+1→ Y
JMP
Jump to new location
(PC + 1) → PCL，(PC + 2) → PCH
JSR
Jump to subroutine
PC + 2↓，(PC + 1) → PCL，(PC + 2) → PCH
6
NT68P81
Instruction Set List (contiuned)
Instruction Code
Meaning
Operation
LDA
Load accumulator with memory
M→A
LDX
Load index register X with memory
M→X
LDY
Load index register Y with memory
M→Y
LSR
Shift right one bit
0 → M7•••M0 → C
NOP
No operation
No operation (2 cycles)
ORA
Logical OR
A+M→A
PHA
Push accumulator on stack
A↓
PHP
Push status register on stack
P↓
PLA
Pull accumulator from stack
A↑
PLP
Pull status register from stack
P↑
ROL
Rotate left through carry
C ← M7•••M0 ← C
ROR
Rotate right through carry
C → M7•••M0 → C
RTI
Return from interrupt
P ↑，PC ↑
RTS
Return from subroutine
PC ↑，PC+1 → PC
SBC
Subtract with borrow
A － M － C → A，C
SEC
Set carry
1→ C
SED
Set decimal mode
1→ D
SEI
Set interrupt disable status
1→ I
STA
Store accumulator in memory
A →M
STX
Store index register X in memory
X →M
STY
Store index register Y in memory
Y →M
TAX
Transfer accumulator to index X
A→X
TAY
Transfer accumulator to index Y
A→Y
TSX
Transfer stack pointer to index X
S→X
TXA
Transfer index X to accumulator
X→ A
TXS
Transfer index X to stack pointer
X→ S
TYA
Transfer index Y to accumulator
Y→A
*For more detailed specifications, pleas e refer to 6502 programming data book.
7
NT68P81
3. OTP ROM: 6K X 8 bits
The built-in OTP ROM program code, executed by the 6502 CPU, has a capacity of 6K x 8-bit and is addressed from
E800H to FFFFH. It can be programmed by the universal EPROM writer through a conversion adapter and programming
configuration such as INTEL - 27C64. In the OPERATING mode, the OTP ROM is integrated with the system and it cannot
be directly accessed. When the user wants to work with the OTP ROM alone, the user must first enter the
PROGRAMMING mode by setting: PIN < RESET = VPP>. At this time, through multiplex pins, we can use familiar
procedures to program and verify the OTP ROM block with the universal programmer.
OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
VIH
Parameter
Input Voltage
Min.
Max.
Unit
VDD - 0.3
VDD + 0.3
V
1
-0.3
0.3
V
1
+/-10
µA
VIL
IIL
Input Current
IOH
Output Voltage
IOL
IDD
ISTB1
Note:
Typ.
Test Conditions
-400
µA
VDD = 5V, VOH = 4.5V
1
mA
VDD = 5V, VOL = 0.5V
1
mA
F = 3MHz
100
µA
Operating Current
Standby Current
Note
3
1. All inputs and outputs are CMOS compatible
2. F = 3MHz, l out = 0mA, CE = VIH. VDD = 5V
3. CE = VIH, OE = VIL, VDD = 5V
OTP ROM Mega Cell A.C. Electrical Characteristics (READ Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
Parameter
Min.
Tcyc
Cycle Time
T12
Non-overlap Time to PH1 & PH2
Tacc
Max.
250
5
Unit
Conditions
ns
65
ns
Address Access Time
145
ns
Tce
OTPCE to Output Valid
145
ns
Tst
Output Data Setup Time
20
ns
Toh
Output Data Hold Time
0
ns
OTP ROM Mega Cell A.C. Test Conditions
Output Load
1 CMOS Gate and CL = 10pF
Input Pulse Rise and Fall Times
10ns Max.
Input Pulse Levels
0V to 5V
Timing Measurement Reference Level
Inputs 0V and 5V Outputs 0.3V and 4.7V
8
2
4.5V < VDD < 5.5V
NT68P81
OTP ROM Mega Cell Timing Waveforms (READ mode)
T12
Tcyc
PH1
PH2
A0 - A14
OTPCE
DB0 - DB7
Tacc & Tce
Tst
Toh
OTP ROM Mega Cell D.C. Electrical Characteristics (PROGRAMMING Mode)
(VDD = 5V, TA = 25℃, unless otherwise specified)
Symbol
VDD
Parameter
Input Voltage
VIL
IIL
Output Current
IOH
Output Current
IOL
IDD
Typ.
Max.
Unit
6
6.5
V
10.5
12.75
V
2
VDD + 0.3
V
-0.3
0.6
V
+/-10
μA
Supply Voltage
VPP
VIH
Min.
μA
VDD = 5V, VOH = 4.5V
1
mA
VDD = 5V, VOL = 0.5V
IPP
Input Clock
VPIH
Input Voltage
VPIL
30
mA
20
mA
53.203424
MHz
2
VDD + 0.3
V
-0.3
0.6
V
9
Note
4
-400
Operating Current
CLK
Test Conditions
VPP = 12.75V
NT68P81
Note:
4. For reliability concerns, we suggest VDD = 6V & VPP = 12.75V for testing OTP ROM AC characteristics in
PROGRAMMING mode, and the same condition is suggested for universal programmer supply voltage.
OTP ROM Mega Cell A.C. Electrical Characteristics (PROGRAMMING Mode)
(TA = 25℃, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Tms
Mode Decode Setup Time
2
µs
Tmh
Mode Decode Hold Time
2
µs
Tas
Address Setup Time
2
µs
Tah
Address Hold Time
2
µs
Tces
CE Setup Time
2
µs
Tceh
CE Hold Time
2
µs
Tds
Date Setup Time
2
µs
Tdh
Data Hold Time
2
µs
Tvs
VPP Setup Time
2
µs
Tpw
Program Pulse Width
100
µs
Tdv
OE to Output Valid
150
ns
Tdf
OE to Output High-Z
90
ns
OTP ROM Mega Cell A.C. Test Conditions
Output Load
1 TTL Gate and C L = 100pF
Input Pulse Rise and Fall Times
10ns max.
Input Pulse Levels
0.45V to 2.4V
Timing Measurement Reference Level
Inputs 0.8V and 2.2V
Outputs 0.8V and 2.4V
10
Test Conditions
CE = VIL
Note
NT68P81
OTP ROM Mega Cell Timing Waveform (Program)
Tms
Tmh
MODE DEC.
TEST = VPP, MODE [0..2] = 000;
Tvs
VPP
Tas
Tah
A0 - A14
CE
Tceh
Tces
OE
Tdf
DB0 - DB7
DOUT
D IN
Tdv
PGM
Tds
Note:
Tpw
Tdh
5. VDD must be applied simultaneously or before VPP and cut off simultaneously or after VPP.
6. Removing the device from the socket or setting the device in socket with VPP = 12.75V may cause permanent
damage.
11
NT68P81
OTP ROM Mega Cell Mode Selection
RESET
= 12.75V, VPIL = VIL,
Mode [0..2]
Mode
CE
OE
VPP
DB0-DB7
Normal Operating
－
－
－
－
VPIH = VIH
not VPP
－
VPP
000
Output Disable
－
VIH
－
high-Z
VPP
000
Program
VIH
VIH
VPP
data in
VPP
000
Program Verify
VIH
VIL
－
data out
VPP
000
Program Inhibit (Standby)
VIL
－
VPP
high-Z
VPP
001
Security (Program)
VIH
－
VPP
data in
VPP
010
Word-line Stress
－
－
VPP
－
VPP
011
Bit-line Stress
－
－
VPP
“0”
VPP
100
OTP Row (after pkg)
VIH
VIH
VPP
data in
VPP
101
OTP Column (after pkg)
VIH
VIH
VPP
data in
*The security byte is at $0000 address.
When the VPP input is at 12.75V and CE is at VIH, the chip
is in the PROGRAMMING mode.
READ MODE
The NT68P81's OTP ROM mega cell has 2 control pins.
The CE (chip enable) controls the operation power and is
PROGRAM VERLFY MODE
used for device selection. The OE (output enable)
controls the output buffers.
The VERIFY mode will check to see that the desired data
is correctly programmed on the programmed bit. The
VERIFY is accomplished with CE at VIH, VPP input is at
OUTPUT DISABLE MODE
12.75V, and OE = VIL.
If OE = VIH, the outputs will be in a high impedance state.
So two or more ROMs can be connected together on a
common bus.
PROGRAM INHIBIT
Using this mode, programming of two or more OTP ROMs
in parallel with different data is accomplished. All inputs
STANDBY MODE
except for CE and OE may be commonly connected. The
TTL high level program pulse is only applied to the CE of
the desired device and TTL high level signal is applied to
the other devices.
By applying a low level to the chip is in standby mode, it
will reduce the operating current to 100µA.
PROGRAM MODE
Initially, all bits are in "1" state which is an erased state.
Thus the program operation is to introduce "0" data into
the desired bit locations by electronic programming.
12
NT68P81
4. SRAM: 256 X 8 bits
The built-in SRAM is used for general purpose data memory and for stack area. SRAM is addressed from 0080H to
017FH. Because the 6502C default stack pointer is 01FFH, the stack area will map $01FF-$0180 to $00FF-$0080, thus
the programmer can set the “S” register to 7FH when starting program, allowing stack point to be 017FH.
as;
LDX
TXS
#$7F
$0000
$001F
System Registers
Unused
$0080
$00FF
RAM
$0100
$017F
RAM
stack pointer
Unused
$E800
ROM
$FFFA
NMI-L
$FFFB
NMI-H
$FFFC
RST-L
$FFFD
RST-H
$FFFE
IRQ-L
$FFFF
IRQ-H
NMI Vector
RESET Vector
IRQ Vector
13
NT68P81
5. System Reserved Registers
Address
Register
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
$0000
IRQFUNC
00H
－
－
－
－
KBD
INT1
INT0
TMR
R
$0001
IRQCLRF
00H
－
－
－
－
CKBD
CINT1
CINT0
CTMR
W
$0002
IE_FUNC
00H
－
－
－
－
EKBD
EINT1
EINT0
ETMR
R/W
$0003
IRQUSB
00H
SUSP
STUP
－
－
IN2
IN1
OT0
IN0
R
$0004
IRQCLRU
00H
CSUSP
CSTUP
－
－
CIN2
CIN1
COT0
CIN0
W
$0005
IE_USB
00H
ESUSP
ESTUP
－
－
EIN2
EIN1
EOT0
EIN0
R/W
$0006
BT
00H
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
$0007
TCON
01H
－
－
－
－
－
－
－
ENBT
W
$0008
TMOD
00H
－
－
－
－
－
TM2
TM1
TM0
R/W
$0009
PORT0
FFH
P07
P06
P05
P04
P03
P02
P01
P00
R/W
$000A
PORT1
FFH
P17
P16
P15
P14
P13
P12
P11
P10
R/W
$000B
PORT2
FFH
P27
P26
P25
P24
P23
P22
P21
P20
R/W
$000C
PORT3
1FH
－
－
－
P34
P33
P32
P31
P30
R/W
$000D
LED
07H
－
－
－
－
－
LED2
LED1
LED0
W
$000E
CLRWDT
00H
0
1
0
1
0
1
0
1
W
$000F
MODE_FG
02H
－
－
－
－
－
－
POF
SUSF
R/W
－ : no effect
6. Power-on Reset
7. Timing Generator
Built-in power-on reset circuit can generate a minimum of
5ms pulse to reset the entire chip. The user also can use
an external RESET pin to reset the entire chip.
This block generates the system timing and control
signals supplied to the CPU and on-chip peripherals. The
crystal oscillator generates a 6MHz system clock. It only
generates 3MHz clock for CPU.
14
NT68P81
8. Base Timer (BT)
The Base Timer is an 8 -bit counter with a programmable clock source selection. The BT can be enabled/disabled by the
CPU. After reset, the BT is disabled and cleared. The BT can be preset by writing a preset value to BT7 ~ BT0 of the BT
register at any time. When the BT is enabled, the BT starts counting from the preset value. When the value reaches FFH, it
generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the BT will wrap
around and begin counting at 00H. The BT can be enabled by writing a "0" to " ENBT " bit in the TCON (Timer Control)
register. The ENBT signal is level trigger.
The input clock source of BT is controlled by the TMOD register. The following table shows 8 ranges of the BT.
TM2
TM1
TM0
Pre-scalar Ratio
Min. Count
Max. Count
0
0
0
System Clock/2 3
1.33 µs
341.33 µs
0
0
1
System Clock/2 4
2.66 µs
682.66 µs
0
1
0
System Clock/2 5
5.32 µs
1.36 ms
0
1
1
System Clock/2 6
10.64 µs
2.72 ms
1
0
0
System Clock/2 7
21.28 µs
5.44 ms
1
0
1
System Clock/2 8
42.56 µs
10.89 ms
1
1
0
System Clock/2 9
85.12 µs
21.79 ms
1
1
1
System Clock/2 10
170.24 µs
43.58 ms
For counting accuracy, please set the TMOD register first, then preset the BT register, and enable the base timer finally.
(TM2, TM1, TM0) = (1, 1, 1) is reserved for USB driver use.
15
NT68P81
9. Interrupt Controller
There are 10 interrupt sources: Timer, INT0, INT1, KBD, SUSP, IN0, IN1, IN2, OT0 and STUP.
9.1. Timer Interrupt
When the BASE TIMER overflows, it will set the TMR flag, If the interrupt is enabled by writing "1" to the bit 0 in IE_FUNC
($0002H), then it will interrupt 6502 CPU. The TMR flag can be read by the software. Once set by an interrupt source, it can
read from bit0 in IRQFUNC ($0000H) and remains high unless cleared by writing "1" to the bit 0 in IRQCLRF ($0001H). All
of register's data is cleared to "0" at initialization by the system reset. When an interrupt occurs, the CPU jumps to $FFFEH
& $FFFFH to execute the interrupt service routine, thus the TMR flag must be cleared by the software.
9.2. INT0 Interrupt
As soon as INT0 pin detects a falling edge trigger, NT68P81 sets the INT0 flag ($0000H, bit1). After that, the 6502 CPU is
interrupted if this interrupt has been already been enabled by writing “1” to EINT0 ($0002H, bit1). If the EINT0 flag is
cleared, the 6502 CPU can’t be INT0 interrupted even if the INT0 flag is set. INT0 flag can be only be set by hardware and
cannot be set or cleared directly by the software except for writing “1” to CINT0 ($0001H, bit1) flag to clear INT0 flag. When
an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine so the INT0 flag must
be cleared by software.
9.3. INT1 Interrupt
As soon as the INT1 pin detects a falling edge trigger, NT68P81 sets the INT1 flag ($0000H, bit2). Then the 6502 CPU is
interrupted if the interrupt has already been enabled by writing “1” to EINT1 ($0002H, bit2). If EINT0 flag is cleared, the
6502 CPU can’t be INT1 interrupted even if INT1 flag is set. INT1 flag can only be set by the hardware and can not be set
or cleared directly by the software except for writing “1” to CINT1 ($0001H, bit2) flag to clear INT1 flag.
When an interrupt occurs, CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the INT1 flag must be
cleared by the software.
9.4. KBD Interrupt
This interrupt will set the KBD flag ($0000H, bit3) every 4ms(HID 1.00 version) to indicate that keyboard scan data is ready
to send for endpoint1. Then the 6502 CPU is interrupted if this interrupt has been enabled already by writing “1” to EKBD
($0002H, bit3). If the EKBD flag is cleared, the 6502 CPU can’t be KBD interrupted even if the KBD flag is set. The KBD
flag can only be set by the hardware and can not be set or cleared directly by the software except for writing “1 ” to CKBD
($0001H, bit 3) flag to clear KBD flag.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the KBD flag must
be cleared by the software.
9.5. IN0 Token Interrupt
When an IN TOKEN for endpoint 0 is done, it will set the IN0 flag. If this interrupt is enabled by writing "1" to EIN0 ($0005H,
bit0), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN0 flag must
be cleared by the software.
9.6. OT0 (OUT 0) Token Interrupt
When an OUT TOKEN for endpoint 0 is done, it will set the OT0 flag. If this interrupt is enabled by writing "1" to EOT0
($0005H, bit1), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the OT0 flag must
be cleared by the software.
16
NT68P81
9.7. IN1 Token Interrupt
When an IN TOKEN for endpoint 1 is done, it will set the IN1 flag. If this interrupt is enabled by writing "1" to EIN1 ($0005H,
bit2), it will interrupt the 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN1 flag must
be cleared by the software.
9.8. IN2 Token Interrupt
When an IN TOKEN for endpoint 2 is done, it will set the IN2 flag. If this interrupt is enabled by writing "1" to EIN2 ($0005H,
bit3), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the IN2 flag must
be cleared by the software.
9.9. STUP (SETUP) Token Interrupt
When a SETUP TOKEN for endpoint 0 is done, it will set the STUP flag. If this interrupt is enabled by writing "1" to ESTUP
($0005H, bit6), it will interrupt 6502 CPU.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the STUP flag
must be cleared by the software.
9.10. SUSP Interrupt
When USB SIE detects a suspend signal, it sets the SUSP flag. Then the 6502 CPU is interrupted if the interrupt has
already been enabled by writing “1” to ESUSP ($0005H, bit7). If ESUSP flag is cleared, 6502 CPU can’t be SUSP
interrupted even if SUSP flag is set. SUSP flag can be set by H/W only and can’t be set/cleared directly by the software
except for writing “1” to CSUSP ($0004H, bit 7) flag to clear SUSP flag.
When an interrupt occurs, the CPU jumps to $FFFEH & $FFFFH to execute the interrupt service routine, the SUSP flag
must be cleared by the software.
10. I/O PORTs
The NT68P81 has 32 pins dedicated to input and output. These pins are grouped into 5 ports, as follows:
PORT0 (P00~P07)
PORT0 is an 8-bit bi-directional CMOS I/O port that is internally pulled high by PMOS. Each pin of PORT0 can be bit
programmed as an input or output port under software control. When programmed as output, data is latched to the port
data register and output to the pin. PORT0 pins with “1” written to them are pulled high by the internal PMOS pull-ups, and
can be used as inputs in that state, then these input signals can be read. The port will output high after the reset.
PORT1 (P10~P17): Functions the same as PORT0.
PORT2 (P20~P27): Functions the same as PORT0.
PORT3 (P30~P34): Functions the same as PORT0. Except for P33/P32 is shared with INT1/INT0 pin. It is also a Schmitt
Trigger input with an interrupt source of falling edge sensitive.
LED: There are three LED direct sink pins which require no external serial resistors.
The address is mapped to $000DH.
17
NT68P81
11. Watch-Dog Timer (WDT)
The NT68P81 has a watch-dog timer reset function that protects programs against system standstill. The clock of the
WDT is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when the operation frequency is 6MHz.
The timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause a system
reset (This cannot be disabled by the software). Before watch-dog reset occurs, the software will clear the watch-dog
register by writing #55H to CLRWDT ($000EH) register.
For example:
LDA
STA
#$55H
$000E
12. Power Control
The power-off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is
set by hardware when an external power VCC arises to its normal operating level, and must be cleared by the software in
the cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset.
Address
Register
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
$000FH
MODE_FG
02H
-
-
-
-
-
-
POF
SUSF
R/W
13. Universal Serial Bus Interface
Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9.
14. Suspend and Resume
Suspend:
When SIE receives the suspend signal, NT68P81 generates a SUSP interrupt request. In the SUSP interrupt service
routine, the software will carry out the following steps:
1)
2)
3)
4)
5)
6)
Clear SUSP IRQ flag,
Store all the port status,
Force return lines (PORT2) pull-high,
Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low,
Turn off LED output,
Clear watch-dog register
After the above action has been completed, the software will then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to #AAH
in order to enter the SUSPEND mode. The oscillator will stop for in order to save power.
Resume:
When the SIE detects a resume signal, the NT68P81 trigger oscillator to oscillate and resets whole chip. After a reset,
software checks the status of POF bit in MODE_FG register to see whether a cold start reset or a warm start reset
occurred. If cold reset, it executes all initial procedure. If warm reset, software checks the status of SUSF bit in MODE_FG
register to see whether a watch-dog reset or resume reset. Under resume reset condition, programmer should restores
all port status. After a warm start, user software should clear the SUSF bit. When any key stroked in suspend mode, it
remotely resume NT68P81 functions. The action is same as host resume.
18
NT68P81
15. Reset Source Summary
These are 5 reset sources in NT68P81 as shown below.
No.
Type
Function
Description
1
Cold
External Pin ( RESET )
Applied Externally
2
Cold
Power-on Reset
Reset after Power-on
3
Cold
USB Reset Signaling
10 ms Reset Period
4
Warm-1
Resume Reset
USB Reset Period
5
Warm-2
Watch-dog Reset
Reset every 0.15S (OSC = 6MHz)
NT68P81 can also be reset externally through the RESET pin. A reset is initialed when the signal at the RESET pin is
held Low for at least 10 system clocks. When RESET signal goes high, the NT68P81 begins to work. The following
shows the definition of RESET input low pulse width.
VDD
VDD
20%VDD
20%VDD
Trstb
16. PS/2 Mouse Application
A PS/2 mouse interface is implemented in P32 (CLK), P33 (DATA) and P34 (Power Control). The timing diagrams are
described as follows.
1st
CLK
CLK
T1
2nd
CLK
Start Bit
T5
T1A
Bit 0
Parity Bit
Auxiliary Device Sending Data Timings
Timing
Description
MIN/MAX
T1
T1A
T2
T3
T4
Time from DATA transaction to falling edge of CLK 1
Time from DATA transaction to falling edge of CLK 2-11
Time from rising edge of CLK to DATA transaction
Duration of CLK inactive (LOW)
Duration of CLK active (HIGH)
Time to Auxiliary Device inhibit after clock 11 to ensure the Auxiliary Device
does not start another transmission
5/25u s
5/25u s
5/T4-5u s
30/50u s
30-50u s
T5
11th
CLK
T4
T3
T2
DATA
10th
CLK
19
>0/50u s
Stop Bit
NT68P81
CLK
I/O Inhibit
2nd
CLK
1st
CLK
10th
CLK
9th
CLK
11th
CLK
T7
T6
T9
T10
T8
DATA
Start Bit
Bit 0
Parity Bit
Stop Bit
Auxiliary Device Receiving Data Timings
Timing
Description
MIN/MAX
T6
T7
Duration of CLK interface (LOW)
Duration of CLK active (HIGH)
Time from inactive to active CLK transition, used to time when the Auxiliary Device samples
DATA
Time from falling edge of line control bit to falling edge of clock 11 CLK
Time from rising edge of clock 11 to rising edge of line control bit
30/50u s
30/50u s
T8
T9
T10
20
5/25u s
5u s/
5/25 u s
Line Control Bit
NT68P81
Absolute Maximum Rating*
*Comments
DC Supply Voltage . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied and exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Input/Output Voltage . . . . . . . .GND - 0.2V to VDD + 0.2V
Operating Ambient Temperature . . . . . . . . .0 °C to 70 °C
Storage Temperature . . . . . . . . . . . . . .-55 °C to +125 °C
Operating Voltage (VDD ) . . . . . . . . . . . . .+4.4V to +5.25V
DC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted)
Symbol
Parameters
Min.
Typ.
Max.
Unit
4.4
5
5.25
V
VDD
Operating Voltage
IOP
Operating Current
20
mA
ISP
Suspend Current
500
µA
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage
VOL1
Output Low Voltage (P0/P1/P2)
VOL2
Output Low Voltage (P3)
ILED
LED Sink Current
VSTIH
Schmitt Trigger Input High Voltage
VSTIH
Schmitt Trigger Input Low Voltage
2
2.4
0.8
No load
V
0.8
6
Conditions
V
V
IOH = -100µA
0.4
V
IOL1 = 4mA
0.4
V
IOL2 = 5mA
10
14
mA
VOL = 3.2V
1.7
2
V
1.1
V
AC Electrical characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 6MHz, unless otherwise noted)
Symbol
Parameters
Min.
Typ.
Max.
Unit
Conditions
6
6.03
MHz
OSC within +/- 0.5%
FOSC
Oscillator Frequency
5.97
TRSTB
RESET Input Low Pulse Width
1.67
TPOR
Power-on Reset Time
5
USB DC/AC SPECIFICATIONS
Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7.
21
µs
30
ms
10 system clocks
NT68P81
Application Circuit 1 (Simple Keyboard with PS/2 Mouse)
VC C
PS/2 Mouse CLK
PS/2 Mouse DATA
PS/2 Mouse Power Control
P32
P33
P34
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
Vcc
0.1 µF
10 µF
GND
LED0
Scroll Lock
LED1
Num Lock
LED2
Caps Lock
NT68P81
RESET
*1
*1 : RESET can be direct
connect to VCC if the
external reset is not
used for module test.
4.7KO
OSCI
6Mhz Crystal
OSCO
P20
P21
P22
P23
P24
P25
P26
P27
D+
To USB Cable
D-
VDP
VDM
1.5KO
VCP
4 . 7µF
P20
P21
P22
P23
P25
P26
E
F3
D
F4
C
K133
F2
P27
#
3
R
T
F
G
V
B
%
5
$
4
U
Y
J
H
M
N
I
}
]
K
F6
K56
^
6
+
=
O
F7
L
APP
F8
&
7
*
8
(
9
+
(Num)
K107
Home
End
Page
Up
Page
Down
Insert
Kor_R
Delete
Kor_L
9
PgUp
8
7
Home
K14
P
6
5
(Num)
4
Enter
(Num)
3
PgDn
2
.
Del
1
End
Space
L-Shift
R-Shift
Back
Space
{
[
|
\ (K29)
:
;
Scroll
Lock
000
Pause
00
0
Ins
P24
<
,
>
.
*
(Num)
/
(Num)
(Num)
Num
Lock
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
F11
Enter
F12
F9
F10
"
'
|
\(K42)
?
/
_
-
)
0
L-Alt
Print
Screen
R-Alt
L-Ctrl
R-Ctrl
P12
P13
P14
F5
P15
L-WIN
P16
Kor_L
Q
W
R-Win
Kor_R
TAB
A
Esc
Z
K131
~
`
Caps
Lock
S
K45
X
K132
F1
!
1
@
2
P17
P30
P31
Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
22
NT68P81
Application Circuit 2 (Windows 2000 Compatible Keyboard)
V CC
Vcc
0.1 µ F
10 µF
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
P32
GND
LED0
Scroll Lock
LED1
Num Lock
LED2
Caps Lock
NT68P81
RESET
4.7K O
*1
6Mhz Crystal
OSCO
P20
P21
P22
P23
P24
P25
P26
P27
D+
To USB Cable
D-
VDP
VDM
1 . 5 KO
VCP
4.7µF
P20
P21
P22
P23
P24
P25
P26
E
F3
D
F4
C
K133
F2
R
T
F
G
V
B
U
Y
J
H
M
N
I
}
]
K
F6
O
F7
L
Bass+
+
(Num)
K107
9
PgUp
8
7
Home
Wake
Up
6
5
(Num)
4
L-Shift
Enter
(Num)
3
PgDn
2
.
Del
1
End
Space
Scroll
Lock
Bass-
Pause
VolumeKor_L
Q
W
Treble-
*
(Num)
/
(Num)
Num
Lock
Scan
|
\ (K29)
:
;
P
0
Ins
<
,
>
.
Scan
Next
R-Shift Previous Stop
Back
Space
{
[
K14
K56
APP
F8
Home
End
Page
Up
Page
Down
Insert
Sleep
Delete
Power
Down
Play/
Pause
Mute
Volume+
F12
F9
(Num)
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
F11
Enter
?
/
000
L-Alt
Euro
Key
R-Alt
Power
Down
00
.
Sleep
R-Ctrl
Wake
Up
L-WIN
Email
Caps
Lock
Media
Select
$
4
&
7
*
8
(
9
|
\(K42)
TAB
P27
#
3
%
5
^
6
+
=
"
'
WWW
Forward
*1 : RESETB can be
direct connect to VCC if
the external reset is not
used for module test.
OSCI
WWW WWW
Search Home
WWW
WWW
R-Win
Stop Refresh
_
-
)
0
Print
Treble+ Screen
L-Ctrl
F5
Bass
Boost
WWW
Backward
P12
P13
P14
P15
WWW
P16
Kor_R
Favorite
A
Esc
Z
K131
~
`
S
K45
X
K132
F1
My
Calculator Computer
F10
!
1
@
2
P17
P30
P31
P32
Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
23
NT68P81
Application Circuit 3 (Mini Keyboard)
V CC
Vcc
0.1 µ F
10 µF
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
P32
GND
LED0
Scroll Lock
LED1
Num Lock
LED2
Caps Lock
NT68P81
RESET
4.7K O
6Mhz Crystal
OSCO
E
R
U
*4
I
*5(Num)
O
*6
+
(Num)
9
PgUp
8
7
Home
Wake
Up
K14
P
* -(Num)
Scroll Lock
*Num Lock
Pause
P21
F3
4.7µF
P23
F4
P25
*FN_K3
C
K133
T
F
G
V
B
Y
J
*1 End
H
}
]
F7
F6
K
*FN_K6
*2
L
*FN_K7 *3 PgDn Bass+
K107
6
5
(Num)
4
L-Shift
Back
Space
{
[
Bass-
L-WIN
Treble-
1 . 5 KO
VCP
P24
Volume-
W
VDM
*FN_K4
Power
Down
Q
D+
To USB Cable
D-
VDP
D
*FN_K14
Kor_L
P22
WWW
Forward
TAB
Caps
Lock
Media
Select
*1 : RESETB can be
direct connect to VCC if
the external reset is not
used for module test.
OSCI
P20
P21
P22
P23
P24
P25
P26
P27
P20
*1
M
*0 Ins
<
,
> .
*. Del
N
K56
APP
P26
F2
*FN_K2
%
5
^
6
+
=
F8
*FN_K8
Enter
Scan
Home
(Num) *FN_K21 Next *FN_K22 *FN_K16
.
Page Up
3
*
Del
PgDn
(Num) (Num) *FN_K17
/
2
0
Insert
Ins
(Num) *FN_K24 *FN_K15
Delete
1
Num
Space
End
Lock *FN_K23 *FN_K18
Scan
Play/
R-Shift Previous Stop
Mute
Pause
F12
F9
|
F11
Enter *FN_K12 *FN_K9
\ (K29) *FN_K11
_
: ;
|
? /
"
\(K42) * /(Num)
* +(Num)
'
Euro
000
L-Alt
R-Alt
Treble+
Key
.
Wake
Sleep
00
R-Ctrl
L-Ctrl
Up
WWW WWW
Bass
Email Search Home
Boost
WWW
WWW
WWW
FN
R-Win
Stop Refresh Favorite
~
Z
Esc
K131
A
`
F1
K132 *FN_K1
S
K45
X
My
Calculator Computer
P27
#
3
$
4
& 7
*7 Home
* 8
*8
( 9
*9 PgUp
End
*FN_K19
Page Down
*FN_K20
Sleep
Power
Down
P00
P01
P02
P03
P04
P05
P06
P07
P10
Volume+
F10
P11
*FN_K10
) 0
* *(Num)
Print Screen
*FN_K13
F5
*FN_K5
WWW
Backward
P12
P13
P14
P15
P16
Kor_R
!
1
@
2
P17
P30
P31
P32
Notice: “Return Key” must be forced to PORT2 for remote wake up function. If not, remote wake up function will not work.
*: For FN key model usage
24
NT68P81
FN Key Model Usage for Keypad
FN+Scroll
Lock
Num Lock
FN+&
7 Home
FN+*
FN+U
4←
FN+J
1 End
FN+M
0 Ins
7
8↑
FN + (
FN+I
5(Num)
FN+K
2↓
8
9 PgUp
FN+)
FN+O
6→
FN+P
FN+L
3 PgDn
FN+:
;
+(Num)
. Del
FN+?
/
/(Num)
FN+>
9
.
0
*(Num)
-(Num)
FN Key Model Usage for Consumer Keys
FN_K1
FN+F1
WWW Backward
FN_K2
FN+F2
WWW Forward
FN_K3
FN+F3
WWW Stop
FN_K4
FN+F4
WWW Refresh
FN_K5
FN+F5
WWW Search
FN_K6
FN+F6
WWW Favorite
FN_K7
FN+F7
WWW Home
FN_K8
FN+F8
Email
FN_K9
FN+F9
My Computer
FN_K10
FN+F10
Calculator
FN_K11
FN+F11
Media Select
FN_K12
FN+F12
Mute
FN_K13
FN+Print
Screen
Bass Boost
FN_K14
FN+Pause
Sleep
FN_K15
FN+Insert
Volume+
FN_K16
FN+Home
Bass+
FN_K17
FN+Page Up
Treble+
FN_K18
FN+Delete
Volume-
FN_K19
FN+End
Bass-
FN_K20
FN+Page Down
Treble-
FN_K21
FN+ ↑
Stop
FN_K22
FN+ ←
Scan Previous Track
FN_K23
FN+ ↓
Play/Pause
FN_K24
FN+ →
Scan Next Track
25
NT68P81
Bonding Diagram
P24
P25
P26
P27
LED0
19
P05
P23
20
P06
P22
21
P07
P21
22
P10
P20
23
P11
P17
24
P12
P16
P13
P14
P15
25
18
17
26
27
NT68P81
28
29
30
(0,0)
16
P04
15
P03
14
P02
13
P01
12
P00
11
Reset B
10
P34
9
P33
8
P32
7
P31
6
P30
5470 µm
31
32
33
34
35
36
37
41
42
2
3
VCP
GND
GND
OSCO
OSCI
VCC
LED2
VCC
38
40
4
5
VDM
1
39
VDP
LED1
3400 µm
Substrate connect to VCC
Unit: µm
Pad No.
Designation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
GND
VCP
VDP
VDM
P30
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
X
264.50
424.50
734.95
1069.35
1368.85
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1443.05
1463.90
1173.90
883.90
593.90
Y
-2460.05
-2481.00
-2470.00
-2466.00
-2466.00
-2069.05
-1768.65
-1468.25
-1167.85
-867.45
-560.45
-235.35
65.05
365.45
659.85
1007.20
2545.00
2545.00
2545.00
2545.00
26
21
Pad No.
P11
Designation
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
LED2
VCC
VCC
303.90
X
2545.00
Y
-308.10
-598.10
-888.10
-1178.10
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1478.00
-1112.85
-812.45
-626.85
2545.00
2545.00
2545.00
2545.00
1012.50
670.80
370.40
70.00
-230.40
-530.80
-831.20
-1131.60
-1432.00
-1732.40
-2037.15
-2337.55
-2481.00
-2470.55
-2470.55
NT68P81
41
OSCO
-326.45
-2481.00
42
27
OSCI
-7.75
-2481.00
NT68P81
Ordering Information
Part No.
Packages
NT68P81H
CHIP FORM
NT68P81
40L DIP
Standard code functional descriptions
Code Number
Name
Reference application
circuit
NT68P81-D01012
Simple Keyboard with
PS/2 Mouse
Application circuit 1
Windows 2000
Compatible Keyboard
Application circuit 2
NT68P81-D01013
Functional Description
1. PS/2 mouse port
2. '000' and '00' keys
1. ACPI keys
2. '000', '00' and Euro keys
3. Consumer keys (Windows 2000)
NT68P81-D01014
Mini Keyboard
Application circuit 3
1. ACPI keys
2. ‘000’, ‘00’and Euro keys
3. Consumer keys (Windows 2000)
4. FN key and 40 Translated keys
28
NT68P81
Package Information
P-DIP 40L Outline Dimensions
unit: inches/mm
D
21
E1
40
1
20
E
A1
A2
Base Plane
Seating Plane
L
A
C
S
B
B1
Symbol
A
A1
A2
B
B1
C
D
E
E1
e1
L
α
eA
S
a
e1
Dimensions in inches
Dimensions in mm
0.210 Max.
5.33 Max.
0.010 Min.
0.25 Min.
0.155±0.010
3.94±0.25
0.018 +0.004
0.46 +0.10
-0.002
-0.05
0.050 +0.004
1.27 +0.10
-0.002
-0.05
0.010 +0.004
0.25 +0.10
-0.002
-0.05
2.055 Typ. (2.075 Max.) 52.20 Typ. (52.71 Max.)
0.600±0.010
15.24±0.25
0.550 Typ. (0.562 Max.) 13.97 Typ. (14.27 Max.)
0.100±0.010
2.54±0.25
0.130±0.010
3.30±0.25
0°~ 15°
0°~ 15°
0.655±0.035
0.093 Max.
16.64±0.89
2.36 Max.
Note:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
29
eA
NT68P81
Product Spec. Change Notice
NT68P81 Specification Revision History
Version
2.1
Content
Data
FN Key Model Usage for Consumer Keys
modified - FN_K22 and FN_K24 (Page
24)
Oct. 2002
2.0
Volume Knob Application deleted (Page
18)
PS/2 Mouse Application added (Page 18
and 19)
Application circuit 2 and 3 modified (Page
22 and 23)
FN key usage added (Page 24)
Standard code functional descriptions
modified (Page 26)
Sep. 2002
1.3
Application circuits modified (Page 20, 21
and 22)
Standard code functional description
added (Page 24)
July 2002
1.0
Original
Nov. 1998
30