NT6868C
Keyboard Controller
Features
n
n
n
n
n
n Mask optional for built-in RC oscillator with an
external resistor or external ceramic resonator
applied
n Mask optional for DATA/CLK driving capability
n Watch-dog timer
n Built-in power-on reset
n Built-in low voltage reset
n CMOS technology for low power consumption
n Available in 40 pin DIP package and 40 pad CHIP
FORM
Built-in 6502 8-bit CPU
2 MHz CPU operation frequency
4K bytes of ROM
128 bytes of SRAM
One 8-bit programmable base timer with 1 - 256 µsec
interval
n 29 programmable bi-directional I/O pins
n 3 LED direct sink pins with internal serial resistors
General Description
NT6868C is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base
timer.
Additionally, it includes a built-in low voltage reset, a
4MHz RC oscillator that only requires an externally
applied or a 4MHz ceramic resonator, and a watch-dog
timer that has a resistor preventing system standstill.
Pin Configuration
GND
NC
DATA
CLK
P30
P05
P06
P07
P10
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P11
20
40
39
38
37
NT6868C
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
1
2
3
4
5
Pad Configuration
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSCI
R/OSCO
V DD
LED2
LED1
P
1
7
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
26
25
24
23
22
21
20
19
18
17
16
P05
15
P04
P20
27
14
P03
LED0
P27
P26
P25
P21
28
13
P02
P22
29
12
P01
P23
30
11
P00
P24
P23
P22
P21
P24
31
10
RESET
P25
32
9
P34
P26
33
8
P33
P27
34
7
P32
LED0
35
LED1
36
6
P31
P20
P17
P16
P15
P14
P13
P12
1
NT6868CH
37
38
39
40
1
L
E
D
2
V
R
/
O
S
C
O
O
S
C
I
G
N
D
D
D
2
3
4
5
N
C
D
A
T
A
C
L
K
P
3
0
V2.0
NT6868C
Block Diagram
CLK
4K BYTES
ROM
TIMING GENERATOR
(RC OSC/Ceramic Resonator: 4MHz)
DATA
LED0
LED1
LED2
128 BYTES
SRAM + STACK
6502
CPU
I/O PORTS
P10 - P17
WATCH DOG
TIMER
INT. CONTROLLER
P00 - P07
P20 - P27
RESET
POWER-ON RESET/
LOW VOLTAGE RESET
V DD
BASE TIMER
P30 - P34
GND
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
I/O
Description
1
1
GND
P
Ground pin
2
2
NC
-
No connection, recommended to connect VDD or floating
3
3
DATA
I/O
I/O, 10KΩ pull-up resistor for communication
4
4
CLK
I/O
I/O, 10KΩ pull-up resistor for communication
5 - 9,
11 - 34
5 - 9,
11 - 34
P30 - P34,
P00 - P27
I/O
Bi-directional I/O pins
10
10
RESET
I
RESET signal input pin with internal pull-up resistor; Active low
35 - 37
35 - 37
LED0 LED2
O
LED direct sink pins
38
38
VDD
P
Power supply
39
39
R/OSCO
I
47KΩ resistor connected for RC OSC or 4MHz ceramic resonator
connection
40
40
OSCI
-
No connection for RC OSC connection; for 4MHz ceramic resonator
* Under the constraint of the maximum frequency variation, (∆F/F)max, ≤ ±1%, code 3, 7 (ceramic resonator option) must
be selected while pins 39 and 40 are connected to a ceramic resonator. If (∆F/F)max, ≤ ±10%, code 1, 5 (RC OSC option),
then it is recommended to be selected. Also, connect pin 39 a 47KΩ resistor with, ≤ ±1% accuracy to VDD while pin 40 is
floating.
2
NT6868C
Functional Description
6502 CPU
6502 is an 8-bit CPU. Please refer to 6502 data sheet for more details.
7
0
ACCUMULATOR A
0000
SRAM
7
0
009F
INDEX REGISTER X
STACK PTR
UNUSED
00C0
7
SYSTEM REGISTERS
0
00CF
INDEX REGISTER Y
15
0
UNUSED
PROGRAM COUNTER PC
7
0
S
7
S
EC00
STACK POINTER SP
0
V
B
D
I
Z
C
USER ROM
STATUS REGISTER P
FFFA
NMI-L
CARRY
FFFB
ZERO
NMI VECTOR
NMI-H
INTERRUPT MASK
FFFC
RST-L
DECIMAL MODE
FFFD
BREAK
FFFE
OVERFOLW
FFFF
RST-H
IRQ-L
IRQ VECTOR
IRQ-H
SIGN
Figure 1. 6502 CPU Registers and Status Flags
3
Figure 2. NT6868C Memory Map
NT6868C
System Reserved Registers
Address
Register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$00C0
BT
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
$00C1
TCON
-
-
-
-
-
-
-
ENBT
W
$00C2
CLRIRQX
-
-
-
-
-
-
-
CLRIRQTMR
W
$00C3
PORT0
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
RW
$00C4
PORT1
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
RW
$00C5
PORT2
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
RW
$00C6
PORT3
-
-
-
PD34
PD33
PD32
PD31
PD30
RW
$00C7
CLK
-
-
-
-
-
-
-
CLK
RW
$00C8
DATA
-
-
-
-
-
-
-
DATA
RW
$00C9
LED
-
-
-
-
-
LED2
LED1
LED0
W
$00CA
CLRWDT
0
1
0
1
0
1
0
1
W
$00CB
X
X
X
X
X
X
X
X
X
X
$00CC
X
X
X
X
X
X
X
X
X
X
$00CD
X
X
X
X
X
X
X
X
X
X
$00CE
X
X
X
X
X
X
X
X
X
X
$00CF
X
X
X
X
X
X
X
X
X
X
- : no effect
X : access not allowed
4K X 8 ROM
Power-On Reset
The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.
The built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the
150ms pulse occurs at 60% of VDD when powered on.
128 X 8 SRAM
The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. The user can allocate stack area in the
SRAM by setting the stack pointer register (S). Since
6502C’s default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.
For example :
LDX
TXS
power
VDD
60%
The start of 150ms pulse
t
#$7F
4
NT6868C
Timing Generation
This block generates the system timing and control
signal supplied to the CPU and on-chip peripherals.
There are two types of system clock sources: a built-in
RC oscillator or an external ceramic resonator. Both of
them are mask optional and generate a 4MHz system
clock. They also generate 2MHz for the CPU, and 1 MHz
for the base timer. The following shows the relationship
of code type number with oscillation type.
Oscillator
Code Number
RC OSC
1, 5
External Resistor
3, 7
The following table provides the relationship between
the external resistor and the RC OSC frequency. (This is
for reference only)
External Resistor (KΩ )
RC OSC Frequency (MHz)
39
4.7
43
4.44
47
4
56
3.68
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by the CPU. After a
reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any
time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a
timer interrupt only if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap
around and begin counting at 00H. The timer interval can be programmed from 1 - 256 µsec. The base timer can be
enabled by writing a '0' to ' ENBT ' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
8-Bit timer
1µs
BT7
BT6
BT5
BT4
BT2
BT2
BT1
TMRINT
BT0
BT Pre-loaded Data:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C0
BT
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
(W)
TCON
-
-
-
-
-
-
-
ENBT
(W)
Timer Control Register:
$00C1
INT. Controller
When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the
software. Once set by an interrupt source, it remains HIGH unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset.
When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine. When a BASE
TIMER interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by the software.
Interrupt Control Register:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C2
CLRIRQX
-
-
-
-
-
-
-
CLRIRQTMR
(W)
5
NT6868C
I/O Ports
The NT6868C has 31 pins dedicated to input and output. These pins are grouped into 6 ports as follows:
PORT 0 (P00 - P07):
Port 0 is an 8-bit bi-directional CMOS I/O port that is internally pulled HIGH by PMOS. Each pin of port 0 can be bit
programmed as an input or output pin under the software control. When programmed as output, data is latched to the port
data register and output to the pin. Port 0 pins with ''1'' written to them are pulled HIGH by the internal PMOS pull-ups, and
are used as input in that state. These input signals can then be read. The port output will be HIGH after reset.
PORT 1 ( P10 - P17 ) : These functions are the same as PORT 0.
PORT 2 ( P20 - P27)
: These functions s are the same as PORT 0.
PORT 3 ( P30 - P34)
: These functions are the same as PORT 0.
CLK & DATA
: These two pins have the same structure as I/O ports.
PORT Registers:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C3
PORT0
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
(RW)
$00C4
PORT1
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD10
(RW)
$00C5
PORT2
PD27
PD26
PD25
PD24
PD23
PD22
PD21
PD20
(RW)
$00C6
PORT3
-
-
-
PD34
PD33
PD32
PD31
PD30
(RW)
$00C7
CLK
-
-
-
-
-
-
-
CLK
(RW)
$00C8
DATA
-
-
-
-
-
-
-
DATA
(RW)
V DD
Latch
WREN
Weak PMOS
L
IO
Q
DB
D
SD
RST
RDENB
IO Port Structure
6
NT6868C
LED Port
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C9
LED
-
-
-
-
-
LED2
LED1
LED0
(W)
V DD
LED [ 0 ]
WREN
WREN
L
L
LED [ 1:2 ]
Q
Q
DB
DB
D
D
SD
RST
SD
RST
LED0 Port Structure
LED1, LED2 Port Structures
Watch-Dog Timer
NT6868C implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must
be cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by the software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00CA
CLRWDT
0
1
0
1
0
1
0
1
(W)
Low Voltage Reset (LVR) Circuit
The NT6868C will check on the voltage level of the power supply. When the voltage level of power supply is below a
threshold of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above a threshold
voltage of 3.0V (Typical) again. As soon as the power voltage reaches 3.0V (Typical), the entire chip will be reset for about
150ms.
RESET
NT6868C can also be externally reset through the RESET pin. A reset is initiated when the signal at the RESET pin is
held LOW for at least 10 system clocks. As soon as the RESET signal goes high, the NT6868C begins to reset for about
150ms. The following shows the definition of the RESET input at LOW pulse width.
V DD
VDD
20%VDD
20%VDD
Trstb
7
NT6868C
Absolute Maximum Ratings*
*Comments
DC Supply Voltage . . . . . . . . . . . . . . -0.3V to +7.0V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
Input/Output Voltage . . . . . . GND -0.2V to VD D + 0.2V
Operating Ambient Temperature . . . . . . 0 ° C to +70°C
Storage Temperature . . . . . . . . . . . . . -55°C to +125°C
Operating Voltage (VD D ) . . . . . . . . . .+4.5V to 5.5V
DC Electrical Characteristics (VDD = 5V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified)
Symbol
Parameter
ICC
Power Supply Current
VIH
Input High Voltage
VIL
Input Low Voltage
Min.
Typ.
Max.
Unit
20
mA
2
Conditions
No load
V
0.8
V
VOH1
Output High Voltage (Port 0, 1, 2, 3)
2.4
V
IOH = -100µA
VOH2
Output High Voltage (CLK, DATA)
2.4
V
IOH = -400µA, Note 1
VOH3
Output High Voltage (CLK, DATA)
2.4
V
IOH = -800µA, Note 2
VOL1
Output Low Voltage (PORT 0, 1, 2)
0.4
V
IOL = 4mA
VOL2
Output Low Voltage (PORT 3)
0.4
V
IOL = 5mA
VOL3
Output Low Voltage (CLK, DATA)
0.4
V
IOL = 10mA
∆F/F
Initial Frequency Variation 1
+/-10
%
For RC OSC option
only; By Lots
∆F/F
Frequency Variation 2
+/-1
%
For ceramic resonator
option only; By Lots
ILED
LED Sink Current (LED 0, 1, 2)
17
mA
VOL = 3.2V
VLVR
Low Voltage Reset Threshold
TPOR
Power-on Reset Time
120
TRSTB
RESET Input Low Pulse Width
2.5
RPH
10
14
3.0
150
V
180
ms
µs
220
RESET Pull High Resistor
10 system clocks
KΩ
Note 1: There are 2 types of DATA/CLK driving capabilities. This condition of VOH2 is the same as the specification of
NT6868A. Under this condition, the user can select mask option 1 or 3.
Note 2: The driving capability of DATA/CLK is higher than V OH2. Under this condition, the user can select mask option 5 or
7.
8
NT6868C
Application Circuit I (for reference only)
V DD
4.7 - 10 mf
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
V DD
V DD
GND
Scroll Lock
LED0
Num Lock
LED1
Caps Lock
LED2
0.1mf
RESET
Optional
NT6868C
DATA
KBD DATA
CLK
P20
P21
P22
P23
P24
P25
P26
P27
R0
S0
R1
R/OSCO
47K (System clock can be decreased
by increasing the resistance)
R2
R3
R4
Pause
R7
(L)
Ctrl
F5
!
1
Esc
Z
K131
Caps
Lock
S
(K45)
Macro
X
K132
F1
@
2
E
F3
D
F4
C
K133
F2
#
3
R
T
F
G
V
B
%
5
$
4
&
7
S2
W
S3
S4
Tab
U
Y
I
}
]
J
K
S7
O
F7
L
S8
P
{
[
:
;
S9
Scroll
Lock
H
M
N
^
6
F6
<
,
K56
+
=
*
8
>
.
APP
F8
(
9
|
\(K42)
?
/
-
)
0
"
'
(L)
Alt
(R)
Alt
S10
K14
Back
Space
|
\(K29)
4
S11
7
Home
1
End
Space
Num
Lock
8
5
2
0
Ins
/
9
6
3
.
PgDn
Del
S12
S13
R6
A
Q
S6
R5
(R)
Ctrl
~
,
S1
S5
KBD CLOCK
VDD
PgUp
F11
Enter
F12
Print
Screen
F9
F10
Delete
Insert
*
-
Page
Up
Page
Down
Home
End
(R)
S14
+
K107
(L)
Enter
(R)
S15
Shift
Shift
S16
WINL
S17
WINR
9
NT6868C
Application Circuit II (for reference only)
V DD
4.7 - 10µf
V DD
P00
V DD
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30 NT6868C
P31
GND
Scroll Lock
LED0
Num Lock
LED1
Caps Lock
LED2
0.1µf
RESET
Optional
KBD
DATA
DATA
KBD
CLOCK
CLK
P20
P21
P22
P23
P24
P25
P26
P27
R0
S0
R1
R2
R/OSCO
OSCI
R3
R4
Q
S2
W
S3
R5
R6
(R)
Ctrl
Pause
S1
4MHz
Ceramic Resonator
R7
(L)
Ctrl
~
,
F5
!
1
A
Esc
Z
K131
Caps
Lock
S
(K45)
Macro
X
K132
E
F3
D
F4
C
K133
F2
#
3
S4
R
T
F
G
V
B
%
5
$
4
S5
U
Y
J
H
M
N
^
6
&
7
S6
I
}
]
K
F6
<
,
K56
+
=
*
8
>
.
APP
F8
(
9
\(K42)
?
/
-
)
0
Tab
S7
O
F7
L
S8
P
{
[
:
;
S9
Scroll
Lock
S10
K14
4
S11
7
Home
1
End
8
5
2
6
3
PgDn
S13
9
PgUp
|
(L)
Alt
Back
Space
S12
"
'
F1
(R)
Alt
@
2
Print
Screen
|
\(K29)
F11
Enter
Space
0
Ins
F12
Num
Lock
F10
Delete
/
Insert
.
Del
F9
*
-
Page
Up
Page
Down
Home
End
(R)
S14
+
S15
K107
(L)
Shift
S16
WINL
S17
Enter
(R)
Shift
WINR
10
NT6868C
Application Circuit For Windows 2000 Standard Code
47K
S0
P15
S1
P30
S2
P31
S3
P00
S4
P01
S5
P02
S6
P03
S7
P04
S8
P13
S9
P14
S10
P12
S11
P10
S12
P07
S13
P06
S14
P05
S15
P11
S16
P16
S17
P17
S18
P32
R0
P20
R1
P21
R2
P22
R3
P23
R4
P24
R5
P25
R6
P26
R7
P27
R_OSC
Scroll Lock
LED 0
.1uF
Num Lock
LED 1
Caps Lock
LED 2
NT6868A/C
VDD
VDD
10uF
GND
GND
DATA
DATA
CLOCK
CLOCK
RESET
10
0.1uF
11
NT6868C
Key Matrix definition for Windows 2000 Standard Code
Power
Pause
126
Sleep
163
R-Ctrl
164
64
Wake Up
165
L-Ctrl
58
F5
116
S0
Q
Tab
17
A
16
W
31
Caps Lock
18
19
114
R
20
F
21
U
23
J
22
I
28
O
K
27
40
56
,
54
:
[
(K56)
"
41
;
Scroll Lock
162
|
42
'
?
55
\
L-Alt
125
7
8
9
8
12
-
S5
S6
(
_
/
S4
*
10
R-Alt
60
4
F8
119
S3
&
=
App
.
5
+
13
S2
$
6
7
>
39
{
26
53
L
118
P
117
3
^
51
<
4
5
N
52
F6
38
]
F7
25
36
2
%
6
S1
#
113
50
M
3
F2
B
49
H
37
}
24
35
1
@
112
133
V
2
F1
(K133)
48
G
34
Y
C
115
1
132
!
~
`
(K132)
47
F4
33
T
131
X
45
D
(K131)
46
(K45)
32
F3
Z
110
S
30
E
Esc
9
S7
)
11
0
S8
Print
124Screen
62
S9
(K14)
Back Space
14
15
|
29
7
F11
\ (101) 122
4
91 (Home)
92
(
1
)
93
Enter
43
123
F9
120
F10
121
S10
Space
(End)
F12
Num Lock
61
90
Delete
84
76
Power
163
S11
8
96
(
5
)
97
2
(Num)
98
(
0
)
99
/
(Ins)
95
(Num)
Insert
89
75
Sleep
164
S12
9
101 (Page Up)
6
102 (
3
)
103 (Page Dn)
.
104
(Del)
*
100 (Num)
105 (Num)
Page Up
85
Page Down
86
S13
+
106 (Num)
(K107)
107
Wake Up
165
Enter
108 (Num)
L-Shift
44
R-Shift
57
83
Media
180 Next
Home
79
End
80
81
Media Mute
Volume +
S14
Media
Previous
181
182
WWW
Search
188
WWW
Home
189
Media Stop
Media Play
183
184
185
S15
L-Win
Volume 186
Kor_L
134
160
WWW
Forward
191
Media
Select
195
WWW Mail
187
R-Win
WWW Stop
161
192
Calculator
My
Computer
197
196
WWW
Refresh
193
WWW Back
190
WWW
Bookmark
194
S16
Kor_R
135
S17
S18
R7
R6
R5
R4
R3
R2
R1
R0
12
NT6868C
Bonding Diagram
P
1
7
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
26
25
24
23
22
21
20
19
18
17
16
P05
15
P04
P20
27
NT6868CH
14
P03
P21
28
Y
13
P02
P22
29
12
P01
P23
30
11
P00
P24
31
10
RESET
P25
32
9
P34
P26
33
8
P33
P27
34
7
P32
LED0
35
LED1
36
6
P31
(0, 0)
X
37
38
39
40
1
L
E
D
2
V
R
/
O
S
C
O
O
S
C
I
G
N
D
D
D
2
3
4
5
N
C
D
A
T
A
C
L
K
P
3
0
1752.6 µm
1930.4 µm
*Substrate Connect to Gnd
unit: µm
Pad No.
Designation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
GND
NC
DATA
CLK
P30
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
X
-26.70
103.30
233.30
497.55
623.30
752.55
765.20
765.20
765.20
765.20
765.20
765.20
765.20
765.20
765.20
765.20
537.50
407.50
277.50
147.50
Y
-680.90
-743.05
-735.35
-743.05
-735.35
-735.95
-447.35
-317.35
-187.35
-57.35
72.65
202.65
332.65
462.65
592.65
735.15
734.15
734.15
734.15
734.15
13
Pad No.
Designation
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
LED0
LED1
LED2
VDD
R/OSCO
OSCI
X
17.50
-112.50
-242.50
-372.50
-502.50
-645.00
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-546.70
-416.70
-286.70
-156.70
Y
734.15
734.15
734.15
734.15
734.15
734.15
576.30
434.30
304.30
174.15
44.00
-86.00
-216.00
-346.00
-476.00
-622.10
-632.30
-617.30
-617.30
-617.30
NT6868C
Ordering Information
Part No.
NT6868CH
NT6868C
Package
CHIP FORM
40L DIP
Code Type No.
Oscillation Type
1XXXX
Built-in RC OSC
V OH2
3XXXX
Ceramic Resonator
V OH2
5XXXX
Built-in RC OSC
V OH3
7XXXX
Ceramic Resonator
V OH3
14
Data/Clk Driving capacitance
NT6868C
Package Information
DIP 40L Outline Dimensions
unit: inches/mm
D
21
E1
40
1
20
E
A1
A2
Base Plane
Seating Plane
L
A
C
S
B
B1
α
e1
Symbol
Dimensions in inches
Dimensions in mm
A
0.210 Max.
5.33 Max.
A1
0.010 Min.
0.25 Min.
A2
0.155±0.010
3.94±0.25
B
0.018 +0.004
-0.002
0.46 +0.10
-0.05
B1
0.050 +0.004
-0.002
1.27 +0.10
-0.05
C
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
2.055 Typ. (2.075 Max.)
52.20 Typ. (52.71 Max.)
E
0.600±0.010
15.24±0.25
E1
0.550 Typ. (0.562 Max.)
13.97 Typ. (14.27 Max.)
e1
0.100±0.010
2.54±0.25
L
0.130±0.010
3.30±0.25
α
0° ~ 15°
0° ~ 15°
eA
0.655±0.035
16.64±0.89
S
0.093 Max.
2.36 Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E 1 does not include resin fins.
3. Dimension S includes end flash.
15
eA