TI OP07CDR

 SLOS099E − OCTOBER 1983 − REVISED MAY 2004
D Low Noise
D No External Components Required
D Replace Chopper Amplifiers at a Lower
D
D
D OR P PACKAGE
(TOP VIEW)
OFFSET N1
IN−
IN+
VCC−
Cost
Wide Input-Voltage Range
. . . 0 to ±14 V Typ
Wide Supply-Voltage Range
. . . ±3 V to ±18 V
1
8
2
7
3
6
4
5
OFFSET N2
VCC+
OUT
NC
NC −No internal connection
description/ordering information
These devices offer low offset and long-term stability by means of a low-noise, chopperless,
bipolar-input-transistor amplifier circuit. For most applications, external components are not required for offset
nulling and frequency compensation. The true differential input, with a wide input-voltage range and outstanding
common-mode rejection, provides maximum flexibility and performance in high-noise environments and in
noninverting applications. Low bias currents and extremely high input impedances are maintained over the
entire temperature range. The OP07 is unsurpassed for low-noise, high-accuracy amplification of very-low-level
signals.
These devices are characterized for operation from 0°C to 70°C.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
PDIP (P)
0°C to 70°C
SOIC (D)
TOP-SIDE
MARKING
Tube of 50
OP07CP
OP07CP
Tube of 50
OP07DP
OP07DP
Tube of 75
OP07CD
Reel of 2500
OP07CDR
Tube of 75
OP07DD
Reel of 2500
OP07DDR
OP07C
OP07D
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
symbol
OFFSET N1
IN+
IN−
OFFSET N2
1
3
2
+
6
OUT
−
8
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004, Texas Instruments Incorporated
!" #$
# % & ## '($ # ) # "( "#
) "" $
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1
SLOS099E − OCTOBER 1983 − REVISED MAY 2004
schematic
7
OFFSET N1
OFFSET N2
1
8
6
IN+
IN−
VCC+
OUT
3
2
COMPONENT COUNT
Resistors
Transistors
Capacitors
28
39
4
4
VCC−
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage: VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 V
VCC− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −22 V
Differential input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input voltage, VI (either input, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V
Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Package thermal impedance, θJA (see Notes 5 and 6): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC− .
2. Differential voltages are at IN+ with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either power supply.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SLOS099E − OCTOBER 1983 − REVISED MAY 2004
recommended operating conditions
VCC±
VIC
Supply voltage
TA
Operating free-air temperature
VCC± = ±15 V
Common-mode input voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
UNIT
V
±3
±18
−13
13
V
0
70
°C
3
4
8
100
25°C
25°C
25°C
Peak output voltage
Large-signal differential voltage amplification
Unity-gain bandwidth
Input resistance
Common-mode rejection ratio
Supply-voltage sensitivity (∆VIO/∆VCC)
Power dissipation
VOM
AVD
B1
ri
CMRR
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
kSVS
PD
RS = 50 Ω
RL = 2 kΩ
25°C
0°C to 70°C
25°C
0°C to 70°C
0°C to 70°C
25°C
97
0.4
100
120
100
4
80
10
7
120
120
33
0.6
400
400
400
8
150
51
32
50
±13
94
94
7
0.4
100
120
± 11
±11.5
±12
±13
4
80
10
7
106
110
31
0.6
400
400
400
±12.6
±12
±12.8
±13
±13.5
±14
18
±3
±2
12
1.6
8
150
51
32
50
± 14
± 12
50
8
6
2.5
250
150
MAX
mW
µV/V
V/V
dB
MΩ
MHz
V/mV
V
V
pA/°C
nA
pA/°C
nA
mV
µV/mo
µV/°C
µV
V
UNIT
† All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise noted.
NOTE 7: Since long-term drift cannot be measured on the individual devices prior to shipment, this specification is not intended to be a warranty. It is an engineering estimate of the
averaged trend line of drift versus time over extended periods after the first 30 days of operation.
VO = 0,
No load
VCC± = ±3 V, VO = 0,
No load
VCC± = ±3 V to ±18 V,
RS = 50 Ω
VIC = ±13 V,
VO = ±10 V,
25°C
±12.6
±11
RL ≥ 2 kΩ
VCC ± = ±3 V, VO = ±0.5 V,
RL ≥ 500 kΩ
±12
0°C to 70°C
±13
±12.8
RL ≥ 1 kΩ
±12
±11.5
RL ≥ 2 kΩ
25°C
25
C
RL ≥ 10 kΩ
±13.5
±13
0°C to 70°C
Common-mode input voltge range
VICR
±14
±13
25°C
18
±9
±2.2
0°C to 70°C
0°C to 70°C
50
±7
12
±1.8
8
25°C
1.6
0°C to 70°C
0°C to 70°C
±4
0.8
±4
0.8
0.7
85
60
TYP
OP07D
25°C
6
MIN
25°C
1.8
250
150
MAX
0.5
0.5
85
60
TYP
OP07C
0.4
0°C to 70°C
0°C to 70°C
25°C
MIN
Temperature coefficient of input bias current
Input bias current
IIB
See Figure 1
RS = 50 Ω
RS = 50 Ω
TA
a I IB
Temperature coefficient of input offset current
a I IO
RS = 20 kΩ,
Offset adjustment range
Input offset current
See Note 6
Long-term drift of input offset voltage
IIO
VO = 0,
Temperature coefficient of input offset voltage
a V IO
VO = 0,
Input offset voltage
TEST CONDITIONS†
VIO
PARAMETER
electrical characteristics at specified free-air temperature, VCC± = ±15 V (unless otherwise noted)
*+
*
*
SLOS099E − OCTOBER 1983 − REVISED MAY 2004
SLOS099E − OCTOBER 1983 − REVISED MAY 2004
operating characteristics, VCC± = ±15 V, TA = 25°C
OP07C
OP07D
TYP
TYP
f = 10 Hz
10.5
10.5
f = 100 Hz
10.2
10.3
TEST
CONDITIONS†
PARAMETER
Vn
Equivalent input noise voltage
9.8
9.8
VN(PP)
Peak-to-peak equivalent input noise voltage
f = 0.1 Hz to 10 Hz
0.38
0.38
f = 10 Hz
0.35
0.35
In
Equivalent input noise current
f = 100 Hz
0.15
0.15
f = 1 kHz
0.13
0.13
IN(PP)
Peak-to-peak equivalent input noise current
15
15
f = 1 kHz
f = 0.1 Hz to 10 Hz
SR
Slew rate
RL ≥ 2 kΩ
0.3
0.3
† All characteristics are measured under open-loop conditions, with zero common-mode input voltage, unless otherwise noted.
UNIT
nV/√Hz
µV
pA/√Hz
pA
V/µs
APPLICATION INFORMATION
20 kΩ
VCC+
OFFSET N1
1
IN+
IN−
3
2
OFFSET
N2
8
+
7
6
OUT
−
4
VCC−
Figure 1. Input Offset-Voltage Null Circuit
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5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OP-07DPSR
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP-07DPSRE4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
OP07CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
OP07DD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07DDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07DDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07DDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OP07DP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
OP07DPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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