INTEGRATED CIRCUITS DATA SHEET PCA3354C; PCD3354A 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM Product specification Supersedes data of 1996 May 09 File under Integrated Circuits, IC03 1996 Dec 18 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION 5.1 5.2 Pinning Pin description 6 FREQUENCY GENERATOR 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Frequency generator derivative registers Melody output (P1.7/MDY) DTMF clock divider and output (DP1.7/DCO) Frequency registers DTMF frequencies Modem frequencies Musical scale frequencies 7 EEPROM AND TIMER 2 ORGANIZATION 7.1 7.2 7.3 7.4 7.5 7.6 EEPROM registers EEPROM latches EEPROM flags EEPROM macros EEPROM access Timer 2 8 DERIVATIVE INTERRUPTS 9 TIMING 10 RESET 11 IDLE MODE 12 STOP MODE 13 SUMMARY OF I/O PORTS AND MASK OPTIONS 14 SUMMARY OF DERIVATIVE REGISTERS 15 HANDLING 16 LIMITING VALUES 17 DC CHARACTERISTICS 18 AC CHARACTERISTICS 19 PACKAGE OUTLINES 20 SOLDERING 20.1 20.2 20.3 20.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 21 DEFINITIONS 22 LIFE SUPPORT APPLICATIONS 1996 Dec 18 2 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 1 PCA3354C; PCD3354A FEATURES 2 • 8-bit CPU, ROM, RAM, EEPROM and I/O; all in a 44-lead quad flat package GENERAL DESCRIPTION This data sheet details the specific properties of the PCA3354C and PCD3354A. The shared properties of the PCD33xxA family of microcontrollers are described in the “PCD33xxA family” data sheet, which should be read in conjunction with this publication. • 8 kbytes ROM; 256 bytes RAM • 256 bytes Electrically Erasable Programmable Read Only Memory (EEPROM) The PCA3354C and PCD3354A are microcontrollers oriented towards telephony applications. They include 8 kbytes ROM, 256 bytes RAM, 36 I/O lines, and an on-chip generator for dual tone multifrequency (DTMF), modem and musical tones. In addition to dialling, the generated frequencies can be made available as square waves for melody generation, providing ringer operation. • Over 100 instructions (based on MAB8048) all of 1 or 2 cycles • 36 quasi-bidirectional I/O port lines • 8-bit programmable Timer/event counter 1 • 8-bit reloadable Timer 2 • Three single-level vectored interrupts: The PCA3354C and PCD3354A also incorporate 256 bytes of EEPROM, permitting data storage without battery backup. The EEPROM can be used for storing telephone numbers, particularly for implementing redial functions. – external – 8-bit programmable Timer/event counter 1 – derivative; triggered by reloadable Timer 2 • Two test inputs, one of which also serves as the external interrupt input • DTMF, modem, musical tone generator The differences between PCA3354C and PCD3354A are shown in Table 1. • Reference for supply and temperature-independent tone output The instruction set is similar to the MAB8048 and is a sub-set of that listed in the “PCD33xxA family” data sheet. • Filtering for low output distortion (CEPT compatible) Table 1 • Melody output for ringer application • Programmable DTMF clock divider Differences: PCA3354C and PCD3354A TYPE • Power-on-reset VPOR AMBIENT TEMP. RANGE • Stop and Idle modes PCA3354C fixed at 2.0 V ±0.3 V 0 to 50 °C • Supply voltage: 1.8 to 6 V (DTMF tone output and EEPROM erase/write from 2.5 V) PCD3354A (1.2 to 3.6 V) ±0.5 V(1) −25 to +70 °C Note • CPU clock frequency: 1 to 16 MHz (3.58 MHz or 10.74 MHz for DTMF) 1. See Chapter 13, Table 24. • Operating ambient temperature: – −25 to +70 °C (PCD3354A) – 0 to 50 °C (PCA3354C) • Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION (see note 1) PACKAGE TYPE NUMBER NAME PCA3354CH PCD3354AH QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 × 14 × 2.2 mm VERSION SOT205-1 Note 1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and the ROM mask options. 1996 Dec 18 3 1996 Dec 18 4 TIMER 2 REGISTER TIMER 2 RELOAD REGISTER RESET POWER-ON-RESET 8 4 PORT 2 BUFFER 8 PORT 2 FLIP-FLOP VPOR EEPROM ADDRESS REGISTER EEPROM CONTROL REGISTER EEPROM 256 bytes 8 8 LGF REGISTER 8 8 HGF REGISTER SINE WAVE GENERATOR FILTER TONE DTMF-CLOCK & MELODY CONTROL REGISTER 8 8 INTERRUPT LOGIC derivative interrupt EEPROM DATA TRANSFER 8 8 8 INTERRUPT CE/T0 INITIALIZE RESET XTAL2 DECIMAL ADJUST LOGIC UNIT OSCILLATOR XTAL1 8 TIMER/ EVENT COUNTER MEMORY BANK FLIP-FLOPS ARITHMETIC CONTROL AND TIMING TEMPORARY REGISTER 2 TEMPORARY REGISTER 1 8 T1 32 INTERNAL CLOCK FREQ. 30 PCA3354C PCD3354A Fig.1 Block diagram. IDLE STOP external interrupt timer interrupt 8 8 PORT 1 BUFFER 8 P1.0 to P1.7/MDY PORT 1 FLIP-FLOP ACCUMULATOR DER. PORT 1 BUFFER DER. PORT 1 FLIP-FLOP fDTMF 8 DP1.0 to DP1.7/DCO 8 5 8 8 LOWER PROGRAM COUNTER LOGIC BRANCH CONDITIONAL INSTRUCTION REGISTER AND DECODER HIGHER PROGRAM COUNTER DECODE RESIDENT ROM 8 kbytes 8 ACC BIT TEST ACC CARRY TIMER FLAG CE/T0 T1 RAM ADDRESS REGISTER 8 8 PROGRAM STATUS WORD PORT 0 FLIP-FLOP D E C O D E REGISTER 0 REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 MULTIPLEXER 8 DER. PORT 0 FLIP-FLOP MED265 RESIDENT RAM ARRAY 256 bytes DATA STORE OPTIONAL SECOND REGISTER BANK 8 DER. PORT 0 BUFFER 8 DP0.0 to DP0.7 8 LEVEL STACK (VARIABLE LENGTH) 8 PORT 0 BUFFER 8 P0.0 to P0.7 4 4 P2.0 to P2.3 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM handbook, full pagewidth Philips Semiconductors Product specification PCA3354C; PCD3354A BLOCK DIAGRAM Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 34 P1.1 P2.1 1 33 P1.0 P2.2 2 32 P0.7 P2.3 3 31 P0.6 DP0.0 4 30 P0.5 DP0.1 5 DP0.2 6 DP0.3 7 DP0.4 8 26 P0.3 DP0.5 9 25 P0.2 DP0.6 10 24 P0.1 DP0.7 11 23 P0.0 29 P0.4 28 XTAL2 5 DP1.7/DCO 22 DP1.5 20 DP1.6 21 27 XTAL1 DP1.4 19 DP1.3 18 DP1.2 17 DP1.0 15 DP1.1 16 RESET 14 CE/T0 12 PCA3354CH PCD3354AH Fig.2 Pin configuration. 1996 Dec 18 35 P1.2 36 VSS 37 TONE 38 VDD 39 P1.3 40 P1.4 41 P1.5 44 P2.0 handbook, full pagewidth 42 P1.6 Pinning 43 P1.7/MDY 5.1 PINNING INFORMATION T1 13 5 PCA3354C; PCD3354A MED266 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 5.2 PCA3354C; PCD3354A Pin description Table 2 SOT205-1 package (for information on parallel I/O ports, see Chapter 13) SYMBOL PIN TYPE DESCRIPTION P2.1 to P2.3 1 to 3 I/O 3 bits of Port 2: 4-bit quasi-bidirectional I/O port DP0.0 to DP0.7 Derivative Port 0: 8-bit quasi-bidirectional I/O port 4 to 11 I/O CE/T0 12 I Chip Enable or Test 0 input T1 13 I Test 1/count input of 8-bit Timer/event counter 1 RESET 14 I reset input DP1.0 to DP1.6 15 to 21 I/O 7 bits of Derivative Port 1: 8-bit quasi-bidirectional I/O port DP1.7/DCO 22 I/O 1 bit of Derivative Port 1: 8-bit quasi-bidirectional I/O port; or DTMF clock output P0.0 to P0.3 23 to 26 I/O 4 bits of Port 0: 8-bit quasi-bidirectional I/O port XTAL1 27 I crystal oscillator/external clock input XTAL2 28 O crystal oscillator output P0.4 to P0.7 29 to 32 I/O 4 bits of Port 0: 8-bit quasi-bidirectional I/O port P1.0 to P1.2 3 bits of Port 1: 8-bit quasi-bidirectional I/O port 33 to 35 I/O VSS 36 P ground TONE 37 O DTMF output 38 P 39 to 42 I/O 4 bits of Port 1: 8-bit quasi-bidirectional I/O port P1.7/MDY 43 I/O 1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output P2.0 44 I/O 1 bit of Port 2: 4-bit quasi-bidirectional I/O port VDD P1.3 to P1.6 1996 Dec 18 positive supply voltage 6 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 6 PCA3354C; PCD3354A The TONE output can alternatively issue twelve modem frequencies for data rates between 300 and 1200 bits/s. FREQUENCY GENERATOR A versatile frequency generator section with built-in programmable clock divider is provided (see Fig.3). The clock divider allows the DTMF section to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 1⁄3 × fxtal) depending on the state of the divider control bit DIV3 (see Table 5). The frequency generator includes precision circuitry for dual tone multifrequency (DTMF) signals, which is typically used for tone dialling telephone sets. 6.1 In addition to DTMF and modem frequencies, two octaves of musical scale in steps of semitones are available. Their frequencies are provided either in purely sinusoidal form on the TONE output or as a square wave on the port line P1.7/MDY. The latter is typically for ringer applications in telephone sets. If no frequency output is selected the TONE output is in 3-state mode. Frequency generator derivative registers 6.1.1 HIGH AND LOW GROUP FREQUENCY REGISTERS Table 3 gives the addresses, symbols and access types of the High Group Frequency (HGF) and Low Group Frequency (LGF) registers, used to set the frequency output. Table 3 Hexadecimal addresses, symbols, access types and bit symbols of the frequency registers BIT SYMBOLS REGISTER ADDRESS REGISTER SYMBOL ACCESS TYPE 7 6 5 4 3 2 1 0 11H HGF W H7 H6 H5 H4 H3 H2 H1 H0 12H LGF W L7 L6 L5 L4 L3 L2 L1 L0 6.1.2 CLOCK AND MELODY CONTROL REGISTER (MDYCON) Table 4 Clock and Melody Control Register, MDYCON (address 13H; access type R/W) 7 6 5 4 3 2 1 0 0 0 0 0 0 EDCO DIV3 EMO Table 5 Description of MDYCON bits BIT SYMBOL DESCRIPTION 7 to 3 − 2 EDCO 1 DIV3 Enable DTMF clock divider. If bit DIV3 = 0, then the DTMF clock fDTMF = fxtal. If bit DIV3 = 1, then fDTMF = 1⁄3 × fxtal. 0 EMO Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line. If bit EMO = 1, then P1.7/MDY is the melody output. EMO = 1 does not inhibit the port instructions for P1.7/MDY. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY must remain set to avoid conflicts between melody and port outputs. When the HGF contents are zero while EMO = 1, P1.7/MDY is in the HIGH state. 1996 Dec 18 These bits are set to a logic 0. Enable DTMF clock output. If bit EDCO = 0, then DP1.7/DCO is a general purpose derivative port line. If bit EDCO = 1, then DP1.7/DCO is the DTMF clock output. EDCO = 1 does not inhibit the port instructions for DP1.7/DCO. Therefore the state of both port line and flip-flop may be read in and the port flip-flop may be written by derivative port instructions. However, the port flip-flop of DP1.7/DCO must remain set to avoid conflicts between DTMF clock and port outputs. 7 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM handbook, full pagewidth 8 fxtal PCA3354C; PCD3354A fDTMF CLOCK DIVIDER CLOCK AND MELODY CONTROL REGISTER square wave 8 HGF REGISTER PORT/CLOCK OUTPUT LOGIC DP1.7/ DCO PORT/MELODY OUTPUT LOGIC P1.7/ MDY RC LOW-PASS FILTER TONE DIGITAL SINE WAVE SYNTHESIZER DAC 8 INTERNAL BUS SWITCHED CAPACITOR BANDGAP VOLTAGE REFERENCE SWITCHED CAPACITOR LOW-PASS FILTER MGB782 DAC 8 LGF REGISTER DIGITAL SINE WAVE SYNTHESIZER Fig.3 Block diagram of the frequency generator, melody output (P1.7/MDY) and DTMF clock output (DP1.7/DCO). 6.2 Melody output (P1.7/MDY) 6.3 The melody output (P1.7/MDY) is very useful for generating musical notes when a purely sinusoidal signal is not required, such as for ringer applications. The DTMF clock divider allows the DTMF part to run either with the main clock frequency (fDTMF = fxtal) or with a third of it (fDTMF = 1⁄3 × fxtal) depending on the state of the divider control bit DIV3 in register MDYCON. The square wave (duty cycle = 12⁄23 or 52%) will include the attenuated harmonics of the base frequency, which is defined by the contents of the HGF register (Table 3). However, even higher frequency notes may be produced since the low-pass filtering on the TONE output is not applied to the P1.7/MDY output. This results in the minimum decimal value x in the HGF register (see equation in Section 6.4) being 2 for the P1.7/MDY output, rather than 60 for the TONE output. A sinusoidal TONE output is produced at the same time as the melody square wave, but due to the filtering, the higher frequency sine waves with x < 60 will not appear at the TONE output. For low power applications, a 3.58 MHz quartz crystal or PXE resonator can be chosen together with the divide-by-one function of the clock divider. For other applications a 10.74 MHz quartz crystal or PXE resonator may be chosen together with the divide-by-three function of the clock divider. This triples the program speed of the microcontroller, thereby keeping the assumed DTMF frequency of 3.58 MHz. Since a 3.58 MHz clock is needed for peripheral telephony circuits such as the analog voice scrambler/descrambler PCD4440T, a switchable DTMF clock output is provided depending on the state of the enable clock output bit EDCO in register MDYCON. Since the melody output is shared with P1.7, the port flip-flop of P1.7 has to be set HIGH before using the melody output. This is to avoid conflicts between melody and port outputs. The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 13, Table 24. 1996 Dec 18 DTMF clock divider and output (DP1.7/DCO) 8 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A Table 6 If EDCO = 1 and DIV3 = 1 in the MDYCON register: a square wave with the frequency fDTMF = 1⁄3 × fxtal is output on the derivative port line DP1.7/DCO. If EDCO = 1 and DIV3 = 0: a square wave with the frequency fDTMF = fxtal is output on the derivative port line DP1.7/DCO. VALUE (HEX) DTMF standard frequencies and their implementation; value = LGF, HGF contents FREQUENCY (Hz) STANDARD DEVIATION GENERATED (%) (Hz) DD 697 697.90 0.13 0.90 The melody output drive depends on the configuration of port P1.7/MDY, see Chapter 13, Table 24. C8 770 770.46 0.06 0.46 B5 852 850.45 −0.18 −1.55 6.4 A3 941 943.23 0.24 2.23 7F 1209 1206.45 −0.21 −2.55 72 1336 1341.66 0.42 5.66 67 1477 1482.21 0.35 5.21 5D 1633 1638.24 0.32 5.24 Frequency registers The two frequency registers HGF and LGF define two frequencies. From these, the digital sine synthesizers together with the Digital-to-Analog Converters (DACs) construct two sine waves. Their amplitudes are precisely scaled according to the bandgap voltage reference. This ensures tone output levels independent of supply voltage and temperature. The amplitude of the Low Group Frequency sine wave is attenuated by 2 dB compared to the amplitude of the High Group Frequency sine wave. Table 7 TELEPHONE DTMF FREQ. KEYBOARD PAIRS SYMBOLS (Hz) The two sine waves are summed and then filtered by an on-chip switched capacitor and RC low-pass filters. These guarantee that all DTMF tones generated fulfil the CEPT recommendations with respect to amplitude, frequency deviation, total harmonic distortion and suppression of unwanted frequency components. The value 00H in a frequency register stops the corresponding digital sine synthesizer. If both frequency registers contain 00H, the whole frequency generator is shut off, resulting in lower power consumption. The frequency ‘f’ of the sine wave generated from either of the frequency registers is a function of the clock frequency ‘fxtal’ and the decimal value ‘x’ held in the register. The equation relating these variables is: f xtal f = --------------------------------; where 60 ≤ x ≤ 255. [ 23 ( x + 2 ) ] The frequency limitation given by x ≥ 60 is due to the low-pass filters which would attenuate higher frequency sine waves. 6.5 DTMF frequencies Assuming an oscillator frequency fxtal = 3.58 MHz, the DTMF standard frequencies can be implemented as shown in Table 6. The relationship between telephone keyboard symbols, DTMF frequency pairs and the corresponding frequency register contents are given in Table 7. 1996 Dec 18 Dialling symbols, corresponding DTMF frequency pairs and frequency register contents 9 LGF VALUE (HEX) HGF VALUE (HEX) 0 (941, 1336) A3 72 1 (697, 1209) DD 7F 2 (697, 1336) DD 72 3 (697, 1477) DD 67 4 (770, 1209) C8 7F 5 (770, 1336) C8 72 6 (770, 1477) C8 67 7 (852, 1209) B5 7F 8 (852, 1336) B5 72 9 (852, 1477) B5 67 A (697, 1633) DD 5D B (770, 1633) C8 5D C (852, 1633) B5 5D D (941, 1633) A3 5D • (941, 1209) A3 7F # (941, 1477) A3 67 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 6.6 PCA3354C; PCD3354A Table 9 Modem frequencies Again assuming an oscillator frequency fxtal = 3.58 MHz, the standard modem frequencies can be implemented as in Table 8. It is suggested to define the frequency by the HGF register while the LGF register contains 00H, disabling Low Group Frequency generation. Table 8 NOTE Standard modem frequencies and their implementation HGF VALUE (HEX) FREQUENCY (Hz) MODEM DEVIATION GENERATED (%) (Hz) HGF VALUE (HEX) FREQUENCY (Hz) STANDARD(1) GENERATED D#5 F8 622.3 622.5 E5 EA 659.3 659.5 F5 DD 698.5 697.9 F#5 D0 740.0 741.1 G5 C5 784.0 782.1 G#5 B9 830.6 832.3 9D 980(1) 978.82 −0.12 −1.18 A5 AF 880.0 879.3 82 1180(1) 1179.03 −0.08 −0.97 A#5 A5 923.3 931.9 8F 1070(2) 1073.33 0.31 3.33 B5 9C 987.8 985.0 79 1270(2) 1265.30 −0.37 −4.70 C6 93 1046.5 1044.5 80 1200(3) 1197.17 −0.24 −2.83 C#6 8A 1108.7 1111.7 45 2200(3) 2192.01 −0.36 −7.99 D6 82 1174.7 1179.0 76 1300(4) 1296.94 −0.24 −3.06 D#6 7B 1244.5 1245.1 48 2100(4) 2103.14 0.15 3.14 E6 74 1318.5 1318.9 5C 1650(1) 1655.66 0.34 5.66 F6 6D 1396.9 1402.1 52 1850(1) 1852.77 0.15 2.77 F#6 67 1480.0 1482.2 4B 2025(2) 2021.20 −0.19 −3.80 G6 61 1568.0 1572.0 44 2225(2) 2223.32 −0.08 −1.68 G#6 5C 1661.2 1655.7 Notes 1. Standard is V.21. 2. Standard is Bell 103. 3. Standard is Bell 202. 4. Standard is V.23. 6.7 Musical scale frequencies and their implementation Musical scale frequencies 56 1760.0 1768.5 51 1864.7 1875.1 B6 4D 1975.5 1970.0 C7 48 2093.0 2103.3 C#7 44 2217.5 2223.3 D7 40 2349.3 2358.1 D#7 3D 2489.0 2470.4 Note Finally, two octaves of musical scale in steps of semitones can be realized, again assuming an oscillator frequency fxtal = 3.58 MHz (Table 9). It is suggested to define the frequency by the HGF register while the LGF contains 00H, disabling Low Group Frequency generation. 1996 Dec 18 A6 A#6 1. Standard scale based on A4 @ 440 Hz. 10 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 7 PCA3354C; PCD3354A Whereas read access times to an EEPROM are comparable to RAM access times, write and erase accesses are much slower at 5 ms each. To make these operations more efficient, several provisions are available in the PCA3354C; PCD3354A. EEPROM AND TIMER 2 ORGANIZATION The PCA3354C; PCD3354A have 256 bytes of Electrically Erasable Programmable Read Only Memory (EEPROM). Such non-volatile storage provides data retention without the need for battery backup. In telecom applications, the EEPROM is used for storing redial numbers and for short dialling of frequently used numbers. More generally, EEPROM may be used for customizing microcontrollers, such as to include a PIN code or a country code, to define trimming parameters, to select application features from the range stored in ROM. First, the EEPROM array is structured into 64 four-byte pages (see Fig.4) permitting access to 4 bytes in parallel (write page, erase/write page and erase page). It is also possible to erase and write individual bytes. Finally, the EEPROM address register provides auto-incrementing, allowing very efficient read and write accesses to sequential bytes. The most significant difference between a RAM and an EEPROM is that a bit in EEPROM, once written to a logic 1, cannot be cleared by a subsequent write operation. Successive write accesses actually perform a logical OR with the previously stored information. Therefore, to clear a bit, the whole byte must be erased and re-written with the particular bit cleared. Thus, an erase-and-write operation is the EEPROM equivalent of a RAM write operation. 1996 Dec 18 To simplify the erase and write timing, the derivative 8-bit down-counter (Timer 2) with reload register is provided. In addition to EEPROM timing, Timer 2 can be used for general real-time tasks, such as for measuring signal duration and for defining pulse widths. 11 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A handbook, full pagewidth 6 8 EEPROM ADDRESS REGISTER 2 6 : 64 DECODER 2 : 4 DECODER 8 EEPROM LATCH 0 F0 EEPROM LATCH 1 F1 EEPROM LATCH 2 F2 EEPROM LATCH 3 F3 256-byte EEPROM ARRAY (64 4-byte PAGES) 8 8 EEPROM TEST REGISTER 8 EEPROM CONTROL REGISTER 8 T2F set on underflow TIMER 2 RELOAD REGISTER 8 8 TIMER 2 REGISTER (T2) 8 INTERNAL BUS MGB783 1 f 480 xtal Fig.4 Block diagram of the EEPROM and Timer 2. 1996 Dec 18 12 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 7.1 PCA3354C; PCD3354A EEPROM registers 7.1.1 EEPROM CONTROL REGISTER (EPCR) The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register. See Tables 10, 11 and 12. Table 10 EEPROM Control Register (address 04H, access type R/W) 7 6 5 4 3 2 1 0 STT2 ET2I T2F EWP MC3 MC2 MC1 0 Table 11 Description of the EPCR bits BIT SYMBOL DESCRIPTION 7 STT2 Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2 decrements from reload value. 6 ET2I Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1, then T2F event can request interrupt. 5 T2F Timer 2 flag. Set when T2 underflows (or by program); reset by program. 4 EWP Erase or write in progress (EWP). Set by program (EWP starts EEPROM erase and/or write and Timer 2). Reset at the end of EEPROM erase and/or write. 3 MC3 2 MC2 Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as shown in Table 12. 1 MC1 0 − This bit is set to a logic 0. Table 12 Mode selection; X = don’t care EWP MC3 MC2 MC1 0 0 0 0 read byte 0 0 1 0 increment mode 1 0 1 X write page 1 1 0 0 erase/write page 1 1 1 1 erase page X 0 0 1 not allowed X 1 0 1 X 1 1 0 1996 Dec 18 DESCRIPTION 13 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 7.1.2 PCA3354C; PCD3354A EEPROM ADDRESS REGISTER (ADDR) The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed. As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero. Table 13 EEPROM Address Register (address 01H, access type R/W) 7 6 5 4 3 2 1 0 0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Table 14 Description of ADDR bits BIT SYMBOL 7 − 6 to 2 AD6 to AD2 AD2 to AD6 select one of 32 pages. 1 to 0 AD1 to AD0 AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0 and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment mode (Table 12) is active during page setup, the subcounter consisting of AD0 and AD1 increments after every write to an EEPROM latch, thus enhancing access to sequential EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when AD0 and AD1 are both a logic 1. 7.1.3 DESCRIPTION This bit is set to a logic 0. EEPROM DATA REGISTER (DATR) Table 15 EEPROM Data Register (address 03H; access type R/W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Table 16 Description of DATR bits BIT SYMBOL DESCRIPTION 7 to 0 D7 to D0 The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write operation to DATR, loads data into the EEPROM latch (see Fig.4) defined by bits AD0 and AD1 of ADDR. 7.1.4 EEPROM TEST REGISTER (TST) The EEPROM Test register is used for testing purposes during device manufacture. It must not be accessed by the device user. 1996 Dec 18 14 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 7.2 PCA3354C; PCD3354A page, are irrelevant during write and erase cycles. However, write and erase cycles need not affect all bytes of the page. The EEPROM flags F0 to F3 (see Fig.4) determine which bytes within the EEPROM page are affected by the erase and/or write cycles. A byte whose corresponding EEPROM flag is zero remains unchanged. EEPROM latches The four EEPROM latches (EEPROM Latch 0 to 3; Fig.4) cannot be read by user software. Due to their construction, the latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of any EEPROM cycle. 7.3 With erase page, a byte is erased if its corresponding EEPROM flag is set. With write page, data in EEPROM latches 0 to 3 (Fig.4) are ORed to the individual page bytes if and only if the corresponding EEPROM flags are set. EEPROM flags The four EEPROM flags (F0 to F3; Fig.4) cannot be directly accessed by user software. An EEPROM flag is set as a side-effect when the corresponding EEPROM latch is written through DATR. The EEPROM flags are reset at the conclusion of any EEPROM cycle. In an erase/write cycle, F0 to F3 select which page bytes are erased and ORed with the corresponding EEPROM latches. 7.4 The described page-wise organization of erase and write cycles allows up to four bytes to be individually erased or written within 5 ms. This advantage necessitates a preparation step, called page setup, before the actual erase and/or write cycle can be executed. ORing, in this event, means that the EEPROM latches are copied to the selected page bytes. EEPROM macros The instruction sequence used in an EEPROM access should be treated as an indivisible entity. Erroneous programs result if ADDR, DATR, RELR or EPCR are inadvertently changed during an EEPROM cycle or its setup. Special care should be taken if the program may asynchronously divert due to an interrupt. A new access to the EEPROM may only be initiated when no write, erase or erase/write cycles are in progress. This can be verified by reading bit EWP (register EPCR). Page setup controls EEPROM latches and EEPROM flags. This will be described in the Sections 7.5.1 to 7.5.5. 7.5.1 Page setup is a preparation step required before write page, erase page and erase/write page cycles. As previously described, these page operations include single-byte write, erase and erase/write as a special event. EEPROM flags F0 to F3 determine which page bytes will be affected by the mentioned page operations. EEPROM Latch 0 to 3 must be preset through DATR to specify the write cycle data to EEPROM and to set the EEPROM flags as a side-effect. For write, erase and erase/write cycles, it is assumed that the Timer 2 Reload Register (RELR) has been loaded with the appropriate value for a 5 ms delay, which depends on fxtal (see Table 23). The end of a write, erase or erase/write cycle will be signalled by a cleared EWP and by a Timer 2 interrupt provided that ET2I = 1 and that the derivative interrupt is enabled. 7.5 EEPROM access Obviously, the actual preset value of the EEPROM latches is irrelevant for erase page. Preset of one, two, three or all four EEPROM latches and the corresponding EEPROM flags can be performed by repeatedly defining ADDR and writing to DATR (see Table 17). One read, one write, one erase/write and one erase access are defined by bits EWP and MC1 to MC3 in the EPCR register; see Table 10. Read byte retrieves the EEPROM byte addressed by ADDR when DATR is read. Read cycles are instantaneous. If more than one EEPROM latch must be preset, the subcounter consisting of AD0 and AD1 can be induced to auto-increment after every write to DATR, thus stepping through all EEPROM latches. For this purpose, increment mode (Table 12) must be selected. Auto-incrementing stops at EEPROM Latch 3. It is not mandatory to start at EEPROM Latch 0 as in shown in Table 18. Write and erase cycles take 5 ms, however. Erase/write is a combination of an erase and a subsequent write cycle, consequently taking 10 ms. As their names imply, write page, erase page and erase/write page are applied to a whole EEPROM page. Therefore, bits AD0 and AD1 of register ADDR (see Table 13), defining the byte location within an EEPROM 1996 Dec 18 PAGE SETUP Note that AD2 to AD6 are irrelevant during page setup. They will usually specify the intended EEPROM page, anticipating the subsequent page cycle. 15 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A From now on, it will be assumed that AD2 to AD6 will contain the intended EEPROM page address after page setup. latches, the corresponding bytes in the page should previously have been erased. The EEPROM latches are preset as described in Section 7.5.1. The actual transfer to the EEPROM is then performed as shown in Table 20. Table 17 Page setup; preset INSTRUCTION RESULT MOV A, #addr address of EEPROM latch MOV ADDR, A send address to ADDR MOV A, #data load write, erase/write or erase data MOV DATR, A send data to addressed EEPROM latch The last instruction also starts Timer 2. The data in the EEPROM latches are ORed with that in the corresponding page bytes within 5 ms. A single-byte write is simply a special case of ‘write page’. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by bits AD2 to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1). This allows efficient coding of multi-page write operations. Table 18 Page setup; auto-incrementing INSTRUCTION RESULT MOV A, #MC2 increment mode control word MOV EPCR, A select increment mode MOV A, #baddr EEPROM Latch 0 address (AD0 = AD1 = 0) MOV ADDR, A send EEPROM Latch 0 address to ADDR MOV A, R0 load 1st byte from Register 0 MOV DATR, A send 1st byte to EEPROM Latch 0 MOV A, R1 load 2nd byte from Register 1 MOV DATR, A send 2nd byte to EEPROM Latch 1 MOV A, R2 load 3rd byte from Register 2 MOV DATR, A send 3rd byte to EEPROM Latch 2 MOV A, R3 load 4th byte from Register 3 MOV DATR, A send 4th byte to EEPROM Latch 3 7.5.2 Table 20 Write page INSTRUCTION RESULT MOV A, #EWP + MC2 ‘write page’ control word MOV EPCR, A start ‘write page’ cycle 7.5.4 ERASE/WRITE PAGE The EEPROM latches are preset as described in Section 7.5.1. The page byte corresponding to the asserted flags (among F0 to F3) are erased and re-written with the contents of the respective EEPROM latches. The last instruction also starts Timer 2. Erasure takes 5 ms upon which Timer Register T2 reloads for another 5 ms cycle for writing. The top cycles together take 10 ms. A single-byte erase/write is simply a special event of ‘erase/write page’. ADDR auto-increments after the write cycle. If AD0 and AD1 addressed EEPROM Latch 3 prior to the write cycle, ADDR will point to the next EEPROM page (by AD2 to AD6) and to EEPROM Latch 0 (by AD0 and AD1). This allows efficient coding of multi-page erase/write operations. READ BYTE Since ADDR auto-increments after a read cycle regardless of the page boundary, successive bytes can efficiently be read by repeating the last instruction. Table 19 Read byte INSTRUCTION Table 21 Erase/write page RESULT INSTRUCTION RESULT MOV A, #RDADDR load read address MOV ADDR, A send address to ADDR MOV A, #EWP + MC3 ‘erase/write page’ control word read EEPROM data MOV EPCR, A start ‘erase/write page’ cycle MOV A, DATR 7.5.3 WRITE PAGE The write cycle performs a logical OR between the data in the EEPROM latches and that in the addressed EEPROM page. To actually copy the data from the EEPROM 1996 Dec 18 16 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 7.5.5 PCA3354C; PCD3354A The second underflow of an erase/write cycle and the first underflow of write page and erase page conclude the corresponding EEPROM cycle. Timer 2 is stopped, T2F is set whereas EWP and MC1 to MC3 are cleared. ERASE PAGE The EEPROM flags are set as described in Section 7.5.1. The corresponding page bytes are erased. The last instruction also starts Timer 2. Erasure takes 5 ms. A single-byte erase is simply a special case of ‘erase page’. Table 23 Reload values as a function of fxtal Note that ADDR does not auto-increment after an erase cycle. fxtal (MHz) RELOAD VALUE(1) (HEX) 1 0A 2 14 Table 22 Erase page INSTRUCTION RESULT MOV A, #EWP + MC3 + MC2 + MC1 ‘erase page’ control word MOV EPCR, A 7.6 start ‘erase page’ cycle 3E 10.74 6F 16 A6 1. The reload value is (5 × 10−3 × 1⁄480 × fxtal) − 1; fxtal in MHz. Timer 2 7.6.2 TIMER 2 AS A GENERAL PURPOSE TIMER When used for purposes other than EEPROM timing, Timer 2 is started by setting STT2. The Timer 2 Register T2 (see Table 25) is loaded with the reload value from RELR. T2 decrements to zero. On underflow, T2 is reloaded from RELR, T2F is set and T2 continues to decrement. TIMER 2 FOR EEPROM TIMING When used for EEPROM timing, Timer 2 serves to generate the 5 ms intervals needed for erasing or writing the EEPROM. At the decrement rate of 1⁄480 × fxtal, the reload value for a 5 ms interval is a function of fxtal. Table 23 summarizes the required reload values for a number of oscillator frequencies. Timer 2 can be stopped at any time by clearing STT2. The value of T2 is then held and can be read out. After setting STT2 again, Timer 2 decrements from the reload value. Alternatively, it is possible to read T2 ‘on the fly’ i.e. while Timer 2 is operating. Timer 2 is started by setting bit EWP in the EPCR. The Timer Register T2 is loaded with the reload value from RELR. T2 decrements to zero. For an erase/write cycle, underflow of T2 indicates the end of the erase operation. Therefore, Timer Register T2 is reloaded from RELR for another 5 ms interval during which the flagged EEPROM latches are copied to the corresponding bytes in the page addressed by ADDR. 1996 Dec 18 25 6 Note Timer 2 is a 8-bit down-counter decremented at a rate of 1⁄ 480 × fxtal. It may be used either for EEPROM timing or as a general purpose timer. Conflicts between the two applications should be carefully avoided. 7.6.1 3.58 17 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM 8 PCA3354C; PCD3354A 11 IDLE MODE DERIVATIVE INTERRUPTS In Idle mode, the frequency generator, the EEPROM and the Timer 2 sections remain operative. Therefore, the IDLE instruction may be executed while an erase and/or write access to EEPROM is in progress. One derivative interrupt event is defined. It is controlled by bits T2F and ET2I in the EPCR (see Tables 10 and 11). The derivative interrupt event occurs when T2F is set. This request is honoured under the following circumstances: • No interrupt routine proceeds • No external interrupt request is pending 12 STOP MODE • The derivative interrupt is enabled Since the oscillator is switched off, the frequency generator, the EEPROM and the Timer 2 sections receive no clock. It is suggested to clear both the HGF and the LGF registers before entering stop mode. This will cut off the biasing of the internal amplifiers, considerably reducing current requirements. • ET2I is set. The derivative interrupt routine must include instructions that will remove the cause of the derivative interrupt by explicitly clearing T2F. If the derivative interrupt is not used, T2F may directly be tested by the program. Obviously, T2F can also be asserted under program control, e.g. to generate a software interrupt. 9 The Stop mode must not be entered while an erase and/or write access to EEPROM is in progress. The STOP instruction may only be executed when EWP in EPCR is zero. The Timer 2 section is frozen during Stop mode. After exit from Stop mode by a HIGH level on CE/T0, Timer 2 proceeds from the held state. TIMING Although the PCA3354C; PCD3354A operate over a clock frequency range from 1 MHz to 16 MHz, fxtal = 3.58 MHz or 10.74 MHz will usually be chosen to take full advantage of the frequency generator section. 10 RESET In addition to the conditions given in the “PCD33xxA Family” data sheet, all derivative registers are cleared in the reset state. 1996 Dec 18 18 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 13 SUMMARY OF I/O PORTS AND MASK OPTIONS All standard quasi-bidirectional I/O ports are available; see “PCD33xxA Family” data sheet. • Port 0: 8 parallel port lines P0.0 to P0.7 • Port 1: 8 parallel port lines P1.0 to P1.7 • Port 2: 4 parallel port lines P2.0 to P2.3. In addition to the standard ports, 2 derivative I/O ports are available: • Derivative Port 0: 8 parallel port lines DP0.0 to DP0.7 (register DP0L) • Derivative Port 1: 8 parallel port lines DP1.0 to DP1.7 (register DP1L). The port options and the other ROM mask options are listed in Table 24. See Table 25 for the addresses of DP0L and DP1L. Table 24 ROM mask options FUNCTION IMPLEMENTED IN ROM Program/data OPTION Any mix of instructions and data up to ROM size of 8 kbytes. Port Output P0.0 to P0.7 standard open-drain push-pull P1.0 to P1.6 standard open-drain push-pull P1.7/MDY; note 1 standard open-drain push-pull P2.0 to P2.3 standard open-drain push-pull DP0.0 to DP0.7 standard open-drain push-pull DP1.0 to DP1.6 standard open-drain push-pull DP1.7/DCO; note 2 standard open-drain push-pull P0.0 to P0.7 set reset − P1.0 to P1.6 set reset − P1.7/MDY set reset − Port State after reset P2.0 to P2.3 set reset − DP0.0 to DP0.7 set reset − DP1.0 to DP1.6 set reset − DP1.7/DCO set reset − LOW (gmL) MEDIUM (gmM) HIGH (gmH) Oscillator Transconductance Power-on-reset Power-on-reset voltage level: VPOR 1.2 to 3.6 V in increments of 100 mV; OFF Notes 1. If standard (Option 1) or push-pull (Option 3) output is chosen, the P1.7/MDY output becomes a push-pull output. If open-drain (Option 2) is chosen the P1.7/MDY output becomes an open-drain output. 2. If standard (Option 1) or push-pull (Option 3) output is chosen, the DP1.7/DCO output becomes a push-pull output. If open-drain (Option 2) is chosen the DP1.7/DCO output becomes an open-drain output. 1996 Dec 18 19 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 14 SUMMARY OF DERIVATIVE REGISTERS Table 25 Register map ADDR. (HEX) REGISTER 00 not used 01 EEPROM Address Register (ADDR) 02 not used 03 EEPROM Data Register (DATR) 04 EEPROM Control Register (EPCR) 05 Timer 2 Reload Register (RELR) 06 Timer 2 Register (T2) 07 Test Register (TST) 7 6 5 4 3 2 1 0 R/W 0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 R/W STT2 ET21 TF2 EWP MC3 MC2 MC1 0 R/W R7 R6 R5 R4 R3 R2 R1 R0 R/W T2.7 T2.6 T2.5 T2.4 T2.3 T2.2 T2.1 T2.0 R only for test purposes; not to be accessed by the device user 08 to 10 not used 11 High Group Frequency Register (HGF) H7 H6 H5 H4 H3 H2 H1 H0 W 12 Low Group Frequency Register (LGF) L7 L6 L5 L4 L3 L2 L1 L0 W 13 Clock and Melody Control Register (MDYCON) 0 0 0 0 0 DCO DIV3 EMO R/W 14 to 2F not used 30 Derivative Port 0 lines (DP0L) D0.7 D0.6 D0.5 D0.4 D0.3 D0.2 D0.1 D0.0 R 31 Derivative Port 1 lines (DP1L) D1.7 D1.6 D1.5 D1.4 D1.3 D1.2 D1.1 D1.0 R 32 Derivative Port 0 flip-flop (DP0FF) F0.7 F0.6 F0.5 F0.4 F0.3 F0.2 F0.1 F0.0 R/W 33 Derivative Port 1 flip-flop (DP1FF) F1.7 F1.6 F1.5 F1.4 F1.3 F1.2 F1.1 F1.0 R/W 34 to FF not used 1996 Dec 18 20 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 15 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.8 +7.0 VI all input voltages −0.5 VDD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA Ptot total power dissipation − 125 mW PO power dissipation per output − 30 mW ISS ground supply current −50 +50 mA Tstg storage temperature −65 +150 °C Tj operating junction temperature − 90 °C V 16 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices (see “Data Handbook IC14, Section: Handling MOS devices”). 1996 Dec 18 21 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 17 DC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = 0 to +50 °C (PCA3354C) or −25 to +70 °C (PCD3354A); all voltages with respect to VSS; fxtal = 3.58 MHz (gmL); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage operating see Fig.5 1.8 − 6 V 1.0 − 6 V VDD = 3 V; value HGF or LGF ≠ 0 − 0.8 1.6 mA VDD = 3 V; value HGF = LGF = 0 − 0.35 0.7 mA VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF or LGF ≠ 0; DIV3 = 1 − 2.7 6.2 mA VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF = LGF = 0 − 1.7 4.2 mA VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 − 3.5 − mA VDD = 3 V; value HGF or LGF ≠ 0 − 0.7 1.4 mA VDD = 3 V; value HGF = LGF =0 − 0.25 0.5 mA VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF or LGF ≠ 0; DIV3 = 1 − 2.3 5.5 mA VDD = 5 V; fxtal = 10.74 MHz (gmM); value HGF = LGF = 0 − 1.3 3.5 mA VDD = 5 V; fxtal = 16 MHz (gmH); value HGF = LGF = 0 − 2.4 − mA VDD = 1.8 V; Tamb = 25 °C − 1.0 5.5 µA VDD = 1.8 V; Tamb = −25 to +70 °C − − 10 µA − note 1 RAM data retention in Stop mode IDD IDD(idle) IDD(stp) operating supply current supply current (Idle mode) supply current (Stop mode) see Figs 6 and 7; note 2 see Figs 8 and 9; note 2 See Fig.10; notes 2 and 3 Inputs VIL LOW level input voltage 0 VIH HIGH level input voltage 0.7VDD − VDD V ILI input leakage current VSS ≤ VI ≤ VDD −1 − +1 µA 0.3VDD V Port outputs IOL LOW level output sink current VDD = 3 V; VO = 0.4 V; see Fig.11 0.7 3.5 − mA IOH HIGH level pull-up output source current VDD = 3 V; VO = 2.7 V; see Fig.12 −10 −30 − µA VDD = 3 V; VO = 0 V; see Fig.12 − −140 −300 µA HIGH level push-pull output source current VDD = 3 V; VO = 2.6 V; see Fig.13 −0.7 −3.5 − mA IOH1 1996 Dec 18 22 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM SYMBOL PARAMETER PCA3354C; PCD3354A CONDITIONS MIN. TYP. MAX. UNIT TONE output (see Fig.14; notes 1 and 4) VHG(RMS) HGF voltage (RMS values) 158 181 205 mV VLG(RMS) LGF voltage (RMS values) 125 142 160 mV ∆f ⁄ f frequency deviation −0.6 − 0.6 % VDC DC voltage level − 0.5VDD − V ZO output impedance − 100 500 Ω Gv pre-emphasis of group 1.5 2.0 2.5 dB THD total harmonic distortion Tamb = 25 °C; note 5 − −25 − dB note 7 105 − − 10 − − years EEPROM (notes 1 and 6) ncyc endurance (erase/write cycles) tret data retention Power-on-reset (see Fig.15) ∆VPOR Power-on-reset level variation around chosen VPOR note 8; for PCD3354A −0.5 0 +0.5 V VPOR Power-on-reset level note 9; for PCA3354C 1.7 2.0 2.3 V VDD = 5 V 0.2 0.4 1.0 mS Oscillator (see Fig.16) gmL LOW transconductance gmM MEDIUM transconductance VDD = 5 V 0.9 1.6 3.2 mS gmH HIGH transconductance VDD = 5 V 3 4.5 9.0 mS RF feedback resistor 0.3 1.0 3.0 MΩ Notes to the DC characteristics 1. TONE output; EEPROM erase and write require VDD ≥ 2.5 V: a) TONE output requires fxtal < 4 MHz in case DIV3 = 0. b) TONE output requires fxtal < 12 MHz in case DIV3 = 1. 2. VIL = VSS; VIH = VDD; open-drain outputs connected to VSS; all other outputs open: a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit. b) Typical values: Tamb = 25 °C; crystal connected between XTAL1 and XTAL2. 3. VIL = VSS; VIH = VDD; RESET, T1 and CE/T0 at VSS; crystal connected between XTAL1 and XTAL2; open-drain outputs connected to VSS; all other outputs open. 4. Values are specified for DTMF frequencies only (CEPT). 5. Related to the Low Group Frequency (LGF) component (CEPT). 6. After final testing the value of each EEPROM bit is typically logic 1. 7. Verified on sampling basis. 8. VPOR is an option chosen by the user. Depending on its value, it may restrict the supply voltage range. 9. Each device is tested on the condition: VDD(min) < VPOR; to ensure a correct start-up, even for slow rising supply voltages. 1996 Dec 18 23 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A MGB813 MLA493 18 xtal (MHz) 15 6 handbook, halfpage f handbook, halfpage IDD (mA) 12 10.7 MHz HGF ≠ LGF = 0 gmM 4 16 MHz HGF = LGF = 0 gmH –25 oC to 70 oC 9 guaranteed operating range 6 3.58 MHz HGF ≠ LGF gmL 10.7 MHz HGF = LGF = 0 gmM 2 3 0 3.58 MHz HGF = LGF = 0 gmL 1 3 5 0 7 VDD (V) 1 3 5 VDD (V) 7 Measured with crystal between XTAL1 and XTAL2. Fig.5 Maximum clock frequency (fxtal) as a function of supply voltage (VDD). Fig.6 Typical operating supply current (IDD) as a function of supply voltage (VDD). MGB814 MGB828 6 6 handbook, halfpage handbook, halfpage IDD(idle) (mA) IDD (mA) 16 MHz HGF = LGF = 0 gmH –25 oC to 70 oC 4 4 5V 2 10.7 MHz HGF ≠ LGF = 0 gmM 2 3.58 MHz HGF ≠ LGF gmL 10.7 MHz HGF = LGF = 0 gmM 3.58 MHz HGF = LGF = 0 gmL 3V 0 1 10 fxtal (MHz) 10 0 2 1 3 5 VDD (V) Measured with function generator on XTAL1. Measured with crystal between XTAL1 and XTAL2. Fig.7 Fig.8 Typical operating supply current (IDD) as a function of clock frequency (fxtal). 1996 Dec 18 24 7 Typical supply current in Idle mode (IDD(idle)) as a function of supply voltage (VDD). Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A MGB826 MGB830 6 6 handbook, halfpage handbook, halfpage IDD(idle) (mA) IDD(stp) (µA) 5 4 4 3 2 2 5V 1 3V 0 1 10 fxtal (MHz) 10 0 2 1 3 5 VDD (V) 7 Measured with function generator on XTAL1. Fig.9 Fig.10 Typical supply current in Stop mode (IDD(stp)) as a function of supply voltage (VDD). Typical supply current in Idle mode (IDD(idle)) as a function of clock frequency (fxtal). MGB831 MGB832 −300 12 handbook, halfpage handbook, halfpage IOL (mA) IOH (µA) 8 −200 4 −100 VO = 0 V VO = 0.9VDD 0 0 1 3 5 VDD (V) 7 1 3 5 VDD (V) 7 VO = 0.4 V. Fig.12 Typical HIGH level pull-up output source current (IOH) as a function of supply voltage (VDD). Fig.11 Typical LOW level output sink current (IOL) as a function of supply voltage (VDD). 1996 Dec 18 25 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A MGB833 −12 handbook, halfpage IOH1 (mA) handbook, halfpage VDD −8 DEVICE TYPE NUMBER (1) TONE 1 µF 10 kΩ 50 pF −4 VSS MGB835 0 1 3 5 VDD (V) 7 VO = VDD − 0.4 V. Fig.13 Typical HIGH level push-pull output source current (IOH1) as a function of supply voltage (VDD). (1) Device type number: PCA3354C or PCD3354A. Fig.14 TONE output test circuit. MGD495 MGB818 10 6 handbook, halfpage handbook, halfpage VDD (V) gmH gm (mS) 4 gmM 1 VPOR = 2.0 V gmL 2 VPOR = 1.3 V 0 −25 10 25 75 125 Tamb (°C) 70 Fig.15 Typical Power-on-reset level (VPOR) as function of ambient temperature (Tamb). 1996 Dec 18 1 1 3 5 VDD (V) 7 Fig.16 Typical transconductance (gm) as a function of supply voltage (VDD). 26 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 18 AC CHARACTERISTICS VDD = 1.8 to 6 V; VSS = 0 V; Tamb = 0 to +50 °C (PCA3354C) or −25 to +70 °C (PCD3354A); all voltages with respect to VSS; unless otherwise specified. SYMBOL PARAMETER tr rise time all outputs tf fall time all outputs fxtal clock frequency 1996 Dec 18 CONDITIONS VDD = 5 V; Tamb = 25 °C; CL = 50 pF see Fig.5 27 MIN. TYP. MAX. UNIT − 30 − ns − 30 − ns 1 − 16 MHz Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 19 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1 c y X 33 A 23 34 22 ZE e Q E HE A A2 (A 3) A1 wM θ bp Lp pin 1 index 44 L 12 detail X 1 11 ZD e v M A wM bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 2.60 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 14.1 13.9 1 19.2 18.2 19.2 18.2 2.35 2.0 1.2 1.2 0.9 0.3 0.15 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT205-1 133E01A 1996 Dec 18 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 28 o 7 0o Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A If wave soldering cannot be avoided, the following conditions must be observed: 20 SOLDERING 20.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). 20.2 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 20.4 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 20.3 Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Dec 18 Repairing soldered joints 29 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A 21 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 22 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Dec 18 30 Philips Semiconductors Product specification 8-bit microcontrollers with DTMF generator and 256 bytes EEPROM PCA3354C; PCD3354A NOTES 1996 Dec 18 31 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 417021/1200/04/pp32 Date of release: 1996 Dec 18 Document order number: 9397 750 01082