PHILIPS PCD3359A

INTEGRATED CIRCUITS
DATA SHEET
PCD3359A
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
Product specification
Supersedes data of 1996 Dec 18
File under Integrated Circuits, IC03
1998 May 11
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
CONTENTS
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
5
PINNING INFORMATION
5.1
5.2
Pinning
Pin descriptions
6
FREQUENCY GENERATOR
6.1
6.2
6.3
6.4
6.5
6.6
Frequency generator derivative registers
Melody output (P1.7/MDY)
Frequency registers
DTMF frequencies
Modem frequencies
Musical scale frequencies
7
EEPROM AND TIMER 2 ORGANIZATION
7.1
7.2
7.3
7.4
7.5
7.6
EEPROM registers
EEPROM latches
EEPROM flags
EEPROM macros
EEPROM access
Timer 2
8
INTERRUPTS
8.1
8.2
Derivative interrupt
Port 0 Wake-up interrupts
1998 May 11
2
9
TIMING
10
RESET
11
IDLE MODE
12
STOP MODE
13
INSTRUCTION SET RESTRICTIONS
14
OVERVIEW OF PORT AND
POWER-ON-RESET CONFIGURATION
15
SUMMARY OF DERIVATIVE REGISTERS
16
HANDLING
17
LIMITING VALUES
18
DC CHARACTERISTICS
19
AC CHARACTERISTICS
20
PACKAGE OUTLINES
21
SOLDERING
21.1
21.2
21.3
Introduction
DIP
LQFP and SO
22
DEFINITIONS
23
LIFE SUPPORT APPLICATIONS
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
1
PCD3359A
• Clock frequency: 1 to 16 MHz (3.58 MHz for DTMF
suggested)
FEATURES
• 8-bit CPU, ROM, RAM, EEPROM and I/O; in a single
28-lead or 32-lead package
• Operating temperature: −25 to +70 °C
• Manufactured in silicon gate CMOS process.
• 2-kbyte ROM
• 64-byte RAM
• 128-byte EEPROM
2
• OTP version available
This data sheet details the specific properties of the
PCD3359A. The shared properties of the PCD33xxA
family of microcontrollers are described in the “PCD33xxA
family” data sheet, which should be read in conjunction
with this publication.
• Over 100 instructions (based on MAB8048) all of
1 or 2 cycles
• 20 quasi-bidirectional I/O port lines
• 8-bit programmable Timer/event counter 1
GENERAL DESCRIPTION
The PCD3359A is a low voltage microcontroller oriented
towards telephony applications. It includes an on-chip
generator for dual tone multifrequency (DTMF) generator,
modem and musical tones. In addition to dialling,
generated frequencies can be made available as square
waves (P1.7/MDY) for melody generation, providing ringer
operation (in which case the TONE output is disabled).
A wake-up function via Port 0 interrupt facilitates keyboard
interfacing. The PCD3359A can be emulated with the OTP
microcontroller PCD3756A.
• 8-bit reloadable Timer 2
• Three single-level vectored interrupts:
– external
– 8-bit programmable Timer/event counter 1
– derivative; triggered by reloadable Timer 2
• Wake-up via external or Port 0 interrupt
• Two test inputs, one of which also serves as the external
interrupt input
The device also incorporates 128 bytes of Electrically
Erasable Programmable Read-Only Memory (EEPROM).
The EEPROM can be used for storing telephone numbers,
particularly for implementing redial functions.
• DTMF, modem, musical tone generator
• Reference for supply and temperature-independent
tone output
• Filtering for low output distortion (CEPT compatible)
The instruction set is similar to that of the MAB8048 and is
a sub-set of that listed in the “PCD33xxA family” data
sheet.
• Melody output for ringer application
• Power-on-reset
• Stop and Idle modes
• Supply voltage: 1.8 to 6 V (DTMF tone output and
EEPROM erase/write from 2.5 V)
3
ORDERING INFORMATION
TYPE
NUMBER(1)
PACKAGE
NAME
DESCRIPTION
VERSION
PCD3359AP
DIP28
plastic dual in-line package; 28 leads (600 mil)
SOT117-1
PCD3359AT
SO28
plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
PCD3359AH
LQFP32
plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm
SOT358-1
Note
1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type
number will also specify the required program and the ROM mask options.
1998 May 11
3
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PORT 1
BUFFER
FILTER
PORT 2
FLIP-FLOP
PORT 1
FLIP-FLOP
INTERNAL
CLOCK
FREQ.
30
SINE WAVE
GENERATOR
HGF
REGISTER
LGF
REGISTER
MELODY
AND PORT
INTERRUPT
CONTROL
REGISTER
8
8
8
4
TIMER 2
RELOAD
REGISTER
8
8
8
8
TIMER 2
REGISTER
EEPROM
CONTROL
REGISTER
EEPROM
ADDRESS
REGISTER
EEPROM
DATA
TRANSFER
INTERRUPT
LOGIC
PORT 0
FLIP-FLOP
MEMORY
BANK
FLIP-FLOPS
32
TIMER/
EVENT
COUNTER
T1
PCD3359A
8
8
8
8
PORT 0
BUFFER
8
8
8
8
HIGHER
PROGRAM
COUNTER
LOWER
PROGRAM
COUNTER
5
8
8
8
8
8
8
TEMPORARY
REGISTER 1
ACCUMULATOR
RAM
ADDRESS
REGISTER
timer interrupt
port 0 interrupt
ARITHMETIC
TEMPORARY
REGISTER 2
INSTRUCTION
REGISTER
AND
DECODER
external interrupt
EEPROM
128 bytes
POWER-ON-RESET
8
MULTIPLEXER
4
derivative
interrupt
PROGRAM
STATUS
WORD
LOGIC UNIT
T1
VPOR
DECIMAL
ADJUST
RESET
D
E
C
O
D
E
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PORT 2
BUFFER
8
P0.0 to P0.7
RESIDENT ROM
8 kbytes
(PCD3356A)
6 kbytes
(PCD3357A)
2 kbytes
(PCD3359A)
DECODE
7
BLOCK DIAGRAM
4
Philips Semiconductors
4
1998 May 11
P1.7/MDY P1.0 to P1.6
TONE
P2.0 to P2.3
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 4
REGISTER 5
REGISTER 6
REGISTER 7
8 LEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK
CE/T0
CONDITIONAL
BRANCH
TIMER
FLAG
DATA STORE
CARRY
LOGIC
STOP
IDLE
ACC
CONTROL AND TIMING
CE/T0
INITIALIZE
XTAL2
OSCILLATOR
RESIDENT RAM ARRAY
ACC BIT
TEST
MBK811
Product specification
Fig.1 Block diagram.
XTAL1
PCD3359A
handbook, full pagewidth
INTERRUPT
RESET
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
5
5.1
PCD3359A
PINNING INFORMATION
Pinning
handbook, halfpage
P0.1
1
28 P0.0
P0.2
2
27 P2.3
P0.3
3
26 P2.2
P0.4
4
25 P2.1
P0.5
5
24 VDD
P0.6
6
23 TONE
P0.7
7
22 VSS
PCD3359A
T1
8
21 P2.0
XTAL1
9
20 P1.7/MDY
XTAL2 10
19 P1.6
RESET 11
18 P1.5
CE/T0 12
17 P1.4
P1.0 13
16 P1.3
P1.1 14
15 P1.2
MBK809
25 P2.2
26 P2.3
27 P0.0
28 n.c.
29 P0.1
30 P0.2
handbook, full pagewidth
31 P0.3
32 P0.4
Fig.2 Pin configuration (SOT117-1 and SOT136-1).
n.c.
1
24 P2.1
P0.5
2
23 VDD
P0.6
3
22 TONE
P0.7
4
21 VSS
PCD3359A
18 P1.6
RESET
8
17 n.c.
CE/T0
P1.5 16
7
P1.4 15
XTAL2
P1.3 14
19 P1.7/MDY
n.c. 13
6
P1.2 12
XTAL1
P1.1 11
20 P2.0
P1.0 10
5
9
T1
Fig.3 Pin configuration (SOT358-1).
1998 May 11
5
MBK810
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
5.2
PCD3359A
Pin descriptions
Table 1
SOT117-1 and SOT136-1 packages (for information on parallel I/O ports, see Chapter 14)
SYMBOL
PIN
TYPE
DESCRIPTION
1 to 7
I/O
7 bits of Port 0: 8-bit quasi-bidirectional I/O port; or wake-up interrupts
T1
8
I
Test 1 or count input of 8-bit Timer/event counter 1
XTAL1
9
I
crystal oscillator or external clock input
XTAL2
10
O
crystal oscillator output
RESET
11
I
reset input
CE/T0
12
I
Chip Enable or Test 0
13 to 19
I/O
7 bits of Port 1: 8-bit quasi-bidirectional I/O port
20
I/O
1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output
P2.0
21
I/O
VSS
22
P
ground
TONE
23
O
DTMF, modem, musical tone output
P0.1 to P0.7
P1.0 to P1.6
P1.7/MDY
VDD
P2.1 to P2.3
P0.0
Table 2
1 bit of Port 2: 4-bit quasi-bidirectional I/O port
24
P
25 to 27
I/O
3 bits of Port 2: 4-bit quasi-bidirectional I/O port
positive supply voltage
28
I/O
1 bit of Port 0: 8-bit quasi-bidirectional I/O port; or wake-up interrupts
SOT358-1 package (for information on parallel I/O ports, see Chapter 14)
SYMBOL
PIN
TYPE
n.c.
1, 13,
17, 28
−
P0.5 to P0.7
DESCRIPTION
not connected
2 to 4
I/O
T1
5
I
Test 1 or count input of 8-bit Timer/event counter 1
XTAL1
6
I
crystal oscillator or external clock input
XTAL2
7
O
crystal oscillator output
RESET
8
I
reset input
CE/T0
9
I
Chip Enable or Test 0
10 to 12
14 to 16
18
I/O
7 bits of Port 1: 8-bit quasi-bidirectional I/O port
19
I/O
1 bit of Port 1: 8-bit quasi-bidirectional I/O port; or melody output
20,
24 to 26
I/O
4 bits of Port 2: 4-bit quasi-bidirectional I/O port
P1.0 to P1.6
P1.7/MDY
P2.0 to P2.3
3 bits of Port 0: 8-bit quasi-bidirectional I/O port; or wake-up interrupts
VSS
21
P
ground
TONE
22
O
DTMF output
VDD
23
P
positive supply voltage
27,
29 to 32
I/O
P0.0 to P0.4
1998 May 11
5 bits of Port 0: 8-bit quasi-bidirectional I/O port; or wake-up interrupts
6
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
6
PCD3359A
The TONE output can alternatively issue twelve modem
frequencies for data rates between 300 and 1200 bits/s.
FREQUENCY GENERATOR
A versatile frequency generator section is provided (see
Fig.4). For normal operation, use a 3.58 MHz quartz
crystal or PXE resonator. The frequency generator
includes precision circuitry for dual tone multifrequency
(DTMF) signals, which is typically used for tone dialling
telephone sets.Their frequencies are provided in purely
sinusoidal form on the TONE output or as square waves
on the P1.7/MDY output.
6.1
In addition to DTMF and modem frequencies, two octaves
of musical scale in steps of semitones are available.
In case no tones are generated, or the melody function is
used, the TONE output is in 3-state mode.
Frequency generator derivative registers
6.1.1
HIGH AND LOW GROUP FREQUENCY REGISTERS
Table 3 gives the addresses, symbols and access types of the High Group Frequency (HGF) and Low Group Frequency
(LGF) Registers.
Table 3
Hexadecimal addresses, symbols, access types and bit symbols of the frequency registers
BIT SYMBOLS
REGISTER
ADDRESS
REGISTER
SYMBOL
ACCESS
TYPE
7
6
5
4
3
2
1
0
11H
HGF
W
H7
H6
H5
H4
H3
H2
H1
H0
12H
LGF
W
L7
L6
L5
L4
L3
L2
L1
L0
6.1.2
MELODY AND PORT INTERRUPT CONTROL REGISTER (MDYCON)
The Melody and Port Interrupt Control Register has two functions: bit 0 defines the behaviour of the melody output; bits
4 to 7 individually enable/disable specific pairs of Port 0 interrupts. MDYCON is a R/W register.
Table 4
Melody and Port Interrupt Control Register (address 13H)
7
6
5
4
3
2
1
0
EPI3
EPI2
EPI1
EPI0
0
0
0
EMO
Table 5
Description of MDYCON bits
BIT
7 to 4
SYMBOL
EPI3 to EPI0 Enable Port 0 interrupts. Bits 7 to 4 individually enable/disable specific pairs of Port 0
interrupts; see Table 6 and Section 8.2 for details.
3 to 1
−
0
EMO
1998 May 11
DESCRIPTION
These bits are set to a logic 0.
Enable Melody Output. If bit EMO = 0, then P1.7/MDY is a standard port line and the
TONE output is enabled. If bit EMO = 1, then P1.7/MDY is the melody output and the
TONE output is disabled (3-state). EMO = 1 does not inhibit the port instructions for
P1.7/MDY. Therefore, the state of both port line and flip-flop may be read in and the port
flip-flop may be written by port instructions. However, the port flip-flop of P1.7/MDY
must remain set to avoid conflicts between melody and port outputs. When the HGF
contents are zero while EMO = 1, P1.7/MDY is in the logic HIGH state.
7
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
Table 6
PCD3359A
Port 0 Interrupts control bits
INTERRUPTS
BIT
STATE
EPI0
EPI0
EPI0
EPI0
P0.0 AND P0.1
P0.2 AND P0.3
P0.4 AND P0.5
P0.6 AND P0.7
1
enabled
−
−
−
0
disabled
−
−
−
1
−
enabled
−
−
0
−
disabled
−
−
1
−
−
enabled
−
0
−
−
disabled
−
1
−
−
−
enabled
0
−
−
−
disabled
handbook, full pagewidth
8
MELODY AND PORT
INTERRUPT
CONTROL REGISTER
square wave
8
HGF REGISTER
PORT/MELODY
OUTPUT LOGIC
P1.7/
MDY
RC LOW-PASS
FILTER/OUTPUT
LOGIC
TONE
DIGITAL
SINE WAVE
SYNTHESIZER
DAC
8 INTERNAL BUS
SWITCHED
CAPACITOR
BANDGAP
VOLTAGE
REFERENCE
SWITCHED
CAPACITOR
LOW-PASS
FILTER
MGB823
DAC
8
LGF REGISTER
DIGITAL
SINE WAVE
SYNTHESIZER
Fig.4 Block diagram of the frequency generator and melody output (P1.7/MDY) section.
1998 May 11
8
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
6.2
PCD3359A
together with the Digital-to-Analog Converters (DACs)
construct two sine waves. Their amplitudes are precisely
scaled according to the bandgap voltage reference. This
ensures tone output levels independent of supply voltage
and temperature.
Melody output (P1.7/MDY)
The melody output (P1.7/MDY) is very useful for
generating musical notes when a purely sinusoidal signal
is not required, such as for ringer applications.
If bit EMO = 1 in the Melody and Port Interrupt Control
Register the TONE output is disabled (3-state) and a
square wave with the frequency defined by the HGF
contents is output on line P1.7/MDY. The square wave
(duty cycle = 12⁄23 or 52%) will include the attenuated
harmonics of the base frequency, which is defined by the
contents of the HGF register (Table 3). However, even
higher frequency notes may be produced since the
low-pass filtering on the TONE output is not applied to the
P1.7/MDY output. This results in the minimum decimal
value x in the HGF register (see equation in Section 6.3)
being 2 for the P1.7/MDY output, rather than 60 for the
TONE output. A sinusoidal TONE output is produced at the
same time as the melody square wave, but due to the
filtering, the higher frequency sine waves with x < 60 will
not appear at the TONE output.
The amplitude of the Low Group Frequency sine wave is
attenuated by 2 dB compared to the amplitude of the High
Group Frequency sine wave. The two sine waves are
summed and then filtered by an on-chip switched
capacitor and RC low-pass filters. These guarantee that all
DTMF tones generated fulfil the CEPT recommendations
with respect to amplitude, frequency deviation, total
harmonic distortion and suppression of unwanted
frequency components.
The value 00H in a frequency register stops the
corresponding digital sine synthesizer. If both frequency
registers contain 00H, the whole frequency generator is
shut off, resulting in lower power consumption.
The frequency of the sine wave generated ‘f’ is dependent
on the crystal frequency ‘fxtal’ and the decimal value ‘x’ held
in the frequency registers (HGF and LGF). The variables
are related by the equation:
f xtal
f = --------------------------------; where 60 ≤ x ≤ 255.
[ 23 ( x + 2 ) ]
Since the melody output is shared with P1.7, the port
flip-flop of P1.7 has to be set HIGH before using the
melody output. This is to avoid conflicts between melody
and port outputs. The melody output drive depends on the
configuration of port P1.7/MDY; see Chapter 14, Table 25.
6.3
The frequency limitation given by x ≥ 60 is due to the
low-pass filters which would attenuate higher frequency
sine waves.
Frequency registers
The two frequency registers HGF and LGF define two
frequencies. From these, the digital sine synthesizers
1998 May 11
9
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
6.4
PCD3359A
DTMF frequencies
6.5
Assuming an oscillator frequency fxtal = 3.58 MHz, the
DTMF standard frequencies can be implemented as
shown in Table 7.
Again assuming an oscillator frequency fxtal = 3.58 MHz,
the standard modem frequencies can be implemented as
in Table 9. It is suggested to define the frequency by the
HGF register while the LGF register contains 00H,
disabling Low Group Frequency generation.
The relationships between telephone keyboard symbols,
DTMF frequency pairs and the frequency register contents
are given in Table 8.
Table 7
HGF
VALUE
(HEX)
DEVIATION
(%)
(Hz)
DD
697
697.90
0.13
0.90
C8
770
770.46
0.06
0.46
B5
852
850.45
−0.18
−1.55
A3
941
943.23
0.24
2.23
7F
1209
1206.45
−0.21
−2.55
72
1336
1341.66
0.42
5.66
67
1477
1482.21
0.35
5.21
5D
1633
1638.24
0.32
5.24
Table 8
Table 9
DTMF standard frequencies and their
implementation; value = LGF, HGF contents
FREQUENCY (Hz)
VALUE
(HEX) STANDARD GENERATED
Dialling symbols, corresponding DTMF
frequency pairs and frequency register contents
TELEPHONE DTMF FREQ.
KEYBOARD
PAIRS
SYMBOLS
(Hz)
LGF
VALUE
(HEX)
HGF
VALUE
(HEX)
Modem frequencies
Standard modem frequencies and their
implementation
FREQUENCY (Hz)
MODEM
978.82
−0.12
−1.18
82
1180(1)
1179.03
−0.08
−0.97
8F
1070(2)
1073.33
0.31
3.33
79
1270(2)
1265.30
−0.37
−4.70
80
1200(3)
1197.17
−0.24
−2.83
45
2200(3)
2192.01
−0.36
−7.99
76
1300(4)
1296.94
−0.24
−3.06
48
2100(4)
2103.14
0.15
3.14
5C
1650(1)
1655.66
0.34
5.66
52
1850(1)
1852.77
0.15
2.77
4B
2025(2)
2021.20
−0.19
−3.80
44
2225(2)
2223.32
−0.08
−1.68
Notes
1. Standard is V.21.
A3
72
2. Standard is Bell 103.
1
(697, 1209)
DD
7F
3. Standard is Bell 202.
2
(697, 1336)
DD
72
4. Standard is V.23.
3
(697, 1477)
DD
67
4
(770, 1209)
C8
7F
5
(770, 1336)
C8
72
6
(770, 1477)
C8
67
7
(852, 1209)
B5
7F
8
(852, 1336)
B5
72
9
(852, 1477)
B5
67
A
(697, 1633)
DD
5D
(770, 1633)
C8
5D
(852, 1633)
B5
5D
D
(941, 1633)
A3
5D
•
(941, 1209)
A3
7F
#
(941, 1477)
A3
67
1998 May 11
10
(Hz)
980(1)
(941, 1336)
B
(%)
9D
0
C
GENERATED
DEVIATION
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
6.6
PCD3359A
Musical scale frequencies
7
Finally, two octaves of musical scale in steps of semitones
can be realized, again assuming an oscillator frequency
fxtal = 3.58 MHz (Table 10). It is suggested to define the
frequency by the HGF register while the LGF contains
00H, disabling Low Group Frequency generation.
The PCD3359A has 128 bytes of Electrically Erasable
Programmable Read-Only Memory (EEPROM). Such
non-volatile storage provides data retention without the
need for battery backup. In telecom applications, the
EEPROM is used for storing redial numbers and for short
dialling of frequently used numbers. More generally,
EEPROM may be used for customizing microcontrollers,
such as to include a PIN code or a country code, to define
trimming parameters, to select application features from
the range stored in ROM.
Table 10 Musical scale frequencies and their
implementation
NOTE
HGF
VALUE
(HEX)
FREQUENCY (Hz)
STANDARD(1)
GENERATED
D#5
F8
622.3
622.5
E5
EA
659.3
659.5
F5
DD
698.5
697.9
F#5
D0
740.0
741.1
G5
C5
784.0
782.1
G#5
B9
830.6
832.3
A5
AF
880.0
879.3
A#5
A5
923.3
931.9
B5
9C
987.8
985.0
C6
93
1046.5
1044.5
C#6
8A
1108.7
1111.7
D6
82
1174.7
1179.0
D#6
7B
1244.5
1245.1
E6
74
1318.5
1318.9
F6
6D
1396.9
1402.1
F#6
67
1480.0
1482.2
G6
61
1568.0
1572.0
G#6
5C
1661.2
1655.7
A6
56
1760.0
1768.5
A#6
51
1864.7
1875.1
B6
4D
1975.5
1970.0
C7
48
2093.0
2103.3
C#7
44
2217.5
2223.3
D7
40
2349.3
2358.1
D#7
3D
2489.0
2470.4
The most significant difference between a RAM and an
EEPROM is that a bit in EEPROM, once written to a
logic 1, cannot be cleared by a subsequent write
operation. Successive write accesses actually perform a
logical OR with the previously stored information.
Therefore, to clear a bit, the whole byte must be erased
and re-written with the particular bit cleared. Thus, an
erase-and-write operation is the EEPROM equivalent of a
RAM write operation.
Whereas read access times to an EEPROM are
comparable to RAM access times, write and erase
accesses are much slower at 5 ms each. To make these
operations more efficient, several provisions are available.
First, the EEPROM array is structured into 32 four-byte
pages (see Fig.5) permitting access to 4 bytes in parallel
(write page, erase/write page and erase page). It is also
possible to erase and write individual bytes. Finally, the
EEPROM address register provides auto-incrementing,
allowing very efficient read and write accesses to
sequential bytes.
To simplify the erase and write timing, the derivative 8-bit
down-counter (Timer 2) with reload register is provided.
In addition to EEPROM timing, Timer 2 can be used for
general real-time tasks, such as for measuring signal
duration and for defining pulse widths.
Note
1. Standard scale based on A4 at 440 Hz.
1998 May 11
EEPROM AND TIMER 2 ORGANIZATION
11
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
handbook, full pagewidth
5
8
EEPROM ADDRESS REGISTER
2
2 : 4 DECODER
8
5 : 32 DECODER
EEPROM LATCH 0
F0
EEPROM LATCH 1
F1
128-byte EEPROM ARRAY
(32 4-byte PAGES)
EEPROM LATCH 2
F2
EEPROM LATCH 3
F3
8
8
EEPROM TEST REGISTER
8
EEPROM CONTROL REGISTER
8
T2F set on
underflow
TIMER 2 RELOAD REGISTER
8
8
TIMER 2 REGISTER (T2)
8
INTERNAL
BUS
MGB824
1
f
480 xtal
Fig.5 Block diagram of the EEPROM and Timer 2.
1998 May 11
12
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
7.1
PCD3359A
EEPROM registers
7.1.1
EEPROM CONTROL REGISTER (EPCR)
The behaviour of the EEPROM and Timer 2 section is defined by the EEPROM Control Register. See Tables 11, 12
and 13.
Table 11 EEPROM Control Register, EPCR (address 04H, access type R/W)
7
6
5
4
3
2
1
0
STT2
ET2I
T2F
EWP
MC3
MC2
MC1
0
Table 12 Description of EPCR bits
BIT
SYMBOL
DESCRIPTION
7
STT2
Start T2. If STT2 = 0, then Timer 2 is stopped; T2 value held. If STT2 = 1, then T2
decrements from reload value.
6
ET2I
Enable T2 interrupt. If ET2I = 0, then T2F event cannot request interrupt. If ET2I = 1,
then T2F event can request interrupt.
5
T2F
Timer 2 flag. Set when T2 underflows (or by program); reset by program.
4
EWP
Erase or write in progress. Set by program (EWP starts EEPROM erase and/or write
and Timer 2). Reset at the end of EEPROM erase and/or write.
3
MC3
2
MC2
Mode control 3 to 1. These three bits in conjunction with bit EWP select the mode as
shown in Table 13.
1
MC1
0
−
This bit is set to a logic 0.
Table 13 Mode selection; X = don’t care
EWP
MC3
MC2
MC1
0
0
0
0
read byte
0
0
1
0
increment mode
1
0
1
X
write page
1
1
0
0
erase/write page
1
1
1
1
erase page
X
0
0
1
not allowed
X
1
0
1
X
1
1
0
1998 May 11
DESCRIPTION
13
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
7.1.2
PCD3359A
EEPROM ADDRESS REGISTER (ADDR)
The EEPROM Address Register determines the EEPROM location to which an EEPROM access is directed.
As a whole, ADDR auto-increments after read and write cycles to EEPROM, but remains fixed after erase cycles. This
behaviour generates the correct ADDR contents for sequential read accesses and for sequential write or erase/write
accesses with intermediate page setup. Overflow of the 8-bit counter wraps around to zero.
Table 14 EEPROM Address Register, ADDR (address 01H, access type R/W)
7
6
5
4
3
2
1
0
0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Table 15 Description of ADDR bits
BIT
SYMBOL
7
−
6 to 2
AD6 to AD2
AD2 to AD6 select one of 32 pages.
1 to 0
AD1 to AD0
AD1 and AD0 are irrelevant during erase and write cycles. For read accesses, AD0 and
AD1 indicate the byte location within an EEPROM page. During page setup, finally, AD0
and AD1 select EEPROM Latch 0 to 3 whereas AD2 to AD6 are irrelevant. If increment
mode (Table 13) is active during page setup, the subcounter consisting of AD0 and AD1
increments after every write to an EEPROM latch, thus enhancing access to sequential
EEPROM latches. Incrementing stops when EEPROM Latch 3 is reached, i.e. when
AD0 and AD1 are both a logic 1.
7.1.3
DESCRIPTION
This bit is set to a logic 0.
EEPROM DATA REGISTER (DATR)
Table 16 EEPROM Data Register (address 03H; access type R/W)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Table 17 Description of DATR bits
BIT
SYMBOL
DESCRIPTION
7 to 0
D7 to D0
The EEPROM Data Register (DATR) is only a conceptual entity. A read operation from
DATR, reads out the EEPROM byte addressed by ADDR. On the other hand, a write
operation to DATR, loads data into the EEPROM latch (see Fig.5) defined by bits AD0
and AD1 of ADDR.
7.1.4
EEPROM TEST REGISTER (TST)
The EEPROM Test Register is used for testing purposes during device manufacture. It must not be accessed by the
device user.
7.2
EEPROM latches
The four EEPROM latches (EEPROM Latch 0 to 3; Fig.5) cannot be read by user software. Due to their construction, the
latches can only be preset, but not cleared. Successive write operations through DATR to the EEPROM latches actually
perform a logical OR with the previously stored data in EEPROM. The EEPROM latches are reset at the conclusion of
any EEPROM cycle.
1998 May 11
14
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
7.3
PCD3359A
Latch 0 to 3 (Fig.5) are ORed to the individual page bytes
if and only if the corresponding EEPROM flags are set.
EEPROM flags
The four EEPROM flags (F0 to F3; Fig.5) cannot be
directly accessed by user software. An EEPROM flag is
set as a side-effect when the corresponding EEPROM
latch is written through DATR. The EEPROM flags are
reset at the conclusion of any EEPROM cycle.
7.4
In an erase/write cycle, F0 to F3 select which page bytes
are erased and ORed with the corresponding EEPROM
latches.
ORing, in this event, means that the EEPROM latches are
copied to the selected page bytes.
EEPROM macros
The described page-wise organization of erase and write
cycles allows up to four bytes to be individually erased or
written within 5 ms. This advantage necessitates a
preparation step, called page setup, before the actual
erase and/or write cycle can be executed.
The instruction sequence used in an EEPROM access
should be treated as an indivisible entity. Erroneous
programs result if ADDR, DATR, RELR or EPCR are
inadvertently changed during an EEPROM cycle or its
setup. Special care should be taken if the program may
asynchronously divert due to an interrupt. Particularly, a
new access to the EEPROM may only be initiated when no
write, erase or erase/write cycles are in progress. This can
be verified by reading bit EWP (register EPCR).
Page setup controls EEPROM latches and EEPROM
flags. This will be described in the Sections 7.5.1 to 7.5.5.
7.5.1
Page setup is a preparation step required before write
page, erase page and erase/write page cycles.
As previously described, these page operations include
single-byte write, erase and erase/write as a special event.
EEPROM flags F0 to F3 determine which page bytes will
be affected by the mentioned page operations. EEPROM
Latch 0 to 3 must be preset through DATR to specify the
write cycle data to EEPROM and to set the EEPROM flags
as a side-effect. Obviously, the actual preset value of the
EEPROM latches is irrelevant for erase page. Preset of
one, two, three or all four EEPROM latches and the
corresponding EEPROM flags can be performed by
repeatedly defining ADDR and writing to DATR (see
Table 18).
For write, erase and erase/write cycles, it is assumed that
the Timer 2 Reload Register (RELR) has been loaded with
the appropriate value for a 5 ms delay, which depends on
fxtal (see Table 24). The end of a write, erase or erase/write
cycle will be signalled by a cleared EWP and by a Timer 2
interrupt provided that ET2I = 1 and that the SIO/derivative
interrupt is enabled.
7.5
EEPROM access
One read, one write, one erase/write and one erase
access are defined by bits EWP and MC1 to MC3 in the
EPCR register; see Table 11.
Read byte retrieves the EEPROM byte addressed by
ADDR when DATR is read. Read cycles are
instantaneous.
If more than one EEPROM latch must be preset, the
subcounter consisting of AD0 and AD1 can be induced to
auto-increment after every write to DATR, thus stepping
through all EEPROM latches. For this purpose, increment
mode (Table 13) must be selected. Auto-incrementing
stops at EEPROM Latch 3. It is not mandatory to start at
EEPROM Latch 0 as in shown in Table 19.
Write and erase cycles take 5 ms, however. Erase/write is
a combination of an erase and a subsequent write cycle,
consequently taking 10 ms.
As their names imply, write page, erase page and
erase/write page are applied to a whole EEPROM page.
Therefore, bits AD0 and AD1 of register ADDR (see
Table 14), defining the byte location within an EEPROM
page, are irrelevant during write and erase cycles.
However, write and erase cycles need not affect all bytes
of the page. The EEPROM flags F0 to F3 (see Fig.5)
determine which bytes within the EEPROM page are
affected by the erase and/or write cycles. A byte whose
corresponding EEPROM flag is zero remains unchanged.
Note that AD2 to AD6 are irrelevant during page setup.
They will usually specify the intended EEPROM page,
anticipating the subsequent page cycle.
From now on, it will be assumed that AD2 to AD6 will
contain the intended EEPROM page address after page
setup.
With erase page, a byte is erased if its corresponding
EEPROM flag is set. With write page, data in EEPROM
1998 May 11
PAGE SETUP
15
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
The EEPROM latches are preset as described in
Section 7.5.1. The actual transfer to the EEPROM is then
performed as shown in Table 21.
Table 18 Page setup; preset
INSTRUCTION
RESULT
MOV A, #addr
address of EEPROM latch
MOV ADDR, A
send address to ADDR
MOV A, #data
load write, erase/write or erase data
MOV DATR, A
send data to addressed EEPROM
latch
The last instruction also starts Timer 2. The data in the
EEPROM latches are ORed with that in the corresponding
page bytes within 5 ms. A single-byte write is simply a
special case of ‘write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM Latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by bits AD2
to AD6) and to EEPROM Latch 0 (by bits AD0 and AD1).
This allows efficient coding of multi-page write operations.
Table 19 Page setup; auto-incrementing
INSTRUCTION
RESULT
MOV A, #MC2
increment mode control word
MOV EPCR, A
select increment mode
MOV A, #baddr
EEPROM Latch 0 address
(AD0 = AD1 = 0)
MOV ADDR, A
send EEPROM Latch 0 address to
ADDR
MOV A, R0
load 1st byte from Register 0
MOV DATR, A
send 1st byte to EEPROM Latch 0
MOV A, R1
load 2nd byte from Register 1
MOV DATR, A
send 2nd byte to EEPROM Latch 1
MOV A, R2
load 3rd byte from Register 2
MOV DATR, A
send 3rd byte to EEPROM Latch 2
MOV A, R3
load 4th byte from Register 3
MOV DATR, A
send 4th byte to EEPROM Latch 3
7.5.2
Table 21 Write page
INSTRUCTION
start ‘write page’ cycle
ERASE/WRITE PAGE
The last instruction also starts Timer 2. Erasure takes
5 ms upon which Timer Register T2 reloads for another
5 ms cycle for writing. The top cycles together take 10 ms.
A single-byte erase/write is simply a special event of
‘erase/write page’.
ADDR auto-increments after the write cycle. If AD0 and
AD1 addressed EEPROM latch 3 prior to the write cycle,
ADDR will point to the next EEPROM page (by AD2 to
AD6) and to EEPROM latch 0 (by AD0 and AD1).
This allows efficient coding of multi-page erase/write
operations.
Table 20 Read byte
RESULT
Table 22 Erase/write page
MOV A, #RDADDR load read address
MOV ADDR, A
send address to ADDR
MOV A, DATR
read EEPROM data
INSTRUCTION
WRITE PAGE
The write cycle performs a logical OR between the data in
the EEPROM latches and that in the addressed EEPROM
page. To actually copy the data from the EEPROM
latches, the corresponding bytes in the page should
previously have been erased.
1998 May 11
‘write page’ control word
MOV EPCR, A
The EEPROM latches are preset as described in
Section 7.5.1. The page byte corresponding to the
asserted flags (among F0 to F3) are erased and re-written
with the contents of the respective EEPROM latches.
Since ADDR auto-increments after a read cycle regardless
of the page boundary, successive bytes can efficiently be
read by repeating the last instruction.
7.5.3
MOV A, #EWP + MC2
7.5.4
READ BYTE
INSTRUCTION
RESULT
16
RESULT
MOV A, #EWP + MC3
‘erase/write page’ control word
MOV EPCR, A
start ‘erase/write page’ cycle
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
7.5.5
PCD3359A
ERASE PAGE
Table 24 Reload values as a function of fxtal
The EEPROM flags are set as described in Section 7.5.1.
The corresponding page bytes are erased.
fxtal
(MHz)
RELOAD VALUE(1)
(HEX)
The last instruction also starts Timer 2. Erasure takes
5 ms. A single-byte erase is simply a special case of ‘erase
page’.
1
0A
2
14
3.58
25
Note that ADDR does not auto-increment after an erase
cycle.
Table 23 Erase page
INSTRUCTION
6
3E
10
68
16
A6
Note
RESULT
MOV A, #EWP + MC3 + MC2 + MC1
‘erase page’
control word
1. The reload value is (5 × 10−3 × 1⁄480 fxtal) − 1;
fxtal in MHz.
MOV EPCR, A
start ‘erase
page’ cycle
7.6.2
7.6
When used for purposes other than EEPROM timing,
Timer 2 is started by setting STT2. The Timer Register T2
(see Table 26) is loaded with the reload value from RELR.
T2 decrements to zero. On underflow, T2 is reloaded from
RELR, T2F is set and T2 continues to decrement.
Timer 2
Timer 2 is a 8-bit down-counter decremented at a rate of
1⁄
480 × fxtal. It may be used either for EEPROM timing or as
a general purpose timer. Conflicts between the two
applications should be carefully avoided.
7.6.1
Timer 2 can be stopped at any time by clearing STT2.
The value of T2 is then held and can be read out. After
setting STT2 again, Timer 2 decrements from the reload
value. Alternatively, it is possible to read T2 ‘on the fly’ i.e.
while Timer 2 is operating.
TIMER 2 FOR EEPROM TIMING
When used for EEPROM timing, Timer 2 serves to
generate the 5 ms intervals needed for erasing or writing
the EEPROM. At the decrement rate of 1⁄480 × fxtal, the
reload value for a 5 ms interval is a function of fxtal.
Table 24 summarizes the required reload values for a
number of oscillator frequencies.
Timer 2 is started by setting bit EWP in the EPCR.
The Timer Register T2 is loaded with the reload value from
RELR. T2 decrements to zero.
For an erase/write cycle, underflow of T2 indicates the end
of the erase operation. Therefore, Timer Register T2 is
reloaded from RELR for another 5 ms interval during
which the flagged EEPROM latches are copied to the
corresponding bytes in the page addressed by ADDR.
The second underflow of an erase/write cycle and the first
underflow of write page and erase page conclude the
corresponding EEPROM cycle. Timer 2 is stopped, T2F is
set whereas EWP and MC1 to MC3 are cleared.
1998 May 11
TIMER 2 AS A GENERAL PURPOSE TIMER
17
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
8
8.1
PCD3359A
The Port 0 Wake-up interrupts are controlled by the
Enable Port 0 Interrupt bits EPI3 to EPI0 in the
Melody and Port Interrupt Control Register MDYCON.
Pairs of Port 0 interrupts are individually enabled/disabled
via bits 4, 5, 6 and 7. For details see Section 6.1.2. As the
Port 0 interrupt is directly linked to the external interrupt, it
uses the same flag (EIF), enable instructions (EN I, DIS I)
and interrupt vector.
INTERRUPTS
Derivative interrupt
One derivative interrupt event is defined. It is controlled by
bits T2F and ET2I in the EPCR (see Tables 11 and 12).
The derivative interrupt event occurs when T2F is set. This
request is honoured under the following circumstances:
• No interrupt routine proceeds
A Port 0 Wake-up interrupt is serviced if:
• No external interrupt request is pending
• No interrupt routine is in progress
• The derivative interrupt is enabled
• The external interrupt is enabled
• ET2I is set.
• It’s corresponding enable bit in register MDYCON is set
to a logic 1.
The derivative interrupt routine must include instructions
that will remove the cause of the derivative interrupt by
explicitly clearing T2F. If the derivative interrupt is not
used, T2F may directly be tested by the program.
Obviously, T2F can also be asserted under program
control, e.g. to generate a software interrupt.
8.2
If a Port 0 interrupt is to be used, the port flip-flop must first
be set to a logic 1 (set to input mode) before it’s
corresponding EPIn
bit is set.
If only a portion of the Port 0 interrupts are used, the
remaining port lines may still be used as normal I/O.
Port 0 Wake-up interrupts
In addition to the external interrupt CE, the PCD3359A
contain 8 level-sensitive external interrupt sources on
Port 0. This function generates an interrupt request if any
of the enabled lines of Port 0 (P0.0 to P0.7) is pulled LOW.
Like the external interrupt (and contrary to the derivative
interrupt) the Port 0 interrupt operates also in Stop mode
and forces the CPU to exit the Stop mode.
In order to configure an I/O as an input, a logic 1 must first
be written to it. If a logic 0 is written to one of these port
lines (e.g. ANL P0, 00H) while it’s corresponding interrupt
is enabled, a Port 0 interrupt will be generated.
For more details see data sheet “PCD33xxA Family;
Section External Interrupt”.
handbook,
halfpage
CE/T0 (1)
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
EPI3
EPI2
to CE/T0 input of
Digital filter/latch of the
Interrup logic section (2)
EPI1
EPI0
MGB825
(1) From pin CE/T0.
(2) See the “PCD33XXA Family” data sheet.
Fig.6 Simplified External/Port 0 interrupt structure.
1998 May 11
18
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
9
PCD3359A
zero. The Timer 2 section is frozen during Stop mode.
After exit from Stop mode by a HIGH level on CE/T0,
Timer 2 proceeds from the held state.
TIMING
Although the PCD3359A operates over a clock frequency
range from 1 to 16 MHz, fxtal = 3.58 MHz will usually be
chosen to take full advantage of the frequency generator
section.
The Port 0 Wake-up interrupt function remains operative
during Stop mode (depending only on the EPIn bits in
register MDYCON). In addition to the description in the
“PCD33xxA family” data sheet, Stop mode may be left by
a Port 0 Wake-up interrupt event (see Section 8.2).
10 RESET
In addition to the conditions given in the “PCD33XXA
Family” data sheet, all derivative registers are cleared in
the reset state.
13 INSTRUCTION SET RESTRICTIONS
Please note the following:
• ROM space being restricted to 2 kbytes, the
‘SEL MB1/2/3’ instructions would define non-existing
program memory banks and should therefore be
avoided
11 IDLE MODE
In Idle mode, the frequency generator, the EEPROM and
the Timer 2 sections remain operative. Therefore, the
IDLE instruction may be executed while an erase and/or
write access to EEPROM is in progress.
• RAM space being restricted to 64 bytes, care should be
taken to avoid accesses to non-existing RAM locations.
12 STOP MODE
14 OVERVIEW OF PORT AND POWER-ON-RESET
CONFIGURATION
Since the oscillator is switched off, the frequency
generator, the EEPROM and the Timer 2 sections receive
no clock. It is suggested to clear both the HGF and the
LGF registers before entering Stop mode. This will cut off
the biasing of the internal amplifiers, considerably
reducing current requirements.
All standard quasi-bidirectional I/O ports are available; see
“PCD33xxA family” data sheet.
• Port 0: 8 parallel port lines P0.0 to P0.7 or wake-up
interrupts
• Port 1: 8 parallel port lines P1.0 to P1.7
The Stop mode must not be entered while an erase
and/or write access to EEPROM is in progress. The STOP
instruction may only be executed when EWP in EPCR is
• Port 2: 4 parallel port lines P2.0 to P2.3.
Table 25 Port and Power-on-reset configuration
See notes 1 and 2.
COVERED
BY OTP
PORT 0
0
1
2
3
4
PORT 1
5
6
7
0
1
2
3
4
PORT 2
5
6
PCD3756A 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R
7
0
1
2
3
1R(3) 2S
2S
2S
2S
Notes
1. Port output drive: 1 = standard I/O; 2 = open-drain I/O, see “PCD33xxA family” data sheet.
2. Port state after reset: S = Set (HIGH) and R = Reset (LOW).
3. The melody output drive type is push-pull.
1998 May 11
19
VPOR
1.3 V
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
15 SUMMARY OF DERIVATIVE REGISTERS
Table 26 Register map
ADDR.
(HEX)
REGISTER
00
not used
01
EEPROM Address Register (ADDR)
02
not used
03
EEPROM Data Register (DATR)
04
EEPROM Control Register (EPCR)
05
Timer 2 Reload Register (RELR)
06
Timer 2 Register (T2)
07
Test Register (TST)
08 to 10
7
6
5
4
3
2
1
0
R/W
0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
R/W
STT2 ET21
TF2
EWP
MC3
MC2
MC1
0
R/W
R7
R6
R5
R4
R3
R2
R1
R0
R/W
T2.7
T2.6
T2.5
T2.4
T2.3
T2.2
T2.1
T2.0
R
only for test purposes; not to be accessed by the device user
not used
11
High Group Frequency Register (HGF)
H7
H6
H5
H4
H3
H2
H1
H0
W
12
Low Group Frequency Register (LGF)
L7
L6
L5
L4
L3
L2
L1
L0
W
13
Melody and Port Interrupt Control
Register (MDYCON)
EPI3
EPI2
EPI1
EPI0
0
0
0
EMO
R/W
14 to FF
not used
16 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see “Data Handbook IC14, Section: Handling MOS devices”).
17 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
VDD
supply voltage
−0.8
MAX.
UNIT
+7.0
V
VI
all input voltages
−0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
Ptot
total power dissipation
−
125
mW
PO
power dissipation per output
−
30
mW
ISS
ground supply current
−50
+50
mA
Tstg
storage temperature
−65
+150
°C
Tj
operating junction temperature
−
90
°C
1998 May 11
20
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
18 DC CHARACTERISTICS
VDD = 1.8 to 6 V; VSS = 0 V; Tamb = −25 to +70 °C; all voltages with respect to VSS; fxtal = 3.58 MHz; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
operating
see Fig.7
1.8
−
6
V
1.0
−
6
V
VDD = 3 V; value HGF or LGF ≠ 0
−
0.8
1.6
mA
note 1
RAM data retention in Stop
mode
IDD
IDD(idle)
IDD(stp)
operating supply current
supply current (Idle mode)
supply current (Stop mode)
see Figs 8 and 9; note 2
VDD = 3 V
−
0.35
0.7
mA
VDD = 5 V; fxtal = 10 MHz
−
1.5
4.0
mA
VDD = 5 V; fxtal = 16 MHz
−
2.4
6.0
mA
VDD = 3 V; value HGF or LGF ≠ 0
−
0.7
1.4
mA
VDD = 3 V
−
0.25
0.5
mA
VDD = 5 V; fxtal = 10 MHz
−
1.1
3.4
mA
VDD = 5 V; fxtal = 16 MHz
−
1.7
5.0
mA
see Figs 10 and 11; note 2
see Fig.12; note 3
VDD = 1.8 V; Tamb = 25 °C
−
1.0
5.5
µA
VDD = 1.8 V; Tamb = 70 °C
−
−
10
µA
−
0.3VDD V
Inputs
VIL
LOW level input voltage
0
VIH
HIGH level input voltage
0.7VDD −
VDD
V
ILI
input leakage current
VSS ≤ VI ≤ VDD
−1
−
+1
µA
Port outputs
IOL
LOW level port sink current
VDD = 3 V; VO = 0.4 V; see Fig.13
0.7
3.5
−
mA
IOH
HIGH level pull-up output
source current
VDD = 3 V; VO = 2.7 V; see Fig.14
−10
−30
−
µA
VDD = 3 V; VO = 0 V; see Fig.14
−
−140
−300
µA
IOH1
HIGH level push-pull output
source current
VDD = 3 V; VO = 2.6 V; see Fig.15
−0.7
−3.5
−
mA
Tone output (see Fig.16; note 4)
VHG(RMS)
HGF voltage (RMS value)
158
181
205
mV
VLG(RMS)
LGF voltage (RMS value)
125
142
160
mV
∆f ⁄ f
frequency deviation
−0.6
−
+0.6
%
VDC
DC voltage level
−
0.5VDD −
V
Zo
output impedance
−
100
500
Ω
Gv
pre-emphasis of group
1.5
2.0
2.5
dB
THD
total harmonic distortion
−
25
−
dB
1998 May 11
Tamb = 25 °C; note 5
21
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
SYMBOL
PARAMETER
PCD3359A
CONDITIONS
MIN.
TYP.
MAX.
UNIT
EEPROM (notes 1 and 6)
CYt/w
endurance (erase/write cycles) note 7
105
−
−
tret
data retention time
10
−
−
years
configuration as PCD3756A;
(see Table 25)
0.8
1.3
1.8
V
VDD = 5 V
0.2
0.4
1.0
mS
0.3
1.0
3.0
MΩ
Power-on reset (see Fig.17)
VPOR
Power-on-reset level
Oscillator (see Fig.18)
gm
transconductance
RF
feedback resistor
Notes
1. TONE output, EEPROM erase and write require VDD ≥ 2.5 V.
2. VIL = VSS; VIH = VDD; open-drain outputs connected to VSS; all other outputs open; value HGF = LGF = 0, unless
otherwise specified.
a) Maximum values: external clock at XTAL1 and XTAL2 open-circuit.
b) Typical values: Tamb = 25 °C; crystal connected between XTAL1 and XTAL2.
3. VIL = VSS; VIH = VDD; RESET, T1 and CE/T0 at VSS; crystal connected between XTAL1 and XTAL2; pins T1 and
CE/T0 at VSS.
4. Values are specified for DTMF frequencies only (CEPT).
5. Related to the Low Group Frequency (LGF) component (CEPT).
6. After final testing the value of each EEPROM bit is a logic 1, but this cannot be guaranteed after board assembly.
7. Verified on sampling basis.
1998 May 11
22
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
MLA493
18
MGB827
6
handbook,
halfpage
f
handbook, halfpage
xtal
(MHz)
15
IDD
(mA)
16 MHz
4
12
9
3.58 MHz
HGF or LGF ≠ 0
guaranteed
operating range
6
10 MHz
2
3.58 MHz
3
0
0
1
1
3
5
3
5
7
VDD (V)
VDD (V)
7
Measured with crystal between XTAL1 and XTAL2.
Fig.7
Maximum clock frequency (fxtal) as a
function of supply voltage (VDD).
Fig.8
MGB828
6
Typical operating supply current (IDD) as a
function of supply voltage (VDD).
MGB829
6
handbook, halfpage
handbook, halfpage
IDD
(mA)
IDD(idle)
(mA)
4
4
16 MHz
5V
3.58 MHz
HGF or LGF ≠ 0
2
2
10 MHz
3V
3.58 MHz
0
1
10
fxtal (MHz)
10
0
2
1
3
5
VDD (V)
7
Measured with function generator on XTAL1.
Measured with crystal between XTAL1 and XTAL2.
Fig.9
Fig.10 Typical supply current in Idle mode (IDD(idle))
as a function of supply voltage (VDD).
Typical operating supply current (IDD) as a
function of clock frequency (fxtal).
1998 May 11
23
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
MGB826
MGB830
6
6
handbook, halfpage
handbook, halfpage
IDD(idle)
(mA)
IDD(stp)
(µA)
5
4
4
3
2
2
5V
1
3V
0
1
10
fxtal (MHz)
10
0
2
1
3
5
VDD (V)
7
Measured with function generator on XTAL1.
Fig.11 Typical supply current in Idle mode
(IDD(idle))as a function of clock frequency
(fxtal).
Fig.12 Typical supply current in Stop mode
(IDD(stp)) as a function of supply voltage
(VDD).
MGB831
MGB832
−300
12
handbook, halfpage
handbook, halfpage
IOL
(mA)
IOH
(µA)
8
−200
4
−100
VO = 0 V
VO = 0.9VDD
0
0
1
3
5
VDD (V)
7
1
VO = 0.4 V.
5
VDD (V)
7
Fig.14 Typical HIGH level pull-up output source
current (IOH) as a function of supply voltage
(VDD).
Fig.13 Typical LOW level output sink current (IOL)
as a function of supply voltage (VDD).
1998 May 11
3
24
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
MGB833
−12
handbook, halfpage
IOH1
(mA)
handbook, halfpage VDD
−8
DEVICE TYPE NUMBER
(1)
TONE
1 µF
10 kΩ
50 pF
−4
VSS
MGB835
0
1
3
5
VDD (V)
7
VO = VDD − 0.4 V.
Fig.15 Typical HIGH level push-pull output source
current (IOH1) as a function of supply voltage
(VDD).
(1) Device type number: PCD3359A.
Fig.16 TONE output test circuit.
MGD494
6
MGB834
10
handbook, halfpage
handbook, halfpage
VDD
(V)
gm
(mS)
4
1
2
VPOR = 1.3 V
0
−25
10
25
75 T
125
amb (°C)
70
Fig.17 Typical Power-on-reset level (VPOR) as
function of ambient temperature (Tamb).
1998 May 11
1
1
3
5
VDD (V)
7
Fig.18 Typical transconductance as a function of
supply voltage (VDD).
25
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
19 AC CHARACTERISTICS
VDD = 1.8 to 6 V; VSS = 0 V; Tamb = −25 to +70 °C; all voltages with respect to VSS; unless otherwise specified.
SYMBOL
PARAMETER
tr
rise time all outputs
tf
fall time all outputs
fxtal
clock frequency
1998 May 11
CONDITIONS
VDD = 5 V; Tamb = 25 °C; CL = 50 pF
see Fig.7
26
MIN.
TYP.
MAX.
UNIT
−
30
−
ns
−
30
−
ns
1
−
16
MHz
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
20 PACKAGE OUTLINES
seating plane
handbook, full
pagewidthdual in-line package; 28 leads (600 mil)
DIP28:
plastic
SOT117-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
15
28
pin 1 index
E
1
14
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
5.1
0.51
4.0
1.7
1.3
0.53
0.38
0.32
0.23
36.0
35.0
14.1
13.7
2.54
15.24
3.9
3.4
15.80
15.24
17.15
15.90
0.25
1.7
inches
0.20
0.020
0.16
0.066
0.051
0.020
0.014
0.013
0.009
1.41
1.34
0.56
0.54
0.10
0.60
0.15
0.13
0.62
0.60
0.68
0.63
0.01
0.067
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT117-1
051G05
MO-015AH
1998 May 11
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-01-14
27
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
SO28: plastic small outline package; 28 leads; body width 7.5 mm
SOT136-1
D
E
A
X
c
y
HE
v M A
Z
15
28
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
14
e
bp
0
detail X
w M
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.30
0.10
2.45
2.25
0.25
0.49
0.36
0.32
0.23
18.1
17.7
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.10
0.012 0.096
0.004 0.089
0.01
0.019 0.013
0.014 0.009
0.71
0.69
0.30
0.29
0.419
0.043
0.050
0.055
0.394
0.016
inches
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT136-1
075E06
MS-013AE
1998 May 11
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-24
97-05-22
28
o
8
0o
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y
X
24
A
17
25
16
ZE
e
E HE
A A2 A
1
(A 3)
wM
θ
bp
Lp
L
pin 1 index
32
9
detail X
8
1
e
ZD
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.4
0.3
0.18
0.12
7.1
6.9
7.1
6.9
0.8
9.15
8.85
9.15
8.85
1.0
0.75
0.45
0.2
0.25
0.1
Z D (1) Z E (1)
0.9
0.5
0.9
0.5
θ
o
7
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-12-19
97-08-04
SOT358 -1
1998 May 11
EUROPEAN
PROJECTION
29
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.
21 SOLDERING
21.1
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
21.3.2
21.3.2.1
21.2.1
CAUTION
DIP
Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
21.2.2
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
21.3.2.2
REPAIRING SOLDERED JOINTS
21.3.1
SO
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
21.3
LQFP
Wave soldering is not recommended for LQFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
21.2
WAVE SOLDERING
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
LQFP and SO
• The package footprint must incorporate solder thieves at
the downstream end.
REFLOW SOLDERING
Reflow soldering techniques are suitable for all LQFP and
SO packages.
21.3.2.3
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
1998 May 11
30
Method (LQFP and SO)
Philips Semiconductors
Product specification
8-bit microcontroller with DTMF
generator and 128 bytes EEPROM
PCD3359A
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
21.3.3
REPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
22 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
23 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 May 11
31
Philips Semiconductors – a worldwide company
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Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
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Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
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Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
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Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
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Printed in The Netherlands
415102/1200/04/pp32
Date of release: 1998 May 11
Document order number:
9397 750 03731