INTEGRATED CIRCUITS PCK2020 CK00 (100/133MHz) spread spectrum differential system clock generator Product specification Supersedes data of 2000 Jul 25 2000 Nov 13 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator FEATURES PCK2020 PIN CONFIGURATION • 3.3 V operation • Four differential CPU clock pairs • Ten PCI clocks at 3.3 V • Four 66 MHz clocks at 3.3 V • Two 48 MHz clocks at 3.3 V • Two 14.318 MHz reference clocks • 100 or 133 MHz operation • Power management control pins • CPU clock skew less than 200 ps cycle-to-cycle • CPU clock skew less than 150 ps pin-to-pin • 1.5 ns to 3.5 ns delay on PCI pins • Spread Spectrum capability VSSRef 1 56 VDD3.3M Ref0/MultSel0 2 55 3VMref Ref1/MultSel1 3 54 3VMref_b VDD3.3Ref 4 53 VSSM XTAL_IN 5 52 SPREAD XTAL_OUT 6 51 CPUCLK0 VSSPCI 7 50 CPUCLK0 PCICLK0 8 49 VDD3.3CPU PCICLK1 9 48 CPUCLK1 VDD3.3PCI 10 PCICLK2 11 DESCRIPTION The PCK2020 is a clock synthesizer/driver for a Pentium III and other similar processors. The PCK2020 has four differential pair CPU current source outputs, two Mref clock outputs running at 1/2 the CPU clock frequency depending on the state of SEL133/100 pin and four 3V66 clocks running at 66 MHz. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. Finally, there are two 3.3 V reference clocks at 14.318 MHz. All clock outputs meet Intel’s drive strength, rise/fall times, jitter, accuracy, and skew requirements. 46 VSSCPU PCICLK3 12 45 CPUCLK2 VSSPCI 13 44 CPUCLK2 PCICLK4 14 43 VDD3.3CPU PCICLK5 15 42 CPUCLK3 VDD3.3PCI 16 41 CPUCLK3 PCICLK6 17 40 VSSCPU PCICLK7 18 39 I_REF VSSPCI 19 The part possesses a dedicated power-down input pin for power management control. This input is synchronized on-chip and ensures glitch-free output transitions. 47 CPUCLK1 38 VDD3.3Core PCICLK8 20 37 VSSCore PCICLK9 21 36 VDD3.3 VDD3.3PCI 22 35 3V66_0 SEL100/133 23 34 3V66_1 VSSUSB 24 33 VSS 48MHz0/SelA 25 32 VSS 48MHz1/SelB 26 31 3V66_2 VDD3.3USB 27 30 3V66_3 PWRDWN 28 29 VDD3.3 SW00577 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE (°C) ORDER CODE DRAWING NUMBER 56-Pin Plastic SSOP 0 to +70 PCK2020 DL SOT371-1 Intel and Pentium are registered trademarks of Intel Corporation. 2000 Nov 13 2 853-2209 25006 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 PIN DESCRIPTION PIN NUMBER SYMBOL 1 VSSRef 2, 3 Ref0/MultSel0 Ref1/MultSel1 4 VDD3.3Ref 5 XTAL_IN 6 XTAL_OUT 7, 13, 19 VSSPCI 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 PCICLK[0–9] 10, 16, 22 VDD3.3PCI 23 SEL100/133 24 VSSUSB 25, 26 48 MHz/SelA 48 MHz/SelB 27 VDD3.3USB 28 PWRDWN 29, 36 VDD3.3 30, 31, 34, 35 3V66[0–3] 32, 33 VSS 37 VSSCore 38 VDD3.3Core 39 I_REF FUNCTION During power up, pins functions as a latched inputs that enables MULTSEL0 and MULTSEL1 prior to the pins being used for output of 3 V at 14.318 MHz. Part must be clocked to latch data in. Crystal input Crystal output 3.3 V PCI clock outputs fixed at 33 MHz. Select input pin for enabling 133 MHz or 100 MHz CPU outputs. 3.3 V fixed 48 MHz clock outputs. During power up, pins functions as latched inputs that enables SELA and SELB prior to the pins being used for output of 3 V at 48 MHz. Part must be clocked to latch data in. Device enters power down mode when held low. Asserts low. 3.3 V fixed 66 MHz CPU clock outputs. 3.3 V power supply for analog circuits. This pin controls the reference current for the host pairs. This pin requires a fixed precision resistor tied to ground in order to establish the correct current. 40, 46 VSSCPU 41, 44, 47, 50 CPUCLK[0–3] 42, 45, 48, 51 CPUCLK[0–3] 43, 49 VDD3.3CPU 52 SPREAD 53 VSSM 54 3VMref_b 3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on the state of input pin SEL133/100. (Out of phase with 3VMREF output). 55 3VMref 3.3 V clock outputs running at 1/2 CPU clock frequency. 66 MHz or 50 MHz depending on the state of input pin SEL133/100. 56 VDD3.3M 2000 Nov 13 Enables spread spectrum mode when held low on differential host outputs, MREF/MREF_B clocks, 66 MHz clocks, and 33 MHz PCI clocks. Asserts low. 3.3 V power supply 3 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 BLOCK DIAGRAM PWRDWN X REF [0–1](14.318 MHz) XIN X XOUT X 14.318 MHZ OSC PWRDWN USBPLL X 48 MHz[0–1] 3 V X CPUCLK [0–3] PWRDWN SYSPLL SPREAD X X CPUCLK [0–3] PWRDWN SEL 133/100 X SEL0 X X 3V66 [0–3] (66 MHz) DECODE LOGIC SEL1 X PWRDWN PWRDWN X 3VMRef X PCICLK_F (33 MHz) PWRDWN X PWRDWN PWRDWN X 3VMRef X PCICLK_F (33 MHz) SW00727 2000 Nov 13 4 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 FUNCTION TABLES SEL 100/133 SELA SELB 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 HOST MREF 3V66 3V33 PCI 48 MHz REF 100 MHz 50 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz 105 MHz1 52.5 MHz1 70 MHz1 35 MHz1 48 MHz 14.318 MHz 200 MHz 50 MHz 66.7 MHz 33.3 MHz N/A N/A HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 133 MHz 66.7 MHz 66.7 MHz 33.3 MHz 48 MHz 14.318 MHz MHz1 MHz1 MHz1 126.7 MHz1 1 0 1 48 MHz 14.318 MHz 1 1 0 200 MHz 63.3 66.7 MHz 63.3 66.7 MHz 31.7 33.3 MHz 48 MHz 14.318 MHz 1 1 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK NOTE: 1. These frequencies are for debug and thus can vary a small amount from the values listed at the vendor’s discretion. SEL 100/133 SELA SELB 0 0 0 Active 100 MHz 0 0 1 Active 100 MHz – ~5% over-clock 0 1 0 200 MHz, 50 MHz MREF 0 1 1 HI-Z all outputs 1 0 0 Active 133 MHz 1 0 1 Active 133.3 MHz minus ~5 under-clock 1 1 0 200 MHz, 66 MHz MREF 1 1 1 Test mode HOST POWER DOWN MODE PWRDWN HOST/HOST_BAR MREF/MREF_B 3V66 PCI 48 MHz REF 14.318/66 MHz Seeds Asserts low 0 = Active HOST = 2*IREF HOST_BAR LOW LOW LOW LOW OFF LOW/(if applicable) NOTE: 1. The differential outputs should have a voltage forced across them when power down is asserted. SPREAD SPECTRUM FUNCTION TABLE SPREAD FUNCTION 48 MHz PLL REF/MULTSEL0 REF/MULTSEL1 1 HOST/PCI/3V66/MREF/MREF_B No spread No spread 0 HOST/PCI/3V66/MREF/MREF_B Down spread –0.5% No spread 2000 Nov 13 5 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 HOST SWING SELECT FUNCTIONS – TABLE 1 MULTSEL0 MULTSEL1 BOARD IMPEDANCE 0 0 0 IREF IOH VOH @ IREF = 2.32 mA 60 Ω RREF = 475 1% IREF = –2.32 mA IOH = 5*IREF 0.71 V 0 50 Ω RREF = 475 1% IREF = –2.32 mA IOH = 5*IREF 0.59 V 0 1 60 Ω RREF = 475 1% IREF = –2.32 mA IOH = 6*IREF 0.85 V 0 1 50 Ω RREF = 475 1% IREF = –2.32 mA IOH = 6REF 0.71 V 1 0 60 Ω RREF = 475 1% IREF = –2.32 mA IOH = 4*IREF 0.56 V 1 0 50 Ω RREF = 475 1% IREF = –2.32 mA IOH = 4*IREF 0.47 V 1 1 60 Ω RREF = 475 1% IREF = –2.32 mA IOH = 7*IREF 0.99 V 1 1 50 Ω RREF = 475 1% IREF = –2.32 mA IOH = 7*IREF 0.82 V 0 0 30 Ω RREF = 221 1% IREF = –5 mA IOH = 5*IREF 0.75 V 0 0 25 Ω RREF = 221 1% IREF = –5 mA IOH = 5*IREF 0.62 V 0 1 30 Ω RREF = 221 1% IREF = –5 mA IOH = 6*IREF 0.90 V 0 1 25 Ω RREF = 221 1% IREF = –5 mA IOH = 6*IREF 0.75 V 1 0 30 Ω RREF = 221 1% IREF = –5 mA IOH = 4*IREF 0.60 V 1 0 25 Ω RREF = 221 1% IREF = –5 mA IOH = 4*IREF 0.50 V 1 1 30 Ω RREF = 221 1% IREF = –5 mA IOH = 7*IREF 1.05 V 1 1 25 Ω RREF = 221 1% IREF = –5 mA IOH = 7*IREF 0.84 V NOTE: 1. In Table 1, the outputs are optimized for the configurations in bold. CONDITIONS CONFIGURATION LOAD MIN. MAX. IOUT VDD = 3.3 V All combinations, see Table 1 Nominal test load for given configuration –7% of IOH See Table 1 +7% of IOH See Table 1 IOUT VDD = 3.3 V ±5% All combinations, see Table 1 Nominal test load for given configuration –12% of IOH See Table 1 +12% of IOH See Table 1 2000 Nov 13 6 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL PARAMETER VDD3 DC 3.3 V supply IIK DC input diode current LIMITS CONDITION MAX –0.5 +4.6 V –50 mA ±50 mA VI < 0 VI DC input voltage Note 2 IOK DC output diode current VO > VDD or VO < 0 VO DC output voltage Note 2 IO DC output source or sink current VO = 0 to VDD TSTG Storage temperature range PTOT Power dissipation per package plastic medium-shrink (SSOP) UNIT MIN V –0.5 VDD + 0.5 V ±50 mA +150 °C 850 mW –65 For temperature range: –40 to +125°C above +55°C derate linearly with 11.3 mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT VDD3 DC 3.3 V supply voltage 3.135 3.465 V AVDD DC 3.3 V analog supply voltage 3.135 3.465 V 10 10 10 10 10 30 30 20 20 30 pF pF pF pF pF 14.31818 14.31818 MHz 0 +70 °C Capacitive load on: CL PCICLK 3V66 48 MHz clock REF MREF, MREF_BAR fREF Reference frequency, oscillator normal value Tamb Operating ambient temperature range in free air Must meet PCI 2.1 requirements 1 device load, possible 2 loads 1 device load 1 device load 1 device load POWER MANAGEMENT CONDITION MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDDL= 3.465 V ALL STATIC INPUTS = VDD3 OR VSS Power-down mode (PWRDWN = 0) 60 mA Full active 100/133 MHz 250 mA 2000 Nov 13 7 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 DC CHARACTERISTICS SYMBOL LIMITS TEST CONDITIONS PARAMETER VDD (V) Tamb = 0°C to +70°C OTHER MIN TYP UNIT MAX VIH HIGH level input voltage 3.135 to 3.465 2.0 VDD3 + 0.3 V VIL LOW level input voltage 3.135 to 3.465 VSS – 0.3 0.8 V VOH3 3.3 V output HIGH voltage REF, 3V48M, 3V66, MREF, MREF_BAR, 48 MHz 3.135 to 3.465 IOH = –1 mA 2.0 – V VOL3 3.3 V output LOW voltage REF, 3V48M, 3V66, MREF, MREF_BAR, 48 MHz 3.135 to 3.465 IOH = 1 mA – 0.4 V VOHP 3.3 V output HIGH voltage PCI 3.135 to 3.465 IOH = –1 mA 2.4 – V VOLP 3.3 V output LOW voltage PCI 3.135 to 3.465 IOH = 1 mA – 0.55 V PCI, 3V66 3VMREF 3VMREF_BAR output HIGH current 3.135 VOUT = 1.0 V 3.465 VOUT = 3.135 V IOH O 48 MHz,, REF output HIGH current 3.135 VOUT = 1.0 V 3.465 VOUT = 3.135 V IOH O HOST/HOST_BAR _ OUTPUT CURRENT PCI, 3V66 3VMREF 3VMREF_BAR output LOW current 3.135 VOUT = 1.95 V IOL O 3.465 VOUT = 0.4 V IOL O 48 MHz,, REF output LOW current 3.135 VOUT = 1.95 V 3.465 VOUT = 0.4 V VOL HOST/HOST_BAR VSS = 0.0 Rs = 33.2 Ω Rp = 49.9 Ω 3.365 0 < VIN < VDD3 3.465 VOUT = VDD or GND IOH O ±II Input leakage current ±IOZ 3-State output OFF-State current Cin Input pin capacitance Cxtal Crystal input capacitance Cout Output pin capacitance 3 135 to 3 3.135 3.465 465 0.66 V 0.76 V Type y 5 12–55 Ω Type y 3 20–60 Ω Type X1 y 5 Type 12–55 Ω –33 mA –33 –29 –23 –11 30 mA 38 Type y 3 20–60 Ω 29 Type X1 0.0 0.05 V –5 5 µA 10 µA 5 pF 22.5 pF 6 pF 27 IO = 0 13.5 8 mA –12.7 NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section. 2000 Nov 13 mA mA Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 AC CHARACTERISTICS VDD3 = 3.3 V –5%; fcrystal = 14.31818 MHz HOST CLOCK OUTPUTS (SEE FIGURE 1 FOR WAVEFORMS AND FIGURE 6 FOR TEST SETUP) LIMITS Tamb = 0°C to +70°C SYMBOL PARAMETER MIN MAX MIN MAX TPKP HOST CLK period 7.5 7.65 10.0 AbsMinPeriod Absolute Minimum Host CLK Period 7.35 N/A 9.85 TRISE HOST CLK rise time 175 700 TFALL HOST CLK fall time 175 700 TJITTER HOST CLK cycle-to-cycle jitter DUTY CYCLE Output duty cycle TSKEW HOST CLK pin-to-pin skew Rise/Fall Matching Rise and fall time matching Vcrossover 133 MHz MODE UNITS NOTES 10.2 ns 11, 14, 20 N/A ns 11, 14, 20 175 700 ps 11, 15, 20 175 700 ps 11, 15, 20 200 ps 11, 12, 14, 20 55 % 11, 14, 20 150 ps 11, 14, 20 100 MHZ MODE 200 45 55 45 150 35% 45% VOH 60% VOH 35% 45% VOH 60% VOH 11, 16, 20 V 11, 14, 20 MREF OUTPUTS LIMITS Tamb = 0°C to +70°C SYMBOL PARAMETER MIN MAX MIN MAX TPKP MREF period 15.0 15.3 20.0 TPKH MREF HIGH time 5.25 N/A TPKL MREF LOW time 5.05 N/A TRISE MREF rise time 0.5 0.5 TFALL MREF fall time TJITTER Cycle-to-cycle jitter DUTY CYCLE Output Duty Cycle UNITS NOTES 20.4 ns 2, 9, 20 7.5 N/A ns 5, 10, 20 7.3 N/A ns 6, 10, 20 2.0 0.5 2.0 ns 8, 20 2.0 0.5 133 MHz MODE 100 MHz MODE 250 45 55 45 2.0 ns 8, 20 250 ps 18, 20 55 % 18, 20 UNIT NOTES 3V66 OUTPUTS LIMITS Tamb = 0°C to +70°C SYMBOL PARAMETER MIN MAX MIN MAX TPKP 3V66 period 15.0 16.0 15.0 16.0 ns 2, 4, 9, 20 TPKH 3V66 HIGH time 5.25 N/A 5.25 N/A ns 5, 10, 20 133 MHz MODE 100 MHz MODE TPKL 3V66 LOW time 5.05 N/A 5.05 N/A ns 6, 10, 20 TRISE 3V66 rise time 0.5 2.0 0.5 2.0 ns 8, 20 TFALL 3V66 fall time 0.5 2.0 0.5 2.0 ns 8, 20 300 ps 18, 20 55 % 18, 20 250 ps 20 TJITTER Cycle-to-cycle jitter DUTY CYCLE Output Duty Cycle TSKEW Pin-to-pin skew 2000 Nov 13 300 45 55 250 9 45 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 PCI OUTPUTS SYMBOL PARAMETER LIMITS Tamb = 0°C to +70°C 133 MHz MODE 100 MHz MODE MIN MAX MIN MAX UNITS NOTES TPKP PCI period 30.0 N/A 30.0 N/A ns 2, 3, 9, 20 TPKH PCI HIGH time 12.0 N/A 12.0 N/A ns 5, 10, 20 TPKL PCI LOW time 12.0 N/A 12.0 N/A ns 6, 10, 20 TRISE PCI rise time 0.5 2.0 0.5 2.0 ns 8, 20 TFALL PCI fall time 0.5 2.0 0.5 2.0 ns 8, 20 TJITTER Cycle-to-cycle jitter 500 ps 18, 20 DUTY CYCLE Output Duty Cycle 55 % 18, 20 TSKEW Pin-to-pin skew 500 ps 18, 20 500 45 55 45 500 USB CLOCK OUTPUT, 48 MHz (LUMP CAPACITANCE TEST LOAD = 20 pF) SYMBOL LIMITS Tamb = 0°C to +70°C PARAMETER UNITS 48 MHz MIN MAX MIN NOTES MAX f Frequency, Actual 48.008 fD Deviation from 48 MHz +167 MHz THKL 3V48MHZCLK LOW time 5.05 N/A 5.05 N/A ns 20 TRISE 3V48MHZCLK rise time 1.0 4.0 1.0 4.0 ns 8, 20 TFALL 3V48MHZCLK fall time 1.0 4.0 1.0 4.0 ns 8, 20 TJITTER Cycle-to-cycle jitter 350 ps 18, 20 DUTY CYCLE Output Duty Cycle 55 % 18, 20 UNITS NOTES ppm 350 45 55 45 REF CLOCK OUTPUT, (LUMP CAPACITANCE TEST LOAD = 20 pF) SYMBOL LIMITS Tamb = 0°C to +70°C PARAMETER 48 MHz MIN MAX MIN MAX f Frequency, Actual MHz 20 THKL REF CLK LOW time 31.0 36.67 14.318 31.0 36.67 ns 20 THKH REF CLK HIGH time 32.0 37.5 32.0 37.5 ns 20 TRISE REF CLK rise time N/A N/A N/A N/A ns 8, 20 TFALL REF CLK fall time N/A N/A N/A N/A ns 8, 20 TJITTER Cycle-to-cycle jitter 1000 ps 18, 20 DUTY CYCLE Output Duty Cycle 55 % 18, 20 1000 45 55 45 ALL OUTPUTS LIMITS Tamb = 0°C to +70°C SYMBOL PARAMETER MIN MAX MIN MAX TpZL, tpZH Output enable delay (all outputs) 1.0 10.0 1.0 TpLZ, tpZH Output disable delay (all outputs) 1.0 10.0 1.0 TSTABLE All clock Stabilization from Power-up 2000 Nov 13 133 MHz MODE 3 10 UNITS NOTES 10.0 ns 20 10.0 ns 20 3 ms 7, 20 100 MHz MODE Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 GROUP OFFSET LIMITS GROUP OFFSET MEASUREMENT LOADS (LUMPED) MEASURE POINTS NOTES 3V66 to PCI 1.5–3.5 ns 3V66 leads 3V66 @ 30 pf PCI @ 30 pf 3V66 @ 1.5 V PCI @ 1.5 V 19, 20 NOTES: 1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels. 2. Period, jitter, offset and skew measured on rising edge @ 1.25 V for 2.5 V clocks and @ 1.5 V for 3.3 V clocks. 3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the Host clock divided by three at Host = 100 MHz. 4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided by three at Host = 100 MHz. 5. THKH is measured at 2.0 V for 2.5 V outputs and 2.4 V for 3.3 V outputs as shown in Figure 7. 6. THKL is measured at 0.4 V for all outputs as shown in Figure 7. 7. The time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 8. THRISE and THFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 9. The average period over any 1 µs period of time must be greater than the minimum specified period. 10. Calculated at minimum edge-rate (1 V/ns) to guarantee 45/55% duty-cycle. Pulse width is required to be wider at faster edge-rate to ensure duty-cycle specification is met. 11. Test load is Rs = 33.2 Ω, Rp = 49.9 Ω. 12. Must be guaranteed in a realistic system environment. 13. Configured for VOH = 0.71 V in a 50 Ω environment. 14. Measured at crossing points. 15. Measured at 20% to 80%. 16. Determined as a fraction of 2* (Trp–Trn)/(Trp+Trn) where Trp is a rising edge and Trn is an intersecting falling edge. 17. Voltage measure point (Vm = 1.25 V). VDD = 2.5 V. 18. Voltage measure point (Vm = 1.5 V). VDD = 3.3 V. 19. All offsets are to be measured at rising edges. 20. Parameters are guaranteed by design. 2000 Nov 13 11 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 AC WAVEFORMS VI VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH –0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. SEL1, SEL0 VM GND tPLZ VDD VDDQ2 OUTPUT LOW-to-OFF OFF-to-LOW 1.25V CPUCLK @133MHz tPZL VSS VM VX VOL tPHZ VDDQ3 3v66 @66MHz tPZH VOH 1.5V VY OUTPUT HIGH-to-OFF OFF-to-HIGH VSS CPU leads 3V66 VSS THPOFFSET SW00569 VM Outputs enabled Outputs disabled SW00571 Figure 1. Host clock Figure 3. State enable and disable times COMPONENT MEASUREMENT POINTS 2.5VOLT MEASURE POINTS VOH = 2.0V VOL = 0.4V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS VSS COMPONENT MEASUREMENT POINTS 3.3VOLT MEASURE POINTS VOH = 2.4V VOL = 0.4V VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V VSS SYSTEM MEASUREMENT POINTS SW00570 Figure 2. 3.3 V clock waveforms 2000 Nov 13 Outputs enabled 12 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 S1 VDD 2<VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. RT CL TEST 500Ω S1 tPLH/tPHL Open tPLZ/tPZL 2<VDD tPHZ/tPZH VSS VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT SW00572 Figure 4. Load circuitry for switching times PWRDWN CPUCLK (INTERNAL) PCICLK (INTERNAL) PWRDWN CPUCLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO USB (48 MHz) ÁÁ ÁÁ ÁÁ Figure 5. Power management 2000 Nov 13 13 SW00573 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 S1 VDD 2<VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. RT 500Ω CL TEST S1 tPLH/tPHL Open tPLZ/tPZL 2<VDD tPHZ/tPZH VSS VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT SW00574 Figure 6. Host clock measurements THKP DUTY CYCLE THKH 2.5 V CLOCKING INTERFACE 2.0 V 1.25 V 0.4 V THKL TRISE TFALL TPKP DUTY CYCLE TPKH 3.3 V CLOCKING INTERFACE (TTL) 2.4 V 1.5 V 0.4 V TPKL TRISE TFALL Figure 7. 2.5 V/3.3 V clock waveforms 2000 Nov 13 14 SW00575 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 2000 Nov 13 15 SOT371-1 Philips Semiconductors Product specification CK00 (100/133MHz) spread spectrum differential system clock generator PCK2020 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 11-00 Document order number: 2000 Nov 13 16 9397 750 07818